+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity bus_async_trans is
- generic (
- BUS_WIDTH : integer range 2 to 32 := 8;
- NUM_FF : integer range 2 to 4 := 2
- );
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- SIGNAL_A_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
- SIGNAL_OUT : out std_logic_vector(BUS_WIDTH - 1 downto 0)
- );
-
-end entity;
-
-architecture Behavioral of bus_async_trans is
- type buffer_t is array(0 to NUM_FF - 1) of
- std_logic_vector(BUS_WIDTH - 1 downto 0);
- signal signal_ff : buffer_t;
-
-begin
-
- -----------------------------------------------------------------------------
- -- Clock CLK_IN Domain
- -----------------------------------------------------------------------------
-
- PROC_SYNC_SIGNAL: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- signal_ff(NUM_FF - 1) <= SIGNAL_A_IN;
- if( RESET_IN = '1' ) then
- for i in NUM_FF - 2 downto 0 loop
- signal_ff(i) <= (others => '0');
- end loop;
- else
- for i in NUM_FF - 2 downto 0 loop
- signal_ff(i) <= signal_ff(i + 1);
- end loop;
- end if;
- end if;
- end process PROC_SYNC_SIGNAL;
-
- -- Output Signals
- SIGNAL_OUT <= signal_ff(0);
-
-end Behavioral;
slv_no_more_data_o <= '0';
slv_unknown_addr_o <= '0';
slv_ack_o <= '0';
- port_select <= (others => '0');
+ port_select <= x"00";
else
slv_ack_o <= '1';
slv_unknown_addr_o <= '0';
end entity;
architecture Behavioral of level_to_pulse is
-
- type STATES is (IDLE,
- WAIT_LOW
- );
- signal STATE, NEXT_STATE : STATES;
-
+ signal signal_ff : std_logic_vector(1 downto 0);
signal pulse_o : std_logic;
begin
- PROC_CONVERT_TRANSFER:process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
- STATE <= IDLE;
- else
- STATE <= NEXT_STATE;
- end if;
- end if;
- end process PROC_CONVERT_TRANSFER;
-
-
- PROC_CONVERT: process(STATE,
- LEVEL_IN
- )
- begin
-
- case STATE is
- when IDLE =>
- if (LEVEL_IN = '1') then
- pulse_o <= '1';
- NEXT_STATE <= WAIT_LOW;
- else
- pulse_o <= '0';
- NEXT_STATE <= IDLE;
- end if;
-
- when WAIT_LOW =>
- pulse_o <= '0';
- if (LEVEL_IN = '0') then
- NEXT_STATE <= IDLE;
- else
- NEXT_STATE <= WAIT_LOW;
- end if;
-
- end case;
-
- end process PROC_CONVERT;
+ signal_ff(1) <= LEVEL_IN when rising_edge(CLK_IN);
+ signal_ff(0) <= signal_ff(1) when rising_edge(CLK_IN);
+ pulse_o <= '1' when signal_ff = "10" and RESET_IN = '0' else '0';
- -- Output Signals
+ -- Output Signals
PULSE_OUT <= pulse_o;
end Behavioral;
0x8b80 : r/w Overflow Rate num averages (3 Bit)
0x8b81 : r/w Overflow Rate average enable
--- Debug Multiplexer
-0x8020 : r/w Select Debug Entity
- 0: nx_status
- 1: nx_register_setup
- 2: nx_i2c_master
- 3: adc_spi_master
- 4: nx_fpga_timestamp
- 5: nx_trigger_handler
- 6: nx_trigger_generator
- 7: nx_data_receiver
- 8: nx_data_delay
- 9: nx_data_validate
- 10: nx_trigger_validate
- 11: nx_event_buffer
- 12: nx_histograms
- 13: nx_status_event
- 14: Checkerboard
-
---- Trigger Selction Window Setup
- _
-Physics Trigger [PT] _______________| |___________________________________
- _
-NX_TS_Trigger [NXT] ____________________| |______________________________
- _
-CTS Trigger [CT] _____________________________________| |_____________
- _
-FPGA TS Trigger [FT] _________________________________________| |_________
- |
-CTS+FPGA Trigger Delay |--------------------|
- |
-FPGA TS-Ref stored |
-in Event Header -----------|--------------------|
- |
-Trigger Window Offset(-) |----------| |
-Trigger Window Width(-) |----------------| |
-Timestamps stored in Event(-) |--|---|--|-||--|---------------|
- | |
- | |
-Trigger Window Offset(+) |-----| |
-Trigger Window Width(+) |---------| |
-Timestamps stored in Event(+) -----------------|--||--|-|-----|
- ---------------------------------------------------------------> Time t
+-- Latch Handler
+0x8180 : r/w Latch Select
+ 0: CTS Timing Trigger
+ 1: External Latch
+-- Scaler Channel #0
+0x8000 : r/w Counter Offset(16 Bit)
+0x8001 : r Counter Latched Low (32 Bit)
+0x8002 : r Counter Latched High (16 Bit)
+-- Debug Multiplexer
+0x8200 : r/w Select Debug Entity
+ 0: Scaler Channel 0
+ 1: Trigger Handler
+ 2: Latch Handler
##############################################################################
-# nXyter FEB Clock Setup:
+# Clock Setup:
#
# CLK_PCLK_RIGHT : real Oszillator 200MHz
# CLK_PCLK_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities
#
-# CLK_PCLK_RIGHT --> nx_main_clk 1+2
-# (250 MHz) -----> nXyter Main Clock 1+2
-# |
-# |----> FPGA Timestamp Entity 1+2
-#
-# nx_main_clk 1+2 --> nXyter Data Clk
-# (1/2 = 125MHz) -----> FPGA Data Receiver
-# |
-# |----> Johnson 1/4 --> ADC SCLK
-#
-# CLK_PCLK_RIGHT (PLL#2) --> clk_adc_dat_1
-# (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 1
-#
-# CLK_PCLK_RIGHT (PLL#3) --> clk_adc_dat_2
-# (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 2
-
+# CLK_PCLK_RIGHT --> PLL#1 --> clk_scaler -----> 400 MHz Clock Domain
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-
+
+ -- Resets
+ signal reset_d1_ff : std_logic_vector(1 downto 0);
+ signal RESET_D1 : std_logic;
+
-- Bus Handler
- constant NUM_PORTS : integer := 3;
+ constant NUM_PORTS : integer := 4;
signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0);
signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0);
signal adc_tr_error : std_logic;
signal nx_token_return : std_logic;
signal nx_nomore_data : std_logic;
-
+
+ -- Latch Handler
+ signal reset_ctr : std_logic;
+ signal latch : std_logic;
+ signal latch_valid : std_logic;
+ signal latch_invalid : std_logic;
+
-- Trigger Validate
signal trigger_data : std_logic_vector(31 downto 0);
signal trigger_data_clk : std_logic;
signal error_event_buffer : std_logic;
-- Debug Handler
- constant DEBUG_NUM_PORTS : integer := 2; -- 14
+ constant DEBUG_NUM_PORTS : integer := 3; -- 14
signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1);
----------------------------------------------------------------------
-- Testing Delay
----------------------------------------------------------------------
- signal clock_div : unsigned(11 downto 0);
+ signal clock_div : unsigned(15 downto 0);
signal clk_pulse : std_logic;
- signal pulse : std_logic;
signal latch_i : std_logic;
- signal latch : std_logic;
+ signal latch_ff : std_logic_vector(2 downto 0);
- signal scaler_counter : unsigned(11 downto 0);
- signal input_pulse : std_logic;
- signal INPUT : std_logic;
+ attribute syn_keep : boolean;
+ attribute syn_keep of reset_d1_ff : signal is true;
+ attribute syn_keep of latch_ff : signal is true;
- signal debug_test : std_logic_vector(15 downto 0);
-
- ----------------------------------------------------------------------
- -- Reset
- ----------------------------------------------------------------------
+ attribute syn_preserve : boolean;
+ attribute syn_preserve of reset_d1_ff : signal is true;
+ attribute syn_preserve of latch_ff : signal is true;
- signal RESET_SCALER_CLK_IN : std_logic;
-
begin
+
+ -----------------------------------------------------------------------------
+ -- Reset Domain Transfer
+ -----------------------------------------------------------------------------
- RESET_SCALER_CLK_IN <= RESET_IN;
+ reset_d1_ff(1) <= RESET_IN when rising_edge(CLK_D1_IN);
+ reset_d1_ff(0) <= reset_d1_ff(1) when rising_edge(CLK_D1_IN);
+ RESET_D1 <= reset_d1_ff(0);
--------------------------------------------------------------------------------
--- Port Maps
--------------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- Port Maps
+ ----------------------------------------------------------------------------
THE_BUS_HANDLER: trb_net16_regio_bus_handler
generic map(
PORT_ADDRESSES => (0 => x"0200", -- Debug Multiplexer
1 => x"0000", -- Scaler Channel 0
2 => x"0160", -- Trigger Handler
+ 3 => x"0180", -- Latch Handler
--2 => x"0040", -- Scaler Channel 2
--3 => x"0060", -- Scaler Channel 3
--4 => x"0080", -- Scaler Channel 4
PORT_ADDR_MASK => (0 => 0, -- Debug Multiplexer
1 => 2, -- Scaler Channel 0
- 7 => 4, -- Trigger Handler
+ 2 => 4, -- Trigger Handler
+ 3 => 4, -- Latch Handler
--2 => 2, -- Scaler Channel 2
--3 => 2, -- Scaler Channel 3
--4 => 2, -- Scaler Channel 4
clock_div <= (others => '0');
clk_pulse <= '0';
else
- if (clock_div < x"00f") then -- x"3e8"
+ if (clock_div < x"64") then -- 1mus
clk_pulse <= '0';
clock_div <= clock_div + 1;
else
clk_pulse <= '1';
- clock_div <= (others => '0');
+ clock_div <= x"0001";
end if;
end if;
end if;
end process PROC_CLOCK_DIVIDER;
- latch_i <= clk_pulse;
- pulse <= CLK_IN;
+-- latch_ff(2) <= CHANNELS_IN(1) when rising_edge(CLK_D1_IN);
+-- latch_ff(1) <= latch_ff(2) when rising_edge(CLK_D1_IN);
+-- latch_ff(0) <= latch_ff(1) when rising_edge(CLK_D1_IN);
+-- latch_i <= '1' when latch_ff(1 downto 0) = "10" else '0';
+
+ latch_handler_1: latch_handler
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ CLK_D1_IN => CLK_D1_IN,
+ RESET_D1_IN => RESET_D1,
+ RESET_CTR_IN => CHANNELS_IN(7),
+ LATCH_TRIGGER_IN => clk_pulse, -- TIMING_TRIGGER_IN, -- latch_i,
+ LATCH_EXTERN_IN => TIMING_TRIGGER_IN,
+ RESET_CTR_OUT => reset_ctr,
+ LATCH_OUT => latch,
+ LATCH_VALID_OUT => latch_valid,
+ LATCH_INVALID_OUT => latch_invalid,
+ SLV_READ_IN => slv_read(3),
+ SLV_WRITE_IN => slv_write(3),
+ SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),
+ SLV_DATA_IN => slv_data_wr(3*32+31 downto 3*32),
+ SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16),
+ SLV_ACK_OUT => slv_ack(3),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(3),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3),
+ DEBUG_OUT => debug_line(2)
+ );
+
scaler_channel_0: scaler_channel
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
CLK_D1_IN => CLK_D1_IN,
- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
- LATCH_IN => latch_i, --LATCH_IN,
+ RESET_D1_IN => RESET_D1,
+
+ RESET_CTR_IN => reset_ctr,
+ LATCH_IN => latch,
PULSE_IN => CHANNELS_IN(0),
- PULSE_INTERNAL_IN => pulse,
INHIBIT_IN => '0',
SLV_READ_IN => slv_read(1),
SLV_ADDR_IN => slv_addr(1*16+15 downto 1*16),
SLV_ACK_OUT => slv_ack(1),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(1),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
DEBUG_OUT => debug_line(0)
);
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- NX_MAIN_CLK_IN => CLK_IN,
+ CLK_D1_IN => CLK_D1_IN,
+ RESET_D1_IN => RESET_D1,
OFFLINE_IN => not nxyter_online,
TIMING_TRIGGER_IN => TIMING_TRIGGER_IN,
DEBUG_OUT => debug_line(1)
);
- -- scaler_channel_1: scaler_channel
- -- port map (
- -- CLK_IN => CLK_IN,
- -- RESET_IN => RESET_IN,
- -- CLK_SCALER_IN => CLK_SCALER_1_IN,
- -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
- -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
- -- PULSE_IN => SCALER_CHANNELS_IN(1),
- -- PULSE_INTERNAL_IN => pulse,
- -- INHIBIT_IN => '0',
- --
- -- SLV_READ_IN => slv_read(1),
- -- SLV_WRITE_IN => slv_write(1),
- -- SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
- -- SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
- -- SLV_ADDR_IN => slv_addr(1*16+15 downto 1*16),
- -- SLV_ACK_OUT => slv_ack(1),
- -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(1),
- -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
- --
- -- DEBUG_OUT => open
- -- );
- --
- -- scaler_channel_2: scaler_channel
- -- port map (
- -- CLK_IN => CLK_IN,
- -- RESET_IN => RESET_IN,
- -- CLK_SCALER_IN => CLK_SCALER_1_IN,
- -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
- -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
- -- PULSE_IN => SCALER_CHANNELS_IN(2),
- -- PULSE_INTERNAL_IN => pulse,
- -- INHIBIT_IN => '0',
- --
- -- SLV_READ_IN => slv_read(2),
- -- SLV_WRITE_IN => slv_write(2),
- -- SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
- -- SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),
- -- SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16),
- -- SLV_ACK_OUT => slv_ack(2),
- -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
- -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
- --
- -- DEBUG_OUT => open
- -- );
- --
- -- scaler_channel_3: scaler_channel
- -- port map (
- -- CLK_IN => CLK_IN,
- -- RESET_IN => RESET_IN,
- -- CLK_SCALER_IN => CLK_SCALER_1_IN,
- -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
- -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
- -- PULSE_IN => SCALER_CHANNELS_IN(3),
- -- PULSE_INTERNAL_IN => pulse,
- -- INHIBIT_IN => '0',
- --
- -- SLV_READ_IN => slv_read(3),
- -- SLV_WRITE_IN => slv_write(3),
- -- SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),
- -- SLV_DATA_IN => slv_data_wr(3*32+31 downto 3*32),
- -- SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16),
- -- SLV_ACK_OUT => slv_ack(3),
- -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(3),
- -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3),
- --
- -- DEBUG_OUT => open
- -- );
- --
- -- scaler_channel_4: scaler_channel
- -- port map (
- -- CLK_IN => CLK_IN,
- -- RESET_IN => RESET_IN,
- -- CLK_SCALER_IN => CLK_SCALER_1_IN,
- -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
- -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
- -- PULSE_IN => SCALER_CHANNELS_IN(4),
- -- PULSE_INTERNAL_IN => pulse,
- -- INHIBIT_IN => '0',
- --
- -- SLV_READ_IN => slv_read(4),
- -- SLV_WRITE_IN => slv_write(4),
- -- SLV_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),
- -- SLV_DATA_IN => slv_data_wr(4*32+31 downto 4*32),
- -- SLV_ADDR_IN => slv_addr(4*16+15 downto 4*16),
- -- SLV_ACK_OUT => slv_ack(4),
- -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(4),
- -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4),
- --
- -- DEBUG_OUT => open
- -- );
- --
- -- scaler_channel_5: scaler_channel
- -- port map (
- -- CLK_IN => CLK_IN,
- -- RESET_IN => RESET_IN,
- -- CLK_SCALER_IN => CLK_SCALER_1_IN,
- -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
- -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
- -- PULSE_IN => SCALER_CHANNELS_IN(5),
- -- PULSE_INTERNAL_IN => pulse,
- -- INHIBIT_IN => '0',
- --
- -- SLV_READ_IN => slv_read(5),
- -- SLV_WRITE_IN => slv_write(5),
- -- SLV_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),
- -- SLV_DATA_IN => slv_data_wr(5*32+31 downto 5*32),
- -- SLV_ADDR_IN => slv_addr(5*16+15 downto 5*16),
- -- SLV_ACK_OUT => slv_ack(5),
- -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(5),
- -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5),
- --
- -- DEBUG_OUT => open
- -- );
- --
- -- scaler_channel_6: scaler_channel
- -- port map (
- -- CLK_IN => CLK_IN,
- -- RESET_IN => RESET_IN,
- -- CLK_SCALER_IN => CLK_SCALER_1_IN,
- -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
- -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
- -- PULSE_IN => SCALER_CHANNELS_IN(6),
- -- PULSE_INTERNAL_IN => pulse,
- -- INHIBIT_IN => '0',
- --
- -- SLV_READ_IN => slv_read(6),
- -- SLV_WRITE_IN => slv_write(6),
- -- SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32),
- -- SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32),
- -- SLV_ADDR_IN => slv_addr(6*16+15 downto 6*16),
- -- SLV_ACK_OUT => slv_ack(6),
- -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(6),
- -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6),
- --
- -- DEBUG_OUT => open
- -- );
- --
- -- scaler_channel_7: scaler_channel
- -- port map (
- -- CLK_IN => CLK_IN,
- -- RESET_IN => RESET_IN,
- -- CLK_SCALER_IN => CLK_SCALER_1_IN,
- -- RESET_SCALER_IN => RESET_SCALER_CLK_IN,
- -- LATCH_IN => latch, -- must be CLK_SCALER_IN domain
- -- PULSE_IN => SCALER_CHANNELS_IN(7),
- -- PULSE_INTERNAL_IN => pulse,
- -- INHIBIT_IN => '0',
- --
- -- SLV_READ_IN => slv_read(7),
- -- SLV_WRITE_IN => slv_write(7),
- -- SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),
- -- SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),
- -- SLV_ADDR_IN => slv_addr(7*16+15 downto 7*16),
- -- SLV_ACK_OUT => slv_ack(7),
- -- SLV_NO_MORE_DATA_OUT => slv_no_more_data(7),
- -- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(7),
- --
- -- DEBUG_OUT => open
- -- );
-------------------------------------------------------------------------------
-- DEBUG Line Select
CLK_IN : in std_logic;
RESET_IN : in std_logic;
CLK_D1_IN : in std_logic;
- RESET_SCALER_IN : in std_logic;
+ RESET_D1_IN : in std_logic;
+ RESET_CTR_IN : in std_logic;
LATCH_IN : in std_logic;
PULSE_IN : in std_logic;
- PULSE_INTERNAL_IN : in std_logic;
INHIBIT_IN : in std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end component;
-
+
+----------------------------------------------------------------------
+-- Latch Handler Entity
+----------------------------------------------------------------------
+ component latch_handler
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ CLK_D1_IN : in std_logic;
+ RESET_D1_IN : in std_logic;
+ RESET_CTR_IN : in std_logic;
+ LATCH_TRIGGER_IN : in std_logic;
+ LATCH_EXTERN_IN : in std_logic;
+ RESET_CTR_OUT : out std_logic;
+ LATCH_OUT : out std_logic;
+ LATCH_VALID_OUT : out std_logic;
+ LATCH_INVALID_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0));
+ end component;
+
-------------------------------------------------------------------------------
-- Trigger Handler
-------------------------------------------------------------------------------
-
component trigger_handler
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
- NX_MAIN_CLK_IN : in std_logic;
+ CLK_D1_IN : in std_logic;
+ RESET_D1_IN : in std_logic;
OFFLINE_IN : in std_logic;
TIMING_TRIGGER_IN : in std_logic;
LVL1_TRG_DATA_VALID_IN : in std_logic;
);
end component;
- component fifo_data_stream_44to44_dc
- port (
- Data : in std_logic_vector(43 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(43 downto 0);
- Empty : out std_logic;
- Full : out std_logic
- );
- end component;
-
- component fifo_44_data_delay_my
- port (
- Data : in std_logic_vector(43 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- AmEmptyThresh : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(43 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostEmpty : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
- end component;
-
- component nx_data_receiver
- generic (
- DEBUG_ENABLE : boolean);
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- TRIGGER_IN : in std_logic;
- NX_ONLINE_IN : in std_logic;
- NX_CLOCK_ON_IN : in std_logic;
- NX_DATA_CLK_IN : in std_logic;
- NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
- NX_TIMESTAMP_RESET_OUT : out std_logic;
- ADC_SAMPLE_CLK_OUT : out std_logic;
- ADC_SCLK_LOCK_OUT : out std_logic;
- ADC_FCLK_IN : in std_logic;
- ADC_DCLK_IN : in std_logic;
- ADC_A_IN : in std_logic;
- ADC_B_IN : in std_logic;
- ADC_NX_IN : in std_logic;
- ADC_D_IN : in std_logic;
- DATA_OUT : out std_logic_vector(43 downto 0);
- DATA_CLK_OUT : out std_logic;
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
- ADC_TR_ERROR_IN : in std_logic;
- DISABLE_ADC_OUT : out std_logic;
- ERROR_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
- end component;
-
- component nx_data_delay
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- DATA_IN : in std_logic_vector(43 downto 0);
- DATA_CLK_IN : in std_logic;
- DATA_OUT : out std_logic_vector(43 downto 0);
- DATA_CLK_OUT : out std_logic;
- FIFO_DELAY_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
- end component;
-
- component nx_data_validate
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- DATA_IN : in std_logic_vector(43 downto 0);
- DATA_CLK_IN : in std_logic;
- TIMESTAMP_OUT : out std_logic_vector(13 downto 0);
- CHANNEL_OUT : out std_logic_vector(6 downto 0);
- TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0);
- ADC_DATA_OUT : out std_logic_vector(11 downto 0);
- DATA_CLK_OUT : out std_logic;
- NX_TOKEN_RETURN_OUT : out std_logic;
- NX_NOMORE_DATA_OUT : out std_logic;
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
- ADC_TR_ERROR_OUT : out std_logic;
- DISABLE_ADC_IN : in std_logic;
- ERROR_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
- end component;
-
component nx_trigger_validate
generic (
BOARD_ID : std_logic_vector(1 downto 0);
-- attribute HGROUP : string;
-- attribute HGROUP of Behavioral : architecture is "SIGNAL_ASYNC_TO_PULSE";
- signal pulse_ff : std_logic_vector(NUM_FF - 1 downto 0);
+ signal pulse_ff : std_logic_vector(NUM_FF downto 0);
signal pulse_o : std_logic;
attribute syn_keep : boolean;
-- Clock CLK_IN Domain
-----------------------------------------------------------------------------
- PROC_SYNC_PULSE: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- pulse_ff(NUM_FF - 1) <= PULSE_A_IN;
- for i in NUM_FF - 2 downto 0 loop
- pulse_ff(i) <= pulse_ff(i + 1);
- end loop;
- end if;
- end process PROC_SYNC_PULSE;
-
- level_to_pulse_1: level_to_pulse
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- LEVEL_IN => pulse_ff(0),
- PULSE_OUT => pulse_o
- );
+ pulse_ff(NUM_FF) <= PULSE_A_IN when rising_edge(CLK_IN);
+ L1: for I in (NUM_FF - 1) downto 0 generate
+ pulse_ff(I) <= pulse_ff(I + 1) when rising_edge(CLK_IN);
+ end generate L1;
+ pulse_o <= '1' when pulse_ff(1 downto 0) = "10" and RESET_IN = '0' else '0';
+
-- Outputs
PULSE_OUT <= pulse_o;
architecture Behavioral of signal_async_trans is
type signal_ff_t is array(0 to NUM_FF - 1) of std_logic;
- signal signal_ff : signal_ff_t;
+ signal signal_ff : signal_ff_t;
attribute syn_keep : boolean;
attribute syn_keep of signal_ff : signal is true;
-- Clock CLK_IN Domain
-----------------------------------------------------------------------------
- PROC_SYNC_SIGNAL: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- signal_ff(NUM_FF - 1) <= SIGNAL_A_IN;
- for i in NUM_FF - 2 downto 0 loop
- signal_ff(i) <= signal_ff(i + 1);
- end loop;
- end if;
- end process PROC_SYNC_SIGNAL;
-
+ signal_ff(NUM_FF - 1) <= SIGNAL_A_IN when rising_edge(CLK_IN);
+
+ L1: for I in (NUM_FF - 2) downto 0 generate
+ signal_ff(I) <= signal_ff(I + 1) when rising_edge(CLK_IN);
+ end generate L1;
+
-- Output Signals
SIGNAL_OUT <= signal_ff(0);
#even numbers are positive LVDS line, odd numbers are negative LVDS line
#DQUL can be switched to 1.8V
-
-
-# Scaler
-#LOCATE COMP "NX1_MAIN_CLK_OUT" SITE "AB1"; #DQLL2_2 #29
-#LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45
-#LOCATE COMP "NX1_DATA_CLK_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-
-
-#LOCATE COMP "NX1_SPI_SDIO_INOUT" SITE "G2"; #DQUL1_0 #73
-#LOCATE COMP "NX1_SPI_SCLK_OUT" SITE "F2"; #DQUL1_2 #77
-#LOCATE COMP "NX1_SPI_CSB_OUT" SITE "C2"; #DQUL1_4 #81
-
-
-LOCATE COMP "SCALER_LATCH_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE
-LOCATE COMP "SCALER_CHANNELS_IN_0" SITE "K2"; #DQUL2_0 #50
-LOCATE COMP "SCALER_CHANNELS_IN_1" SITE "J4"; #DQUL2_2 #54
-LOCATE COMP "SCALER_CHANNELS_IN_2" SITE "D1"; #DQUL2_4 #58
-LOCATE COMP "SCALER_CHANNELS_IN_3" SITE "E1"; #DQUL2_6 #66
-#LOCATE COMP "SCALER_CHANNELS_IN_6" SITE "L5"; #DQUL2_8 #70
-LOCATE COMP "SCALER_CHANNELS_IN_4" SITE "L2"; #DQUL3_6 #
-
-LOCATE COMP "SCALER_CHANNELS_IN_5" SITE "H2"; #DQUL3_0 #49
-LOCATE COMP "SCALER_CHANNELS_IN_6" SITE "K3"; #DQUL3_2 #53
-LOCATE COMP "SCALER_CHANNELS_IN_7" SITE "H1"; #DQUL3_4 #57
-
-#LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46
-
-
-#DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP*" ;
-#IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-
-#DEFINE PORT GROUP "LVDS_group2" "NX1_ADC*IN" ;
-#IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25;
-#
-#IOBUF PORT "NX1_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-#IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=LVDS25;
-#IOBUF PORT "NX1_MAIN_CLK_OUT" IO_TYPE=LVDS25;
-#IOBUF PORT "NX1_RESET_OUT" IO_TYPE=LVDS25;
-#
-#IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
-#IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-#IOBUF PORT "NX1_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-#IOBUF PORT "NX1_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-#
-#IOBUF PORT "NX1_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
-#IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
-#IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
-
-# Nxyter Debug Lines Addon Board
-#LOCATE COMP "SCALER_DEBUG_LINE_1" SITE "R25"; #DQLR2_0 #170
-#LOCATE COMP "SCALER_DEBUG_LINE_3" SITE "R26"; #DQLR2_1 #172
-#LOCATE COMP "SCALER_DEBUG_LINE_5" SITE "T25"; #DQLR2_2 #174
-#LOCATE COMP "SCALER_DEBUG_LINE_7" SITE "T24"; #DQLR2_3 #176
-#LOCATE COMP "SCALER_DEBUG_LINE_9" SITE "T26"; #DQLR2_4 #178
-#LOCATE COMP "SCALER_DEBUG_LINE_11" SITE "U26"; #DQLR2_5 #180
-#LOCATE COMP "SCALER_DEBUG_LINE_13" SITE "U24"; #DQLR2_6 #186
-#LOCATE COMP "SCALER_DEBUG_LINE_15" SITE "V24"; #DQLR2_7 #188
-#LOCATE COMP "SCALER_DEBUG_LINE_14" SITE "W23"; #DQLR1_0 #169
-#LOCATE COMP "SCALER_DEBUG_LINE_12" SITE "W22"; #DQLR1_1 #171
-#LOCATE COMP "SCALER_DEBUG_LINE_10" SITE "AA25"; #DQLR1_2 #173
-#LOCATE COMP "SCALER_DEBUG_LINE_8" SITE "Y24"; #DQLR1_3 #175
-#LOCATE COMP "SCALER_DEBUG_LINE_6" SITE "AA26"; #DQLR1_4 #177
-#LOCATE COMP "SCALER_DEBUG_LINE_4" SITE "AB26"; #DQLR1_5 #179
-#LOCATE COMP "SCALER_DEBUG_LINE_2" SITE "AA24"; #DQLR1_6 #185
-#LOCATE COMP "SCALER_DEBUG_LINE_0" SITE "AA23"; #DQLR1_7 #187
-
-#DEFINE PORT GROUP "NX1_DEBUG_LINE_group" "NX1_DEBUG_LINE_*" ;
-#IOBUF GROUP "NX1_DEBUG_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST;
+#################################################################
+# Scaler Inputs
+#################################################################
+
+LOCATE COMP "CHANNELS_NIM_IN_0" SITE "AE25"; # CHO1
+LOCATE COMP "CHANNELS_NIM_IN_1" SITE "AD24"; # CHO2
+LOCATE COMP "CHANNELS_NIM_IN_2" SITE "Y22"; # CHO31
+LOCATE COMP "CHANNELS_NIM_IN_3" SITE "AB24"; # CHO32
+LOCATE COMP "CHANNELS_NIM_IN_4" SITE "N5"; # CHO41
+LOCATE COMP "CHANNELS_NIM_IN_5" SITE "AC2"; # CHO42
+LOCATE COMP "CHANNELS_NIM_IN_6" SITE "P5"; # CHO43
+LOCATE COMP "CHANNELS_NIM_IN_7" SITE "N3"; # CHO44
+LOCATE COMP "CHANNELS_ECL_IN_0" SITE "Y19"; # OUT1
+LOCATE COMP "CHANNELS_ECL_IN_1" SITE "AC26"; # OUT2
+LOCATE COMP "CHANNELS_ECL_IN_2" SITE "F25"; # OUT3
+LOCATE COMP "CHANNELS_ECL_IN_3" SITE "K23"; # OUT4
+LOCATE COMP "CHANNELS_ECL_IN_4" SITE "K8"; # OUT5
+LOCATE COMP "CHANNELS_ECL_IN_5" SITE "H5"; # OUT6
+LOCATE COMP "CHANNELS_ECL_IN_6" SITE "K7"; # OUT7
+LOCATE COMP "CHANNELS_ECL_IN_7" SITE "C2"; # OUT8
+LOCATE COMP "CHANNELS_ECL_IN_8" SITE "F2"; # OUT9
+LOCATE COMP "CHANNELS_ECL_IN_9" SITE "G2"; # OUT10
+LOCATE COMP "CHANNELS_ECL_IN_10" SITE "M3"; # OUT11
+LOCATE COMP "CHANNELS_ECL_IN_11" SITE "L2"; # OUT12
+LOCATE COMP "CHANNELS_ECL_IN_12" SITE "H2"; # OUT13
+LOCATE COMP "CHANNELS_ECL_IN_13" SITE "V6"; # OUT14
+LOCATE COMP "CHANNELS_ECL_IN_14" SITE "Y5"; # OUT15
+LOCATE COMP "CHANNELS_ECL_IN_15" SITE "W7"; # OUT16
+
+DEFINE PORT GROUP "CHANNELS_group" "CHANNELS_*" ;
+IOBUF GROUP "CHANNELS_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ;
#################################################################
# Additional Lines to AddOn
#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+LOCATE COMP "LEDR_OUT_0" SITE "U24";
+LOCATE COMP "LEDR_OUT_1" SITE "V21";
+LOCATE COMP "LEDR_OUT_2" SITE "T26";
+LOCATE COMP "LEDR_OUT_3" SITE "U23";
+LOCATE COMP "LEDG_OUT_0" SITE "W21";
+LOCATE COMP "LEDG_OUT_1" SITE "AA26";
+LOCATE COMP "LEDG_OUT_2" SITE "AA25";
+LOCATE COMP "LEDG_OUT_3" SITE "W23";
+LOCATE COMP "LEDG_OUT_4" SITE "AA24";
+LOCATE COMP "LEDG_OUT_5" SITE "AD26";
+LOCATE COMP "LEDG_OUT_6" SITE "T25";
+#Ports are defined with the other LEDs on trb3
#################################################################
# Flash ROM and Reboot
-w
-i 2
-l 5
--n 2
+-n 4
-t 10
-s 1
-c 1
# nXyter Files
add_file -vhdl -lib "work" "cores/pll_clk400.vhd"
+add_file -vhdl -lib "work" "cores/pll_quadruple.vhd"
add_file -vhdl -lib "work" "cores/counter_45bit.vhd"
-add_file -vhdl -lib "work" "cores/fifo_5to5_dc.vhd"
+add_file -vhdl -lib "work" "cores/fifo_6to6_dc.vhd"
add_file -vhdl -lib "work" "../base/code/sedcheck.vhd"
add_file -vhdl -lib "work" "trb3_periph_scaler.vhd"
add_file -vhdl -lib "work" "source/scaler_components.vhd"
+add_file -vhdl -lib "work" "source/signal_async_trans.vhd"
+add_file -vhdl -lib "work" "source/signal_async_to_pulse.vhd"
add_file -vhdl -lib "work" "source/level_to_pulse.vhd"
-add_file -vhdl -lib "work" "source/pulse_to_level.vhd"
add_file -vhdl -lib "work" "source/pulse_dtrans.vhd"
-add_file -vhdl -lib "work" "source/signal_async_to_pulse.vhd"
-add_file -vhdl -lib "work" "source/signal_async_trans.vhd"
-add_file -vhdl -lib "work" "source/bus_async_trans.vhd"
+add_file -vhdl -lib "work" "source/pulse_to_level.vhd"
add_file -vhdl -lib "work" "source/pulse_delay.vhd"
add_file -vhdl -lib "work" "source/timer.vhd"
add_file -vhdl -lib "work" "source/timer_static.vhd"
add_file -vhdl -lib "work" "source/scaler.vhd"
add_file -vhdl -lib "work" "source/scaler_channel.vhd"
add_file -vhdl -lib "work" "source/trigger_handler.vhd"
+add_file -vhdl -lib "work" "source/latch_handler.vhd"
#add_file -vhdl -lib "work" "source/nx_data_receiver.vhd"
#add_file -vhdl -lib "work" "source/nx_data_delay.vhd"
#add_file -vhdl -lib "work" "source/nx_data_validate.vhd"
---------------------------------------------------------------------------
-- BEGIN AddonBoard Scaler
---------------------------------------------------------------------------
- --Connections to Scaler Channels
- SCALER_LATCH_IN : in std_logic;
- SCALER_CHANNELS_IN : in std_logic_vector (7 downto 0);
+ --Connections to Scaler Channels
+ CHANNELS_NIM_IN : in std_logic_vector (7 downto 0);
+ CHANNELS_ECL_IN : in std_logic_vector (15 downto 0);
+ LEDR_OUT : out std_logic_vector (3 downto 0);
+ LEDG_OUT : out std_logic_vector (6 downto 0);
+
---------------------------------------------------------------------------
-- END AddonBoard nXyter
---------------------------------------------------------------------------
attribute syn_useioff of FLASH_DOUT : signal is true;
attribute syn_useioff of FPGA5_COMM : signal is true;
attribute syn_useioff of TEST_LINE : signal is false;
- --attribute syn_useioff of SCALER_DEBUG_LINE : signal is false;
- --attribute syn_useioff of INP : signal is false;
- attribute syn_useioff of SCALER_CHANNELS_IN : signal is true;
-
- --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
- --attribute syn_useioff of NX1_ADC_D_IN : signal is true;
- --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
- --attribute syn_useioff of DAC_SDO : signal is true;
- --attribute syn_useioff of DAC_SDI : signal is true;
- --attribute syn_useioff of DAC_SCK : signal is true;
- --attribute syn_useioff of DAC_CS : signal is true;
-
+ attribute syn_useioff of CHANNELS_NIM_IN : signal is false;
+ attribute syn_useioff of CHANNELS_ECL_IN : signal is false;
+ attribute syn_useioff of LEDR_OUT : signal is false;
+ attribute syn_useioff of LEDG_OUT : signal is false;
+
end entity;
signal bussed_tx : CTRLBUS_TX;
-- nXyter-FEB-Board Clocks
+ signal quad_channel_0 : std_logic;
+
signal clk_scaler : std_logic;
signal clk_scaler_lock : std_logic;
signal clk_scaler_reset : std_logic;
-- nXyter 1 Regio Bus
- signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
- signal nx1_regio_data_in : std_logic_vector (31 downto 0);
- signal nx1_regio_data_out : std_logic_vector (31 downto 0);
- signal nx1_regio_read_enable_in : std_logic;
- signal nx1_regio_write_enable_in : std_logic;
- signal nx1_regio_timeout_in : std_logic;
- signal nx1_regio_dataready_out : std_logic;
- signal nx1_regio_write_ack_out : std_logic;
- signal nx1_regio_no_more_data_out : std_logic;
- signal nx1_regio_unknown_addr_out : std_logic;
-
- signal nx1_debug_line_o : std_logic_vector(15 downto 0);
+ signal feb_regio_addr_in : std_logic_vector (15 downto 0);
+ signal feb_regio_data_in : std_logic_vector (31 downto 0);
+ signal feb_regio_data_out : std_logic_vector (31 downto 0);
+ signal feb_regio_read_enable_in : std_logic;
+ signal feb_regio_write_enable_in : std_logic;
+ signal feb_regio_timeout_in : std_logic;
+ signal feb_regio_dataready_out : std_logic;
+ signal feb_regio_write_ack_out : std_logic;
+ signal feb_regio_no_more_data_out : std_logic;
+ signal feb_regio_unknown_addr_out : std_logic;
+
+ signal feb_debug_line_o : std_logic_vector(15 downto 0);
-- Internal Trigger
signal fee1_trigger : std_logic;
timing_trg_received_i <= TRIGGER_LEFT;
----------------------------------------------------------------------------
--- AddOn
----------------------------------------------------------------------------
-
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------
BUS_NO_MORE_DATA_IN(1) => '0',
BUS_UNKNOWN_ADDR_IN(1) => '0',
- --Bus Handler (nXyter1 trb_net16_regio_bus_handler)
- BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in,
- BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in,
- BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in,
- BUS_ADDR_OUT(2*16+11 downto 2*16) => nx1_regio_addr_in(11 downto 0),
+ --Bus Handler (FEB trb_net16_regio_bus_handler)
+ BUS_READ_ENABLE_OUT(2) => feb_regio_read_enable_in,
+ BUS_WRITE_ENABLE_OUT(2) => feb_regio_write_enable_in,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => feb_regio_data_in,
+ BUS_ADDR_OUT(2*16+11 downto 2*16) => feb_regio_addr_in(11 downto 0),
BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open,
- BUS_TIMEOUT_OUT(2) => open, --nx1_regio_timeout_in,
- BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out,
- BUS_DATAREADY_IN(2) => nx1_regio_dataready_out,
- BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out,
- BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out,
+ BUS_TIMEOUT_OUT(2) => open, --feb_regio_timeout_in,
+ BUS_DATA_IN(2*32+31 downto 2*32) => feb_regio_data_out,
+ BUS_DATAREADY_IN(2) => feb_regio_dataready_out,
+ BUS_WRITE_ACK_IN(2) => feb_regio_write_ack_out,
+ BUS_NO_MORE_DATA_IN(2) => feb_regio_no_more_data_out,
+ BUS_UNKNOWN_ADDR_IN(2) => feb_regio_unknown_addr_out,
BUS_READ_ENABLE_OUT(3) => bussed_rx.read,
BUS_WRITE_ENABLE_OUT(3) => bussed_rx.write,
LED_RED <= timing_trg_received_i;
LED_YELLOW <= not med_stat_op(11);
------------------------------------------------------------------------------
--- The xXyter-FEB #1
------------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- AddOn GPIN_ADDON1
+---------------------------------------------------------------------------
+ --LEDG_OUT <= CHANNELS_NIM_IN(6 downto 0);
+ LEDR_OUT <= (others => '1');
scaler_0: scaler
generic map (
TRIGGER_OUT => fee1_trigger,
- LATCH_IN => SCALER_LATCH_IN,
- CHANNELS_IN => SCALER_CHANNELS_IN,
+ LATCH_IN => CHANNELS_ECL_IN(0),
+ CHANNELS_IN(0) => quad_channel_0,
+ CHANNELS_IN(7 downto 1) => CHANNELS_NIM_IN(7 downto 1),
TIMING_TRIGGER_IN => TRIGGER_RIGHT,
LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
FEE_DATA_FINISHED_OUT => fee_data_finished_i(0),
FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(0),
- REGIO_ADDR_IN => nx1_regio_addr_in,
- REGIO_DATA_IN => nx1_regio_data_in,
- REGIO_DATA_OUT => nx1_regio_data_out,
- REGIO_READ_ENABLE_IN => nx1_regio_read_enable_in,
- REGIO_WRITE_ENABLE_IN => nx1_regio_write_enable_in,
- REGIO_TIMEOUT_IN => nx1_regio_timeout_in,
- REGIO_DATAREADY_OUT => nx1_regio_dataready_out,
- REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out,
- REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out,
- REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out,
+ REGIO_ADDR_IN => feb_regio_addr_in,
+ REGIO_DATA_IN => feb_regio_data_in,
+ REGIO_DATA_OUT => feb_regio_data_out,
+ REGIO_READ_ENABLE_IN => feb_regio_read_enable_in,
+ REGIO_WRITE_ENABLE_IN => feb_regio_write_enable_in,
+ REGIO_TIMEOUT_IN => feb_regio_timeout_in,
+ REGIO_DATAREADY_OUT => feb_regio_dataready_out,
+ REGIO_WRITE_ACK_OUT => feb_regio_write_ack_out,
+ REGIO_NO_MORE_DATA_OUT => feb_regio_no_more_data_out,
+ REGIO_UNKNOWN_ADDR_OUT => feb_regio_unknown_addr_out,
DEBUG_LINE_OUT => TEST_LINE
--DEBUG_LINE_OUT => open
);
- nx1_regio_addr_in(15 downto 12) <= (others => '0');
+ feb_regio_addr_in(15 downto 12) <= (others => '0');
-- TEST_LINE(0) <= clk_100_i;
- -- TEST_LINE(1) <= nx1_regio_read_enable_in;
- -- TEST_LINE(2) <= nx1_regio_write_enable_in;
- -- TEST_LINE(3) <= nx1_regio_dataready_out;
- -- TEST_LINE(4) <= nx1_regio_write_ack_out;
- -- TEST_LINE(5) <= nx1_regio_unknown_addr_out;
+ -- TEST_LINE(1) <= feb_regio_read_enable_in;
+ -- TEST_LINE(2) <= feb_regio_write_enable_in;
+ -- TEST_LINE(3) <= feb_regio_dataready_out;
+ -- TEST_LINE(4) <= feb_regio_write_ack_out;
+ -- TEST_LINE(5) <= feb_regio_unknown_addr_out;
-- TEST_LINE(6) <= LED_GREEN;
-- TEST_LINE(7) <= LED_ORANGE;
-- TEST_LINE(8) <= LED_RED;
);
-----------------------------------------------------------------------------
- -- nXyter Main and ADC Clocks
+ -- Scaler Clocks
-----------------------------------------------------------------------------
- -- Scaler Domain Clock 500MHz
+ pll_quadruple_channel_0: entity work.pll_quadruple
+ port map (
+ CLK => CHANNELS_NIM_IN(0),
+ CLKOP => quad_channel_0,
+ LOCK => open
+ );
+
+ -- Scaler Domain Clock 400MHz
pll_scaler_1: entity work.pll_clk400
port map (
CLK => CLK_PCLK_RIGHT,
#################################################
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns;
+PROHIBIT PRIMARY NET "quad_channel_0*";
+PROHIBIT SECONDARY NET "quad_channel_0*";
-MULTICYCLE TO CELL "scaler_0/scaler_channel_*/reset_clk_d1_ff*" 30 ns;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 100 ns;
-MULTICYCLE TO CELL "scaler_0/scaler_channel_*/PULSE_IN_to_pulse/pulse_ff*" 30 ns;
-MULTICYCLE TO CELL "scaler_0/scaler_channel_*/LATCH_IN_to_latch/pulse_ff*" 30 ns;
-MULTICYCLE FROM CELL "scaler_0/scaler_channel_*/internal_pulse*" 100 ns;
+MULTICYCLE TO CELL "scaler_0/reset_d1_ff*[1]*" 100 ns;
-MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ;
-MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ;
+MULTICYCLE TO CELL "scaler_0/scaler_channel_0/pulse_ff*[2]*" 30 ns;
-#MULTICYCLE TO CELL "scaler_0/scaler_channel_1/INHIBIT_IN_to_inhibit/pulse_ff*" 30 ns;
-#MULTICYCLE TO CELL "scaler_0/scaler_channel_1/counter_latched*" 30 ns;
+MULTICYCLE TO CELL "scaler_0/latch_handler_1/reset_ctr_ff*[2]*" 30 ns;
+MULTICYCLE FROM CELL "scaler_0/latch_handler_1/latch_select_r*" 100 ns;
+MULTICYCLE TO CELL "scaler_0/latch_handler_1/latch_ff*[2]*" 30 ns;
+
+MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ;
+MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ;
# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/trigger_busy_ff*" 30 ns;
Zum Kompilieren:
das in workdir aufrufen falls die links weg sind:
-/home/rich/TRB/nXyter/trb3/base/linkdesignfiles.sh
jspc29 / trb3.git / commitdiff