new cts ver.

diff --git a/cts.tex b/cts.tex
index 2e2663c69769b3c93092cacd2e27967b7bde9604..c64ddd8ada6b6c76d2c415b9940cd899917ed426 100644 (file)
--- a/cts.tex
+++ b/cts.tex
@@ -40,7 +40,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
      \item[Bit 21 -- 17] Delay of MDCA (MDC 1/2) trigger = value * 20 ns 
      \item[Bit 31 -- 28] LVL1 trigger width, when value < 7 then width = 105 + Value*5 ns else width = Value*5ns
     \end{description}
-  \item [0xA0C2] Multiplexers output select:
+  \item [0xA0C2] Multiplexers output select - this output is also used for histograms (24th histogram - counting from 0) :
     \begin{description}
      \item[Bit 7 -- 0] Selects the output signal for LVDS OUT(4) (the order like on the fig.\ref{cts_logic}) to see internal FPGA signals after diferent stages of signal processing
       \begin{description}
@@ -65,21 +65,24 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
         \item 129 - anti coincidence signal (0x81)
         \item 255 - 130 not used
       \end{description}
-     \item[Bit 15 -- 8] Selects the output signal for LVDS OUT(5) (the same values as for LVDS OUT(4))
+     \item[Bit 15 -- 8] Selects the output signal for LVDS OUT(5) (the same values as for LVDS OUT(4)) - this output is also used for histograms (25th histogram - counting from 0)
      \item[Bit 31 -- 28] Data version set into the data stream from the CTS (see a CTS data structure chapter)
     \end{description}
   \item [0xA0C4 -- 0xA0C3] Enable CTS trigger inputs (order as on the  Fig.\ref{cts_logic})
   \item [0xA0C5] TS gating disable
-  \item [0xA0C6] Global time offset for 8 START channels used for beam structure
+  \item [0xA0C6] Global time offset for all signals used for beam structure
   \item [0xA0C7] Enable trigger outputs 
-  \item [0xA0C8] Sample period for 8 START channels - $value*100ns$ for individual start beam structure see fig. \ref{ctsbeam}
+  \item [0xA0C8] Sample period for signals being histogrammed - $value*100ns$. See fig. \ref{ctsbeam}
   \item [0xA0D0 -- 0xA0C9] Registers for downscaling incoming signals, only $2^{value}$ is passing. 
   \item [0xA0D8 -- 0xA0D1] Registers for making a delay of the signal - $value * 1,25\,ns$
-  \item [0xA0D9] -- time offset for beam structure A (after BEAM START signal) 
-  \item [0xA0DA] -- time offset for beam structure B (after BEAM START signal)
-  \item [0xA0DB] -- Sample period for beam structure A - $value*100ns$ 
-  \item [0xA0DC] -- Sample period for beam structure B - $value*100NM$ 
-  \item [0xA0DD] -- Length of the beam itself after this time the beam inhibit signal is set till next START BEAM signal - $value*100ns$ 
+  \item [0xA0D9] -- Length of the beam itself after this time the beam inhibit signal is set till next START BEAM signal - $value*100ns$ 
+  \item [0xA0DA] -- use different parts of the START detector for histograms
+    \begin{description}
+    \item [Bit 1 -- 0] when '00' inputs 7 - 0 from the Start detector are used, '01' 11 - 4, '10' 15 - 8
+    \item [Bit 3 -- 2] when '00' inputs 23 - 16 from the Start detector are used, '01' 27 - 20, '10' 31 - 24
+    \end{description}
+  \item [0xA0DD -- 0xA0DB] Delay the signals with large values  - $value * 5\,ns$
+  \item [0xA0E2 -- 0xA0DE] Set width of the signals - $5 + value * 4\,ns$
   \item [0xA0E3] Pulser for triggering the system with different frequencies
     \begin{description}
      \item[Bit 27 -- 0] When 0 the internal triggering is disabled, when different than 0 the internal trigger is enabled and $frequency = 1/Value*10ns $
@@ -89,8 +92,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
      \item[Bit 6 -- 0] LVL1 trigger information(6 -- 0)
      \item[Bit 13 -- 8] LVL1 trigger information(13 -- 8)
     \end{description}
-  \item [0xA0E7 -- 0xA0E5] Delay the signals with large values  - $value * 5\,ns$
-  \item [0xA0EC -- 0xA0E8] Set width of the signals - $5 + value * 4\,ns$
+  
 %     \item[Bit 23 -- 16] Threshold for the rate detection in $1\,us$ time, when number of hits equals the threshold (or more) the per 1sec marker is set
 %     \item[Bit 31 -- 24] Threshold for the rate detection in $100\,ns$ time, when number of hits equals the threshold (or more) the per 1sec marker is set
   \item [0xA0F0] LVL2 EB IP table and downscale factor for removing not needed data
@@ -255,11 +257,10 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
 \subsection{CTS Data structure}
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
-When there is trigger type which is not equal 0x9 (MDC calibration trigger sent each second) then the data from CTS contains 5 data words.
-When there is MDC calibration trigger CTS sends also scalers information.
+When there is trigger type which is not equal 0xE then the data from the CTS contains 5 data words otherwise CTS sends also all r and r/w registers.
 
 \begin{description}
-\item[1 Standard hub word] When hub is used
+\item[1 Standard hub word] 
 \item[2 First header of the data] the same as for the timing detectors (Start,TOF ...)
 \item[3 Second header]
   \begin{description}
@@ -289,11 +290,11 @@ When there is MDC calibration trigger CTS sends also scalers information.
     \item[bit 18] PT 8
     \item[bit 31 -- 19] All 0
   \end{description}
-\item[5 Latches] All 0
-\item[ - 6] The rest of the data is just copy of all RW and R (for the scalers it is a copy of hits per second)  registers (maximally up to the address 0xA0EF)
+\item[5 Latches] All 0 (currently not used)
+\item[6 ...] The rest of the data is just copy of all RW and R registers (see registers description above)
   \begin{description}  
-    \item[6+RW registers(48)-1 -- 6] Register from 0xA0C0 address to 0xA0EC 
-    \item[6+RW registers(48)+R registers(81)-1 -- 6+RW registers(48)] Register from 0xA000 address to 0xA051 
+    \item[48 RW registers] Register starting from 0xA0C0 (see registers description above)
+    \item[81 R registers] Register starting from 0xA000  (see registers description above)
   \end{description}
 \end{description}