Updating TRB3sc pulsers for debug UART, disabled in most designs. Updating Pulser...

diff --git a/adcaddon/config.vhd b/adcaddon/config.vhd
index 700293a91dc2776f3072c4ef1fc66b66a91d9d47..ec7bcd8553f271aa29b78b35d062ac8a28a1167a 100644 (file)
--- a/adcaddon/config.vhd
+++ b/adcaddon/config.vhd
@@ -28,6 +28,7 @@ package config is
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_YES;
+    constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO;
    
     --input monitor and trigger generation logic
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_NO;

diff --git a/adcaddon/trb3sc_adc.prj b/adcaddon/trb3sc_adc.prj
index 62b1e9ef6a1a61b5f6466b9dd2b932e441403420..5d27da07e101eebce7d6a483c99753d2b232038f 100644 (file)
--- a/adcaddon/trb3sc_adc.prj
+++ b/adcaddon/trb3sc_adc.prj
@@ -102,6 +102,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"

diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd
index 4fe7a18e1e459d7d71a8534dae44355f7936c50b..c44a7ea2cdefc5caa8c6e8ae1bbdbdb14258ce5d 100644 (file)
--- a/backplanemaster/config.vhd
+++ b/backplanemaster/config.vhd
@@ -27,6 +27,7 @@ package config is
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_YES;
+    constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO;
     
     --input monitor and trigger generation logic
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_YES;

diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj
index 764e2ab8003d36398d9b132f56f3abb1a322b839..02e544e0051ae9af7dae922c9c8e78022c0dac1a 100644 (file)
--- a/backplanemaster/trb3sc_master.prj
+++ b/backplanemaster/trb3sc_master.prj
@@ -109,6 +109,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"

diff --git a/code/debuguart.vhd b/code/debuguart.vhd
index 9428fc2e4ae5806e65bcee4b2c66f8035be91bfc..579ba46f9d527fb0defa9d00dd1f2727f63393cd 100644 (file)
--- a/code/debuguart.vhd
+++ b/code/debuguart.vhd
@@ -17,7 +17,7 @@ entity debuguart is
     
     DEBUG_ACTIVE  : out std_logic;
   
-    BUS_DEBUG_TX  : in  CTRLBUS_TX;
+    BUS_DEBUG_TX  : in  CTRLBUS_TX := (data => (others => '0'), unknown => '1', others => '0');
     BUS_DEBUG_RX  : out CTRLBUS_RX;
     
     STATUS        : out std_logic_vector(31 downto 0)

diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd
index 4fff2572b63984dde0f4cdeb1f679d79f3945464..88b78f2ec146d8e680dcc7822ea662930679e199 100644 (file)
--- a/code/trb3sc_tools.vhd
+++ b/code/trb3sc_tools.vhd
@@ -51,7 +51,7 @@ entity trb3sc_tools is
     BUS_TX     : out CTRLBUS_TX;
     
     --Control master for default settings
-    BUS_MASTER_IN  : in CTRLBUS_TX;
+    BUS_MASTER_IN  : in CTRLBUS_TX := (data => (others => '0'), unknown => '1', others => '0');
     BUS_MASTER_OUT : out CTRLBUS_RX;
     BUS_MASTER_ACTIVE : out std_logic;
     

diff --git a/hubaddon/config.vhd b/hubaddon/config.vhd
index 13c11fe02e9d28d91d2a15abef40cdd935588ee9..1e9bd04c10a317bc2deca291b1756ca239f40866 100644 (file)
--- a/hubaddon/config.vhd
+++ b/hubaddon/config.vhd
@@ -27,6 +27,7 @@ package config is
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_YES;
+    constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO;
 
     --input monitor and trigger generation logic
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_NO;

diff --git a/hubaddon/trb3sc_hubaddon.prj b/hubaddon/trb3sc_hubaddon.prj
index 3c795c9876ef0b2bfac29122d77ce58cc38d61ce..9e224de2381eac3dc2825db9f8343bb6fa2e1383 100644 (file)
--- a/hubaddon/trb3sc_hubaddon.prj
+++ b/hubaddon/trb3sc_hubaddon.prj
@@ -109,6 +109,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"

diff --git a/padiwa/config.vhd b/padiwa/config.vhd
index 2827b400cd7b25d4a2b2590f9e3a3054c4aee86d..5d60d47a69f6595769584e42aa4a552876282b74 100644 (file)
--- a/padiwa/config.vhd
+++ b/padiwa/config.vhd
@@ -41,6 +41,7 @@ package config is
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_YES;
+    constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO;
 
     --input monitor and trigger generation logic
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_YES;

diff --git a/padiwa/trb3sc_padiwa.prj b/padiwa/trb3sc_padiwa.prj
index 912d140546df476c91b19c2671441c058c473621..297e689dd75599fde00fb2945c43f8b7c6af21b7 100644 (file)
--- a/padiwa/trb3sc_padiwa.prj
+++ b/padiwa/trb3sc_padiwa.prj
@@ -106,6 +106,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"

diff --git a/pulser/config.vhd b/pulser/config.vhd
index 1fb8e03f5e943638e3cfc02eb8da1bba0c0d988a..999ee039c4ade8c0f7288a847575534275ad099f 100644 (file)
--- a/pulser/config.vhd
+++ b/pulser/config.vhd
@@ -21,12 +21,15 @@ package config is
 --Address settings   
     constant INIT_ADDRESS           : std_logic_vector := x"F3CC";
     constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"61";
-   
+    
+--set to 0 for backplane serdes, set to 3 for front SFP serdes
+    constant SERDES_NUM             : integer := 0;   
 
     constant INCLUDE_UART           : integer  := c_YES;
     constant INCLUDE_SPI            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_YES;
-
+    constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO;
+    
     --input monitor and trigger generation logic
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_NO;
     constant INCLUDE_STATISTICS     : integer  := c_NO;

diff --git a/pulser/config_compile_frankfurt.pl b/pulser/config_compile_frankfurt.pl
index be173365137cbd4fa7ee7df78753537fb4d043ab..cb3c4d45def6dfe4ea11717b50534ee39ffde6e7 100644 (file)
--- a/pulser/config_compile_frankfurt.pl
+++ b/pulser/config_compile_frankfurt.pl
@@ -1,9 +1,9 @@
 TOPNAME                      => "trb3sc_pulser",
 lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.5_x64',
+lattice_path                 => '/d/jspc29/lattice/diamond/3.6_x64',
 synplify_path                => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
-synplify_command             => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
+synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
 #synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 
 nodelist_file                => 'nodelist_frankfurt.txt',

diff --git a/pulser/trb3sc_pulser.prj b/pulser/trb3sc_pulser.prj
index a4761dbe1b129012f725cfefbfe7432df21948cb..267734338812c5449298dc7175c6a27c1d08542b 100644 (file)
--- a/pulser/trb3sc_pulser.prj
+++ b/pulser/trb3sc_pulser.prj
@@ -107,11 +107,17 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/pulser/trb3sc_pulser.vhd b/pulser/trb3sc_pulser.vhd
index 06a6840341ea964540f89259c2332373fa207ed7..723a04ef0ad92d365e88ed254351bad146987838 100644 (file)
--- a/pulser/trb3sc_pulser.vhd
+++ b/pulser/trb3sc_pulser.vhd
@@ -23,7 +23,7 @@ entity trb3sc_pulser is
     TRIG_LEFT            : in    std_logic; --Trigger Input
     
     --Backplane for slaves on trbv3scbp1
---     BACK_GPIO            : inout std_logic_vector(3 downto 0);
+    BACK_GPIO            : inout std_logic_vector(3 downto 0);
     
     --AddOn Connector
     OUTP     : out std_logic_vector(16 downto 1);
@@ -153,6 +153,8 @@ architecture trb3sc_arch of trb3sc_pulser is
   signal timer          : TIMERS;
   signal lcd_data       : std_logic_vector(511 downto 0);
   
+  signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;  
+  
   attribute syn_keep of GSR_N     : signal is true;
   attribute syn_preserve of GSR_N : signal is true;  
   attribute syn_keep of bussci_rx     : signal is true;
@@ -199,11 +201,12 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
 
 THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
   generic map(
-    SERDES_NUM  => 3,
-    IS_SYNC_SLAVE   => c_YES
+    SERDES_NUM     => SERDES_NUM,
+    IS_SYNC_SLAVE  => c_YES
     )
   port map(
-    CLK                => clk_full_osc,
+    CLK_REF_FULL       => med2int(0).clk_full,
+    CLK_INTERNAL_FULL  => clk_full_osc,
     SYSCLK             => clk_sys,
     RESET              => reset_i,
     CLEAR              => clear_i,
@@ -217,25 +220,32 @@ THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
     TX_DLM             => open,
     TX_DLM_WORD        => open,
     
-    --SFP Connection
-    SD_RXD_P_IN        => SERDES_RX(0),
-    SD_RXD_N_IN        => SERDES_RX(1),
-    SD_TXD_P_OUT       => SERDES_TX(0),
-    SD_TXD_N_OUT       => SERDES_TX(1),
-    SD_REFCLK_P_IN     => '0',
-    SD_REFCLK_N_IN     => '0',
-    SD_PRSNT_N_IN      => SFP_MOD0(1),
-    SD_LOS_IN          => SFP_LOS(1),
-    SD_TXDIS_OUT       => SFP_TX_DIS(1),
-    --Control Interface
-    BUS_RX             => bussci_rx,
-    BUS_TX             => bussci_tx,
-    -- Status and control port
-    STAT_DEBUG         => med_stat_debug(63 downto 0),
-    CTRL_DEBUG         => open
-  );
-
-SFP_TX_DIS(0) <= '1';
+      --SFP Connection
+      SD_REFCLK_P_IN => '0',
+      SD_REFCLK_N_IN => '0',
+      SD_PRSNT_N_IN  => sfp_prsnt_i,
+      SD_LOS_IN      => sfp_los_i,
+      SD_TXDIS_OUT   => sfp_txdis_i,
+      --Control Interface
+      BUS_RX         => bussci_rx,
+      BUS_TX         => bussci_tx,
+      -- Status and control port
+      STAT_DEBUG     => med_stat_debug(63 downto 0),
+      CTRL_DEBUG     => open
+      );
+
+  SFP_TX_DIS(0) <= '1';
+  gen_sfp_con : if SERDES_NUM = 3 generate
+    sfp_los_i   <= SFP_LOS(1);
+    sfp_prsnt_i <= SFP_MOD0(1); 
+    SFP_TX_DIS(1) <= sfp_txdis_i;
+  end generate;  
+  gen_bpl_con : if SERDES_NUM = 0 generate
+    sfp_los_i   <= BACK_GPIO(1);
+    sfp_prsnt_i <= BACK_GPIO(1); 
+    BACK_GPIO(0) <= sfp_txdis_i;
+  end generate;  
+  
 
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 -- Endpoint