working version

diff --git a/mupix/Mupix8/sources/DataMuxWithConversion.vhd b/mupix/Mupix8/sources/DataMuxWithConversion.vhd
index 2f5e702a9fb6a1ddef149c9462ce30bac0f1c02d..2e44e824e6ca1e4e6671774769ff519e3b6f689e 100644 (file)
--- a/mupix/Mupix8/sources/DataMuxWithConversion.vhd
+++ b/mupix/Mupix8/sources/DataMuxWithConversion.vhd
@@ -194,7 +194,8 @@ begin
         buff_wren    <= '0';
         mux_fsm      <= idle;
       else
-        empty_delay <= empty_delay(0) & fifo_empty(fifo_sel_reg);
+        empty_delay      <= empty_delay(0) & fifo_empty(fifo_sel_reg);
+        increase_counter <= (others => '0');
         case mux_fsm is
           when idle =>
             fifo_rden         <= (others => '0');
@@ -262,6 +263,7 @@ begin
                 conversioncounter       <= 0;
                 buff_wren               <= '0';
                 dataout                 <= (others => '0');
+                increase_counter        <= (others => '0');
                 mux_fsm                 <= wait_fifo;
             end case;
         end case;

diff --git a/mupix/Mupix8/sources/Generator3.vhd b/mupix/Mupix8/sources/Generator3.vhd
index 898be09f7648df33fc5cc35e4f593c6f2e61b1e7..f7fc745f6dec8ce52aa205c04c4e6668f27925c2 100644 (file)
--- a/mupix/Mupix8/sources/Generator3.vhd
+++ b/mupix/Mupix8/sources/Generator3.vhd
@@ -41,10 +41,10 @@ signal pause_ctr   : unsigned(31 downto 0) := (others => '0');
 signal down_ctr    : unsigned(31 downto 0) := (others => '0');
 --signal data_int    : unsigned(15 downto 0) := (others => '0');
 constant chan_sig : chan_type := (
-    0      => x"CA00",
-    1      => x"CA01",
-    2      => x"CA02",
-    3      => x"CA03"
+    0      => x"C01C",
+    1      => x"C02C",
+    2      => x"C03C",
+    3      => x"C04C"
 );
 
 begin
@@ -121,9 +121,7 @@ begin
                 end case;
             end if;
             writeEn <= writeEn_int;
-            data_out(iWIDTH - 1 downto 32) <= (others => '0');
-            data_out(31 downto 16) <= std_logic_vector(num_ctr(15 downto 0));
-            data_out(15 downto 0) <= chan_sig(to_integer(unsigned(chan_sel)));
+            data_out <= chan_sig(to_integer(unsigned(chan_sel))) & std_logic_vector(num_ctr(15 downto 0)) & x"BE";
         end if;
     end process generator;
     

diff --git a/mupix/Mupix8/sources/MuPixDataLink_new.vhd b/mupix/Mupix8/sources/MuPixDataLink_new.vhd
index f476c8af9b36ac3c25314bc75395a335269f4fcf..c672636e4ffd1cdc344c810d92be51120078f0a7 100644 (file)
--- a/mupix/Mupix8/sources/MuPixDataLink_new.vhd
+++ b/mupix/Mupix8/sources/MuPixDataLink_new.vhd
@@ -225,7 +225,6 @@ architecture rtl of MupixDataLinkWithUnpacker is
   -- slow control resets
   signal reset_counters_i : std_logic := '0';
   signal reset_quad_i     : std_logic := '0';
-  signal reset_serdes_i   : std_logic := '1';
   signal reset_fifos_i    : std_logic := '0';
 
 begin
@@ -302,13 +301,13 @@ begin
       rx_pwrup_ch3_c      => ch_powerup_i(3),
       rx_los_low_ch3_s    => rx_sig_lost_i(3),
       rx_cdr_lol_ch3_s    => rx_cdr_i(3),
-      rx_div2_mode_ch3_c  => ch_divmode_i(2),
+      rx_div2_mode_ch3_c  => ch_divmode_i(3),
       fpga_txrefclk       => dataclk,
       tx_sync_qd_c        => '0',  -- serializer reset (not needed for receiving)
       refclk2fpga         => open,
-      rst_n               => reset_serdes_i,  -- reset all channels including PCS (active
+      rst_n               => '1',  -- reset all channels including PCS (active
       -- low, not documented in maunal -> consult
-      -- vhdl code)
+      -- vhdl code of trbnet)
       serdes_rst_qd_c     => reset_quad_i);  -- reset all serdes channels but not PCS (active high)
 
   -- synchronize rx data signals into receive clock domain (maybe not
@@ -441,7 +440,6 @@ begin
         slv_no_more_data_out <= '0';
         slv_unknown_addr_out <= '0';
         reset_counters_i     <= '0';
-        reset_serdes_i       <= '1';    --active low
         reset_quad_i         <= '0';
         reset_fifos_i        <= '0';
         if slv_write_in = '1' then
@@ -453,12 +451,9 @@ begin
               slv_ack_out  <= '1';
               reset_quad_i <= slv_data_in(0);
             when x"0162" =>
-              slv_ack_out    <= '1';
-              reset_serdes_i <= slv_data_in(0);  -- active low 
-            when x"0163" =>
               slv_ack_out   <= '1';
               reset_fifos_i <= slv_data_in(0);
-            when x"0164" =>
+            when x"0163" =>
               slv_ack_out           <= '1';
               serdes_channel_select <= to_integer(unsigned(slv_data_in(1 downto 0)));
             when others =>
@@ -466,7 +461,7 @@ begin
           end case;
         elsif slv_read_in = '1' then
           case slv_addr_in is
-            when x"0164" =>
+            when x"0163" =>
               slv_ack_out              <= '1';
               slv_data_out(1 downto 0) <= std_logic_vector(to_unsigned(serdes_channel_select, 2));
             when x"0165" =>

diff --git a/mupix/Mupix8/tb/MupixTRBReadoutTest.vhd b/mupix/Mupix8/tb/MupixTRBReadoutTest.vhd
index 67610f9960580a07e4c77ba088fdfcae685347f1..702833404f1fb224d2dcbf533067f9150a07408a 100644 (file)
--- a/mupix/Mupix8/tb/MupixTRBReadoutTest.vhd
+++ b/mupix/Mupix8/tb/MupixTRBReadoutTest.vhd
@@ -9,170 +9,176 @@ end entity MupixTRBReadoutTest;
 
 architecture sim of MupixTRBReadoutTest is
 
-       component MupixTRBReadout
-               generic(
-                       g_mupix_links           : natural := 4;
-                       g_cyc_mem_address_width : integer := 13;
-                       g_datawidth             : integer := 32
-               );
-               port(
-                       clk                  : in  std_logic;
-                       rst                  : in  std_logic;
-                       fifo_empty           : in  std_logic_vector(g_mupix_links - 1 downto 0);
-                       fifo_full            : in  std_logic_vector(g_mupix_links - 1 downto 0);
-                       fifo_datain          : in  std_logic_vector(g_mupix_links*g_datawidth - 1 downto 0);
-                       fifo_rden            : out std_logic_vector(g_mupix_links - 1 downto 0);
-                       trb_trigger          : in  std_logic;
-                       dataout              : out std_logic_vector(g_datawidth - 1 downto 0);
-                       data_valid           : out std_logic;
-                       busy                 : out std_logic;
-                       SLV_READ_IN          : in  std_logic;
-                       SLV_WRITE_IN         : in  std_logic;
-                       SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
-                       SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
-                       SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
-                       SLV_ACK_OUT          : out std_logic;
-                       SLV_NO_MORE_DATA_OUT : out std_logic;
-                       SLV_UNKNOWN_ADDR_OUT : out std_logic
-               );
-       end component MupixTRBReadout;
-       
-       component STD_FIFO
-               generic(
-                       DATA_WIDTH : positive := 8;
-                       FIFO_DEPTH : positive := 256
-               );
-               port(
-                       CLK     : in  std_logic;
-                       RST     : in  std_logic;
-                       WriteEn : in  std_logic;
-                       DataIn  : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
-                       ReadEn  : in  std_logic;
-                       DataOut : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-                       Empty   : out std_logic;
-                       Full    : out std_logic
-               );
-       end component STD_FIFO;
-       
-       constant c_clk_period            : time    := 10 ns;
-       constant c_mupix_links           : integer := 4;
-       constant c_cyc_mem_address_width : integer := 6;
-       constant c_datawidth             : integer := 32;
-       
-       signal clk                       : std_logic;
-       signal rst                       : std_logic := '0';
-       signal fifo_empty                : std_logic_vector(c_mupix_links - 1 downto 0) := (others => '1');
-       signal fifo_full                 : std_logic_vector(c_mupix_links - 1 downto 0) := (others => '0');
-       signal fifo_data_to_mux          : std_logic_vector(c_mupix_links*c_datawidth - 1 downto 0) := (others => '0');
-       signal fifo_rden                 : std_logic_vector(c_mupix_links - 1 downto 0) := (others => '0');
-       signal trb_trigger               : std_logic := '0';
-       signal dataout                   : std_logic_vector(c_datawidth - 1 downto 0);
-       signal data_valid                : std_logic;
-       signal busy                      : std_logic;
-       signal SLV_READ_IN               : std_logic := '0';
-       signal SLV_WRITE_IN              : std_logic := '0';
-       signal SLV_DATA_OUT              : std_logic_vector(31 downto 0);
-       signal SLV_DATA_IN               : std_logic_vector(31 downto 0) := (others => '0');
-       signal SLV_ADDR_IN               : std_logic_vector(15 downto 0) := (others => '0');
-       signal SLV_ACK_OUT               : std_logic;
-       signal SLV_NO_MORE_DATA_OUT      : std_logic;
-       signal SLV_UNKNOWN_ADDR_OUT      : std_logic;
-       
-       signal fifo_write_en : std_logic_vector(c_mupix_links - 1 downto 0) := (others => '0');
-       signal fifo_datain   : std_logic_vector(c_mupix_links*c_datawidth - 1 downto 0) := (others => '0');
-       
+  component MupixTRBReadout
+    generic(
+      g_mupix_links           : natural := 4;
+      g_cyc_mem_address_width : integer := 13;
+      g_datawidthfifo         : integer := 40;
+      g_datawidthtrb          : integer := 32
+      );
+    port(
+      clk                  : in  std_logic;
+      rst                  : in  std_logic;
+      fifo_empty           : in  std_logic_vector(g_mupix_links - 1 downto 0);
+      fifo_full            : in  std_logic_vector(g_mupix_links - 1 downto 0);
+      fifo_datain          : in  std_logic_vector(g_mupix_links*g_datawidthfifo - 1 downto 0);
+      fifo_rden            : out std_logic_vector(g_mupix_links - 1 downto 0);
+      trb_trigger          : in  std_logic;
+      dataout              : out std_logic_vector(g_datawidthtrb - 1 downto 0);
+      data_valid           : out std_logic;
+      busy                 : out std_logic;
+      SLV_READ_IN          : in  std_logic;
+      SLV_WRITE_IN         : in  std_logic;
+      SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+      SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+      SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+      SLV_ACK_OUT          : out std_logic;
+      SLV_NO_MORE_DATA_OUT : out std_logic;
+      SLV_UNKNOWN_ADDR_OUT : out std_logic
+      );
+  end component MupixTRBReadout;
+
+  component STD_FIFO
+    generic(
+      DATA_WIDTH : positive := 8;
+      FIFO_DEPTH : positive := 256
+      );
+    port(
+      CLK     : in  std_logic;
+      RST     : in  std_logic;
+      WriteEn : in  std_logic;
+      DataIn  : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+      ReadEn  : in  std_logic;
+      DataOut : out std_logic_vector(DATA_WIDTH - 1 downto 0);
+      Empty   : out std_logic;
+      Full    : out std_logic
+      );
+  end component STD_FIFO;
+
+  constant c_clk_period            : time    := 10 ns;
+  constant c_mupix_links           : integer := 4;
+  constant c_cyc_mem_address_width : integer := 6;
+  constant c_datawidthfifo         : integer := 40;
+  constant c_datawidthtrb          : integer := 32;
+
+  type channel_type is array (0 to 3) of std_logic_vector(15 downto 0);
+  constant c_channel_id : channel_type := (x"C01C", x"C02C", x"C03C", x"C04C");
+
+  signal clk                  : std_logic;
+  signal rst                  : std_logic                                                := '0';
+  signal fifo_empty           : std_logic_vector(c_mupix_links - 1 downto 0)             := (others => '1');
+  signal fifo_full            : std_logic_vector(c_mupix_links - 1 downto 0)             := (others => '0');
+  signal fifo_data_to_mux     : std_logic_vector(c_mupix_links*c_datawidthfifo - 1 downto 0) := (others => '0');
+  signal fifo_rden            : std_logic_vector(c_mupix_links - 1 downto 0)             := (others => '0');
+  signal trb_trigger          : std_logic                                                := '0';
+  signal dataout              : std_logic_vector(c_datawidthtrb - 1 downto 0);
+  signal data_valid           : std_logic;
+  signal busy                 : std_logic;
+  signal SLV_READ_IN          : std_logic                                                := '0';
+  signal SLV_WRITE_IN         : std_logic                                                := '0';
+  signal SLV_DATA_OUT         : std_logic_vector(31 downto 0);
+  signal SLV_DATA_IN          : std_logic_vector(31 downto 0)                            := (others => '0');
+  signal SLV_ADDR_IN          : std_logic_vector(15 downto 0)                            := (others => '0');
+  signal SLV_ACK_OUT          : std_logic;
+  signal SLV_NO_MORE_DATA_OUT : std_logic;
+  signal SLV_UNKNOWN_ADDR_OUT : std_logic;
+
+  signal fifo_write_en : std_logic_vector(c_mupix_links - 1 downto 0)             := (others => '0');
+  signal fifo_datain   : std_logic_vector(c_mupix_links*c_datawidthfifo - 1 downto 0) := (others => '0');
+
 begin
 
 
-       dut : entity work.MupixTRBReadout
-               generic map(
-                       g_mupix_links           => c_mupix_links,
-                       g_cyc_mem_address_width => c_cyc_mem_address_width,
-                       g_datawidth             => c_datawidth
-               )
-               port map(
-                       clk                  => clk,
-                       rst                  => rst,
-                       fifo_empty           => fifo_empty,
-                       fifo_full            => fifo_full,
-                       fifo_datain          => fifo_data_to_mux,
-                       fifo_rden            => fifo_rden,
-                       trb_trigger          => trb_trigger,
-                       dataout              => dataout,
-                       data_valid           => data_valid,
-                       busy                 => busy,
-                       SLV_READ_IN          => SLV_READ_IN,
-                       SLV_WRITE_IN         => SLV_WRITE_IN,
-                       SLV_DATA_OUT         => SLV_DATA_OUT,
-                       SLV_DATA_IN          => SLV_DATA_IN,
-                       SLV_ADDR_IN          => SLV_ADDR_IN,
-                       SLV_ACK_OUT          => SLV_ACK_OUT,
-                       SLV_NO_MORE_DATA_OUT => SLV_NO_MORE_DATA_OUT,
-                       SLV_UNKNOWN_ADDR_OUT => SLV_UNKNOWN_ADDR_OUT
-               );
-       
-       gen_input_fifo : for i in 0 to 3 generate
-               input_fifo : entity work.STD_FIFO
-                       generic map(
-                               DATA_WIDTH => c_datawidth,
-                               FIFO_DEPTH => 16
-                       )
-                       port map(
-                               CLK     => CLK,
-                               RST     => RST,
-                               WriteEn => fifo_write_en(i),
-                               DataIn  => fifo_datain((i + 1)*c_datawidth - 1 downto i*c_datawidth),
-                               ReadEn  => fifo_rden(i),
-                               DataOut => fifo_data_to_mux((i + 1)*c_datawidth - 1 downto i*c_datawidth),
-                               Empty   => fifo_empty(i),
-                               Full    => fifo_full(i)
-                       );
-       end generate gen_input_fifo;
-       
-       
-       clock_gen : process is
-       begin
-               clk <= '1';
-               wait for c_clk_period/2;
-               clk <= '0';
-               wait for c_clk_period/2;
-       end process clock_gen;
-       
-       stimulus : process is
-       begin
-               wait for 100 ns;
-               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000000A", x"0101");
-               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000000B", x"0102");
-               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"ABBA0001", x"0103");
-               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000000F", x"0105");
-               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0106");
-               wait for 5*c_clk_period;
-               for i in 1 to 10 loop
-                       fifo_write_en <= (others => '1');
-                       fifo_datain(4*32 - 1 downto 3*32) <= std_logic_vector(to_unsigned(i, c_datawidth));
-                       fifo_datain(3*32 - 1 downto 2*32) <= std_logic_vector(to_unsigned(i + 10, c_datawidth));
-                       fifo_datain(2*32 - 1 downto 1*32) <= std_logic_vector(to_unsigned(i + 20, c_datawidth));
-                       fifo_datain(1*32 - 1 downto 0*32) <= std_logic_vector(to_unsigned(i + 30, c_datawidth));
-                       wait for c_clk_period;
-               end loop;
-               fifo_write_en                     <= (others => '0');
-               fifo_datain(4*32 - 1 downto 3*32) <= (others => '0');
-               wait for 500 ns;
-               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0100");
-               TRBRegisterRead(SLV_READ_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0104");
-               if SLV_ACK_OUT = '0' then
-                       wait until slv_ack_out = '1';
-                       wait for c_clk_period;
-               end if;
-               TRBRegisterRead(SLV_READ_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0104");
-               if SLV_ACK_OUT = '0' then
-                       wait until slv_ack_out = '1';
-                       wait for c_clk_period;
-               end if;
-               TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000001", x"0100");
-               TRBRegisterRead(SLV_READ_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0104");
-               wait;
-       end process stimulus;
-       
-       
-end architecture;
\ No newline at end of file
+  dut : entity work.MupixTRBReadout
+    generic map(
+      g_mupix_links           => c_mupix_links,
+      g_cyc_mem_address_width => c_cyc_mem_address_width,
+      g_datawidthfifo         => c_datawidthfifo,
+      g_datawidthtrb          => c_datawidthtrb
+      )
+    port map(
+      clk                  => clk,
+      rst                  => rst,
+      fifo_empty           => fifo_empty,
+      fifo_full            => fifo_full,
+      fifo_datain          => fifo_data_to_mux,
+      fifo_rden            => fifo_rden,
+      trb_trigger          => trb_trigger,
+      dataout              => dataout,
+      data_valid           => data_valid,
+      busy                 => busy,
+      SLV_READ_IN          => SLV_READ_IN,
+      SLV_WRITE_IN         => SLV_WRITE_IN,
+      SLV_DATA_OUT         => SLV_DATA_OUT,
+      SLV_DATA_IN          => SLV_DATA_IN,
+      SLV_ADDR_IN          => SLV_ADDR_IN,
+      SLV_ACK_OUT          => SLV_ACK_OUT,
+      SLV_NO_MORE_DATA_OUT => SLV_NO_MORE_DATA_OUT,
+      SLV_UNKNOWN_ADDR_OUT => SLV_UNKNOWN_ADDR_OUT
+      );
+
+  gen_input_fifo : for i in 0 to 3 generate
+    input_fifo : entity work.STD_FIFO
+      generic map(
+        DATA_WIDTH => c_datawidthfifo,
+        FIFO_DEPTH => 16
+        )
+      port map(
+        CLK     => CLK,
+        RST     => RST,
+        WriteEn => fifo_write_en(i),
+        DataIn  => fifo_datain((i + 1)*c_datawidthfifo - 1 downto i*c_datawidthfifo),
+        ReadEn  => fifo_rden(i),
+        DataOut => fifo_data_to_mux((i + 1)*c_datawidthfifo - 1 downto i*c_datawidthfifo),
+        Empty   => fifo_empty(i),
+        Full    => fifo_full(i)
+        );
+  end generate gen_input_fifo;
+
+
+  clock_gen : process is
+  begin
+    clk <= '1';
+    wait for c_clk_period/2;
+    clk <= '0';
+    wait for c_clk_period/2;
+  end process clock_gen;
+
+  stimulus : process is
+  begin
+    wait for 100 ns;
+    TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000000A", x"0101");
+    TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000000B", x"0102");
+    TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"ABBA0001", x"0103");
+    TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"0000000F", x"0105");
+    TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0106");
+    wait for 5*c_clk_period;
+    for i in 1 to 10 loop
+      fifo_write_en                                       <= (others => '1');
+      fifo_datain(4*c_datawidthfifo - 1 downto 3*c_datawidthfifo) <= c_channel_id(0) & std_logic_vector(to_unsigned(i, 8)) & x"BEEB";
+      fifo_datain(3*c_datawidthfifo - 1 downto 2*c_datawidthfifo) <= c_channel_id(1) & std_logic_vector(to_unsigned(i, 8)) & x"BEEB";
+      fifo_datain(2*c_datawidthfifo - 1 downto 1*c_datawidthfifo) <= c_channel_id(2) & std_logic_vector(to_unsigned(i, 8)) & x"BEEB";
+      fifo_datain(1*c_datawidthfifo - 1 downto 0*c_datawidthfifo) <= c_channel_id(3) & std_logic_vector(to_unsigned(i, 8)) & x"BEEB";
+      wait for c_clk_period;
+    end loop;
+    fifo_write_en                                       <= (others => '0');
+    fifo_datain(4*c_datawidthfifo - 1 downto 3*c_datawidthfifo) <= (others => '0');
+    wait for 500 ns;
+    TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0100");
+    TRBRegisterRead(SLV_READ_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0104");
+    if SLV_ACK_OUT = '0' then
+      wait until slv_ack_out = '1';
+      wait for c_clk_period;
+    end if;
+    TRBRegisterRead(SLV_READ_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0104");
+    if SLV_ACK_OUT = '0' then
+      wait until slv_ack_out = '1';
+      wait for c_clk_period;
+    end if;
+    TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000001", x"0100");
+    TRBRegisterRead(SLV_READ_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0104");
+    wait;
+  end process stimulus;
+
+
+end architecture;