type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);
signal ram : ram_t;
-
-
+
+
signal spi_reg20_i : std_logic_vector(15 downto 0);
signal spi_reg40_i : std_logic_vector(15 downto 0);
signal spi_data_i : std_logic_vector(15 downto 0);
signal flash_busy : std_logic;
signal flash_err : std_logic;
-
+
signal leds : std_logic_vector(4 downto 0) := (others => '0');
-
+
signal flash_go_tmp : std_logic_vector(5 downto 0);
signal flash_reset_n : std_logic;
-
+
signal fsm_job : std_logic_vector(1 downto 0);
signal ram_fsm_data_i : std_logic_vector(7 downto 0);
signal ram_fsm_addr_i : std_logic_vector(3 downto 0);
signal ram_fsm_write_i: std_logic;
signal enable_cfg_flash : std_logic;
-
+
signal adc_csb_reg : std_logic_vector(12 downto 1) := x"000";
-
+
begin
spi_cs <= '1';
SPI_CONN_L_CS <= '1';
SPI_CONN_H_CS <= '0';
- SPI_TRB_OUT(0) <= SPI_CONN_H_IN;
+ SPI_TRB_OUT(0) <= SPI_CONN_H_IN;
when others =>
spi_cs <= '1';
SPI_CONN_L_CS <= '1';
SPI_CONN_H_CLK <= SPI_TRB_CLK(0);
SPI_CONN_L_OUT <= SPI_TRB_IN(0);
SPI_CONN_H_OUT <= SPI_TRB_IN(0);
-
-
+
+
spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o;
---------------------------------------------------------------------------
mem_rd_data => flashram_data_o
);
-
+
---------------------------------------------------------------------------
-- I/O Register 0x20
-- Rest of the I/O
---------------------------------------------------------------------------
+ LED_WHITE <= not leds(0);
+ LED_RED <= not leds(1);
+ LED_GREEN <= not leds(2);
+ LED_YELLOW <= not leds(3);
+ LED_ORANGE <= not leds(4);
+
+
+
+
+ GP_LINE <= (others => '0');
end architecture;