SPI description for Amps2, IF

diff --git a/fw_spiconfig.tex b/fw_spiconfig.tex
index 3317ee5570348a9faad7ea949c31a3ec14df3984..5dd22417e22a7285014326aa161d8a1d44206406 100644 (file)
--- a/fw_spiconfig.tex
+++ b/fw_spiconfig.tex
@@ -11,11 +11,26 @@ Note that up to 16 commands can be sent to a board with one trbnet access: Load
 15 -- 0\newline (\& following$\dagger$)& Data & 16 Bit data payload for write commands\\
 
  \end{tabularx} 
-\caption{SPI first data word structure. Following 32 bit words contain payload only}
+\caption{SPI first data word structure (PADIWA v1/2/3 and Amps). Following 32 bit words contain payload only}
 \label{tab:spidata}
 \end{table} 
 
 
+\begin{table}
+ \begin{tabularx}{\textwidth}{c|c|X}
+\textbf{Bits} & \textbf{Name} & \textbf{Content} \\
+\hline
+31 -- 24 & 8-Bit-Register & See table \ref{tab:spiselect}\\
+23 -- 20 & Command & Command, 0: read, 8: write, other: no operation \\
+%19 -- 16 & Subregister & Additional 4 bits for register select (0 -- 15)\\
+15 -- 0  & Data & 16 Bit data payload for write commands\\
+
+ \end{tabularx}
+\caption{SPI data word structure for PADIWA-Amps2.}
+\label{tab:spidata2}
+\end{table}
+
+
 \begin{table}
  \begin{tabularx}{\textwidth}{c|c|c|X}
 \textbf{Register} & \textbf{Subregister} & \textbf{Name} & \textbf{Description} \\
@@ -41,6 +56,41 @@ Unix timestamp of time of compilation. Register 2: Padiwa version number.\\
 0x51 & 0--1 & Flash & Load RAM content to PWM settings. Channel Bit 0 selects upper or lower half of PWM channels. No data payload\\
 0x5C & 0 & Flash & Enable access to configuration Flash when a '1' is written to register 0. Be careful!\\
  \end{tabularx} 
-\caption{SPI component selection}
+\caption{SPI registers for PADIWA v1/2/3 and Amps}
 \label{tab:spiselect}
 \end{table}
+
+
+
+\begin{table}
+ \begin{tabularx}{\textwidth}{c|c|X}
+\textbf{Register} & \textbf{Name} & \textbf{Description} \\
+\hline
+0x00 & PWM & Write/read settings for PWM channels 0 - 15.\\
+%%0x10 & UId/Temp & read unique id. 64 Bit Id is divided in 4 16 Bit words. (r/o)\\
+%%0x10 & 4 & UId/Temp & Board Temperature. Units are 1/16 degrees centigrade (r/o)\\
+0x20 & I/O & Input Enable, one bit per input. 0: enable (default), 1: disable.\\
+0x21 & I/O & Input Status, one bit per input, represents the current status of the pin.\\
+0x22 & I/O & LED. Write: Override LED status. Bit 0-3: LED in alphabetical order. Bit 4: disable override. Read: LED status. LEDs are off by default due to influence on PMTs.\\
+0x23 & I/O & Monitor Select. 4 Bit to select one input to be routed to test output (SPARE\_LINE 5\&6)\\
+0x24 & I/O & Input Invert, one bit for each input signal\\
+0x25 & I/O & Input Stretch, one bit for each input signal. The input signal gets stretched to at least two clock cycles (about 16 ns) length. The timing information of the falling edge is lost.\\
+0x26 & I/O & Temperature Compensation, a 16 Bit value to adjust thresholds 
+when temperature is changing. See below. \\
+0x27 & I/O & Discharge disable. \\
+0x28 & I/O & Discharge override. \\
+0x29 & I/O & Discharge high z. \\
+0x2a & I/O & Delay invert. \\
+0x2b & I/O & Delay select. \\
+0x30--32 & Design & Design Information. Register 0/1: lower/upper part of 
+Unix timestamp of time of compilation. Register 2: Padiwa version number.\\
+%0x22 & any & Cnt & Lower 16 Bits of input signal counters for all 16 channels.\\
+%0x23 & any & Cnt & Upper 8 Bit of input signal counters.\\
+0x4X & Memory & Read/Write to/from RAM. 16 registers with 8 Bit each.\\
+0x5X & Flash & Generic flash controller, see trb3 manual for details.\\
+ \end{tabularx} 
+\caption{SPI registers for PADIWA-Amps2}
+\label{tab:spiselect2}
+\end{table}
+
+