architecture arch of MimosisInput is
constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00";
- constant WORD_LIMIT : integer := 8500;
+ constant WORD_LIMIT : integer := 4000;
signal input_active_i : std_logic;
signal data_i : std_logic_vector(15 downto 0);
signal inp_i : std_logic_vector(7 downto 0);
WrEn => buffer_write,
RdEn => buffer_read,
Reset => RESET,
- AmFullThresh => "1000000000000",
+ AmFullThresh => "0010000000000",
Q(31 downto 0) => buffer_dout,
WCNT => buffer_fill,
Empty => buffer_empty,
\r
PIN(4) <= MIMOSIS_SDA;\r
PIN(3) <= MIMOSIS_SCL;\r
- MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
- MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+ MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z';\r
+ MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z';\r
\r
H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC\r
PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START\r
-- -- 14: Debug - single fine time and the ROM addresses for the two transitions
-- -- 15: Debug - complete carry chain dump
- constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 10; -- size of the event buffer, 2**N
- constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
+ constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 13; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 4095; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
constant USE_GBE : integer := c_YES;
--Runs with 120 MHz instead of 100 MHz
constant USE_RXCLOCK : integer := c_NO;
--Address settings
- constant INIT_ADDRESS : std_logic_vector := x"F586";
- constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"86";
+ constant INIT_ADDRESS : std_logic_vector := x"F575";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"82";
constant INCLUDE_UART : integer := c_NO;
constant INCLUDE_SPI : integer := c_YES;
constant INCLUDE_ADC : integer := c_YES;
- constant INCLUDE_I2C : integer := c_NO;
+ constant INCLUDE_I2C : integer := c_YES;
constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
--input monitor and trigger generation logic
constant PERIPH_TRIGGER_COUNT : integer := 0;
constant ADDON_LINE_COUNT : integer := 1; --36 with Padiwa, 22 with RJ-adapter
constant CTS_OUTPUT_MULTIPLEXERS : integer := 0;
+ constant CTS_NOREADOUT : integer := 1; --no data in readout from CTS
--TODO:
-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO;
--Which external trigger module (ETM) to use?
H6 : inout std_logic_vector(4 downto 0);\r
H7 : inout std_logic_vector(4 downto 0);\r
\r
- PIN : out std_logic_vector(8 downto 1);\r
+ PIN : inout std_logic_vector(8 downto 1);\r
\r
MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic;\r
\r
UP_DOWN_MODE => 0,\r
UP_DOWN_LIMIT => 100,\r
FIXED_DELAY => 100,\r
+ SLOWCTRL_BUFFER_SIZE => 1,\r
\r
NUMBER_OF_GBE_LINKS => 1,\r
LINKS_ACTIVE => "0001",\r
RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,\r
RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,\r
RDO_HEADER_BUFFER_DEPTH => 9,\r
- RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16\r
+ RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16,\r
+ RDO_SKIP_FIRST_BUFFER => CTS_NOREADOUT\r
)\r
port map (\r
CLK => clk_sys,\r
SPI_CLK_OUT => spi_clk,\r
--Header\r
--HEADER_IO => open,\r
- -- HEADER_IO(7) => HDR_IO(6),\r
- -- HEADER_IO(8) => HDR_IO(7),\r
+ HEADER_IO(7) => HDR_IO(6),\r
+ HEADER_IO(8) => HDR_IO(7),\r
ADDITIONAL_REG => add_reg,\r
--ADC\r
ADC_CS => ADC_NCS,\r
-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
\r
- PIN(4) <= MIMOSIS_SDA;\r
- PIN(3) <= MIMOSIS_SCL;\r
- MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
- MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+ -- PIN(4) <= MIMOSIS_SDA;\r
+ -- PIN(3) <= MIMOSIS_SCL;\r
+ -- MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z';\r
+ -- MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z';\r
\r
+PIN(4) <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z';\r
+PIN(3) <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z';\r
+ \r
+ \r
H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC\r
PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START\r
PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET\r