From: Jan Michel Date: Tue, 23 Jun 2015 16:18:52 +0000 (+0200) Subject: fixed reset in reset_handler X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=006b097d9999b9d62ad1c27f69b76b582b48b9d9;p=trb3sc.git fixed reset in reset_handler --- diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 4f504b2..6ad71bd 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -49,6 +49,7 @@ signal clock_select : std_logic := '0'; signal timer : unsigned(15 downto 0) := (others => '0'); signal clear_n_i : std_logic := '0'; +signal reset_i : std_logic; attribute syn_keep of clear_n_i : signal is true; attribute syn_preserve of clear_n_i : signal is true; @@ -200,10 +201,11 @@ THE_RESET_HANDLER : trb_net_reset_handler RESET_IN => '0', -- general reset signal (SYSCLK) TRB_RESET_IN => RESET_FROM_NET, -- TRBnet reset signal (SYSCLK) CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE! - RESET_OUT => RESET_OUT, -- synchronous reset out (SYSCLK) + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) DEBUG_OUT => open ); +RESET_OUT <= reset_i; ---------------------------------------------------------------------------