From: Jan Michel <j.michel@gsi.de>
Date: Thu, 7 Jan 2016 15:59:18 +0000 (+0100)
Subject: flexible clock speed for UART interface
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=006d41e1dd05e0cf21b3af5fec3f54863f01330c;p=padiwa.git

flexible clock speed for UART interface
---

diff --git a/source/uart_sctrl.vhd b/source/uart_sctrl.vhd
index d4ef19b..48eb2c5 100644
--- a/source/uart_sctrl.vhd
+++ b/source/uart_sctrl.vhd
@@ -11,6 +11,9 @@ use machxo2.all;
 
 
 entity uart_sctrl is
+  generic(
+    CLOCK_SPEED : integer := 133000000
+    );
   port(
     CLK     : in  std_logic;
     RESET   : in  std_logic;
@@ -31,7 +34,7 @@ end entity;
 
 architecture uart_sctrl_arch of uart_sctrl is
 
-constant CLK_DIV : integer := 133000000/115200;
+constant CLK_DIV : integer := CLOCK_SPEED/115200;
 
 signal rx_data   : std_logic_vector(7 downto 0);
 signal tx_data   : std_logic_vector(7 downto 0);