From: hadeshyp Date: Mon, 5 Sep 2011 17:06:45 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=01f1e4e4f5a130095bddce298680a10a9a042bd2;p=trb3.git *** empty log message *** --- diff --git a/base/compile_central_frankfurt.pl b/base/compile_central_frankfurt.pl index 7e2ddd7..750ca14 100755 --- a/base/compile_central_frankfurt.pl +++ b/base/compile_central_frankfurt.pl @@ -9,6 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_central"; #Name of top-level entity +my $BasePath = "../base/"; #path to "base" directory my $lattice_path = '/d/sugar/lattice/diamond/1.3'; my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/'; my $lm_license_file_for_synplify = "27000\@localhost"; @@ -34,11 +35,11 @@ $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; my $FAMILYNAME="LatticeECP3"; my $DEVICENAME="LFE3-150EA"; my $PACKAGE="FPBGA1156"; -my $SPEEDGRADE="7"; +my $SPEEDGRADE="8"; #create full lpf file -system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cp $BasePath/$TOPNAME.lpf workdir/$TOPNAME.lpf"); system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); #set -e diff --git a/base/compile_central_gsi.pl b/base/compile_central_gsi.pl index 7e2ddd7..fc412cb 100755 --- a/base/compile_central_gsi.pl +++ b/base/compile_central_gsi.pl @@ -34,7 +34,7 @@ $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; my $FAMILYNAME="LatticeECP3"; my $DEVICENAME="LFE3-150EA"; my $PACKAGE="FPBGA1156"; -my $SPEEDGRADE="7"; +my $SPEEDGRADE="8"; #create full lpf file diff --git a/base/compile_periph_frankfurt.pl b/base/compile_periph_frankfurt.pl index 8d9178c..8a06d8a 100755 --- a/base/compile_periph_frankfurt.pl +++ b/base/compile_periph_frankfurt.pl @@ -35,7 +35,7 @@ $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; my $FAMILYNAME="LatticeECP3"; my $DEVICENAME="LFE3-150EA"; my $PACKAGE="FPBGA672"; -my $SPEEDGRADE="7"; +my $SPEEDGRADE="8"; #create full lpf file diff --git a/base/compile_periph_gsi.pl b/base/compile_periph_gsi.pl index 8d9178c..8a06d8a 100755 --- a/base/compile_periph_gsi.pl +++ b/base/compile_periph_gsi.pl @@ -35,7 +35,7 @@ $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; my $FAMILYNAME="LatticeECP3"; my $DEVICENAME="LFE3-150EA"; my $PACKAGE="FPBGA672"; -my $SPEEDGRADE="7"; +my $SPEEDGRADE="8"; #create full lpf file diff --git a/base/trb3_central.lpf b/base/trb3_central.lpf index 80c8a2f..2daaa77 100644 --- a/base/trb3_central.lpf +++ b/base/trb3_central.lpf @@ -2,6 +2,19 @@ BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; +################################################################# +# Basic Settings +################################################################# + + SYSCONFIG MCCLK_FREQ = 20; + + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; + FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz; + FREQUENCY PORT CLK_GPLL_LEFT 200 MHz; + FREQUENCY PORT CLK_EXT_3 10 MHz; + FREQUENCY PORT CLK_EXT_4 10 MHz; + ################################################################# # Clock I/O diff --git a/base/trb3_central.prj b/base/trb3_central.prj index 7ba2894..7d32ec3 100644 --- a/base/trb3_central.prj +++ b/base/trb3_central.prj @@ -6,7 +6,7 @@ impl -add workdir -type fpga set_option -technology LATTICE-ECP3 set_option -part LFE3_150EA set_option -package FN1156C -set_option -speed_grade -7 +set_option -speed_grade -8 set_option -part_companion "" # compilation/mapping options @@ -54,10 +54,11 @@ impl -active "workdir" add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib "work" "../base/trb3_components.vhd" add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "./trb3_central.vhd" -add_file -vhdl -lib "work" "../base/trb3_components.vhd" + diff --git a/base/trb3_central.vhd b/base/trb3_central.vhd index 6967cbf..24f49aa 100644 --- a/base/trb3_central.vhd +++ b/base/trb3_central.vhd @@ -16,8 +16,8 @@ entity trb3_central is CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45 CLK_GPLL_LEFT : in std_logic; --Clock Manager 2/9, 200 MHz <-- MAIN CLOCK CLK_GPLL_RIGHT : in std_logic; --Clock Manager 1/9, 125 MHz <-- for GbE - CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200 MHz <-- for Serdes if GPLL doesn't work. Same oscillator as GPLL left! - CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200 MHz <-- use this clock for BASIC tests! + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz --Trigger TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out @@ -78,7 +78,7 @@ entity trb3_central is FLASH_CS : out std_logic; FLASH_CIN : out std_logic; FLASH_DOUT : in std_logic; - PROGRAMN : out std_logic; --reboot FPGA + PROGRAMN : out std_logic := '1'; --reboot FPGA --Misc ENPIRION_CLOCK : out std_logic; --Clock for power supply, not necessary, floating @@ -162,20 +162,20 @@ begin --------------------------------------------------------------------------- -- FPGA communication --------------------------------------------------------------------------- - FPGA1_COMM <= (others => '0'); - FPGA2_COMM <= (others => '0'); - FPGA3_COMM <= (others => '0'); - FPGA4_COMM <= (others => '0'); + FPGA1_COMM <= (others => 'Z'); + FPGA2_COMM <= (others => 'Z'); + FPGA3_COMM <= (others => 'Z'); + FPGA4_COMM <= (others => 'Z'); - FPGA1_TTL <= (others => '0'); - FPGA2_TTL <= (others => '0'); - FPGA3_TTL <= (others => '0'); - FPGA4_TTL <= (others => '0'); + FPGA1_TTL <= (others => 'Z'); + FPGA2_TTL <= (others => 'Z'); + FPGA3_TTL <= (others => 'Z'); + FPGA4_TTL <= (others => 'Z'); - FPGA1_CONNECTOR <= (others => '0'); - FPGA2_CONNECTOR <= (others => '0'); - FPGA3_CONNECTOR <= (others => '0'); - FPGA4_CONNECTOR <= (others => '0'); + FPGA1_CONNECTOR <= (others => 'Z'); + FPGA2_CONNECTOR <= (others => 'Z'); + FPGA3_CONNECTOR <= (others => 'Z'); + FPGA4_CONNECTOR <= (others => 'Z'); --------------------------------------------------------------------------- @@ -184,7 +184,7 @@ begin FLASH_CLK <= '0'; FLASH_CS <= '0'; FLASH_CIN <= '0'; - + PROGRAMN <= '1'; --------------------------------------------------------------------------- -- Big AddOn Connector diff --git a/base/trb3_periph.lpf b/base/trb3_periph.lpf index 50e25de..0bd7816 100644 --- a/base/trb3_periph.lpf +++ b/base/trb3_periph.lpf @@ -2,6 +2,16 @@ BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; +################################################################# +# Basic Settings +################################################################# + + SYSCONFIG MCCLK_FREQ = 20; + + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; + FREQUENCY PORT CLK_GPLL_RIGHT 100 MHz; + FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; ################################################################# # Clock I/O diff --git a/base/trb3_periph.prj b/base/trb3_periph.prj index a594c99..2a86381 100644 --- a/base/trb3_periph.prj +++ b/base/trb3_periph.prj @@ -6,7 +6,7 @@ impl -add workdir -type fpga set_option -technology LATTICE-ECP3 set_option -part LFE3_150EA set_option -package FN672C -set_option -speed_grade -7 +set_option -speed_grade -8 set_option -part_companion "" # compilation/mapping options @@ -54,10 +54,11 @@ impl -active "workdir" add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib "work" "../base/trb3_components.vhd" add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "./trb3_periph.vhd" -add_file -vhdl -lib "work" "../base/trb3_components.vhd" + diff --git a/base/trb3_periph.vhd b/base/trb3_periph.vhd index ea90318..8f140da 100644 --- a/base/trb3_periph.vhd +++ b/base/trb3_periph.vhd @@ -14,9 +14,9 @@ entity trb3_periph is port( --Clocks CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz - CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK - CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200 MHz <-- For TDC. Same oscillator as GPLL right! - CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! --Trigger TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out @@ -100,6 +100,7 @@ architecture trb3_periph_arch of trb3_periph is signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + --TDC clock is separate signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. diff --git a/fpgatest/projects/Strategy1.sty b/fpgatest/projects/Strategy1.sty index e5f3dce..816c208 100644 --- a/fpgatest/projects/Strategy1.sty +++ b/fpgatest/projects/Strategy1.sty @@ -1,3 +1,5 @@ - + + + diff --git a/fpgatest/projects/trb3_central.ldf b/fpgatest/projects/trb3_central.ldf index d2e31d1..0735ae7 100644 --- a/fpgatest/projects/trb3_central.ldf +++ b/fpgatest/projects/trb3_central.ldf @@ -1,5 +1,5 @@ - +