From: hadeshyp Date: Tue, 20 Apr 2010 21:58:25 +0000 (+0000) Subject: updated ipu2gbe and gbe_buf with multievent disabled X-Git-Tag: oldGBE~293 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=02334e6d6334c132d29ccd73444fcfed14a64fd3;p=trbnet.git updated ipu2gbe and gbe_buf with multievent disabled --- diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd index 660c336..438fcad 100755 --- a/gbe_ecp2m/trb_net16_gbe_buf.vhd +++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd @@ -11,8 +11,8 @@ use work.trb_net16_hub_func.all; use work.version.all; entity trb_net16_gbe_buf is -generic( - DO_SIMULATION : integer range c_NO to c_YES := c_NO +generic( + DO_SIMULATION : integer range 0 to 1 := 1 ); port( CLK : in std_logic; @@ -178,7 +178,7 @@ attribute HGROUP of trb_net16_gbe_buf : architecture is "GBE_BUF_group"; -- Interface between IPU channel and packet constructor component trb_net16_ipu2gbe is -port( +port( CLK : in std_logic; RESET : in std_logic; --Event information coming from CTS @@ -232,17 +232,17 @@ port( DBG_SF_AEMPTY_OUT : out std_logic; DBG_SF_FULL_OUT : out std_logic; DBG_SF_AFULL_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(31 downto 0) + DEBUG_OUT : out std_logic_vector(31 downto 0) ); end component; component ip_configurator is -port( +port( CLK : in std_logic; RESET : in std_logic; -- configuration interface START_CONFIG_IN : in std_logic; -- start configuration run - BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank + BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory @@ -420,11 +420,11 @@ port( tx_sndpaustim : in std_logic_vector(15 downto 0); tx_sndpausreq : in std_logic; tx_fifoctrl : in std_logic; - ---------------- Input signals to the Rx MAC FIFO I/F --------------- + ---------------- Input signals to the Rx MAC FIFO I/F --------------- rx_fifo_full : in std_logic; ignore_pkt : in std_logic; -------------------- Output signals from the GMII ----------------------- - txd : out std_logic_vector(7 downto 0); + txd : out std_logic_vector(7 downto 0); tx_en : out std_logic; tx_er : out std_logic; -------------------- Output signals from the CPU I/F ------------------- @@ -432,13 +432,13 @@ port( hdataout_en_n : out std_logic; hready_n : out std_logic; cpu_if_gbit_en : out std_logic; - ---------------- Output signals from the Tx MAC FIFO I/F --------------- + ---------------- Output signals from the Tx MAC FIFO I/F --------------- tx_macread : out std_logic; tx_discfrm : out std_logic; tx_staten : out std_logic; tx_done : out std_logic; tx_statvec : out std_logic_vector(30 downto 0); - ---------------- Output signals from the Rx MAC FIFO I/F --------------- + ---------------- Output signals from the Rx MAC FIFO I/F --------------- rx_fifo_error : out std_logic; rx_stat_vector : out std_logic_vector(31 downto 0); rx_dbout : out std_logic_vector(7 downto 0); @@ -447,7 +447,7 @@ port( rx_eof : out std_logic; rx_error : out std_logic ); -end component; +end component; component mb_mac_sim is port ( @@ -500,7 +500,7 @@ port ( --------------- Receive FIFO interface ----------------------------------- RX_DBOUT : out std_logic_vector(7 downto 0); RX_FIFO_FULL : in std_logic; - IGNORE_PKT : in std_logic; + IGNORE_PKT : in std_logic; RX_FIFO_ERROR : out std_logic; RX_STAT_VECTOR : out std_logic_vector(31 downto 0); RX_STAT_EN : out std_logic; @@ -541,7 +541,7 @@ port( MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0); MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0); MR_AN_PAGE_RX_OUT : out std_logic; - MR_AN_COMPLETE_OUT : out std_logic; + MR_AN_COMPLETE_OUT : out std_logic; MR_AN_ENABLE_IN : in std_logic; MR_RESTART_AN_IN : in std_logic; -- Status and control port @@ -553,7 +553,7 @@ port( end component; component slv_mac_memory is -port( +port( CLK : in std_logic; RESET : in std_logic; BUSY_IN : in std_logic; @@ -689,7 +689,7 @@ signal pcs_an_lp_ability : std_logic_vector(15 downto 0); signal pcs_an_complete : std_logic; signal pcs_an_page_rx : std_logic; -signal pcs_stat_debug : std_logic_vector(63 downto 0); +signal pcs_stat_debug : std_logic_vector(63 downto 0); signal stage_stat_regs : std_logic_vector(31 downto 0); signal stage_ctrl_regs : std_logic_vector(31 downto 0); @@ -721,7 +721,7 @@ fc_protocol <= x"11"; -- IP configurator: allows IP config to change for each event builder THE_IP_CONFIGURATOR: ip_configurator -port map( +port map( CLK => CLK, RESET => RESET, -- configuration interface @@ -745,7 +745,7 @@ port map( -- gk 27.03.01 MB_IP_CONFIG: slv_mac_memory -port map( +port map( CLK => CLK, -- clk_100, RESET => RESET, --reset_i, BUSY_IN => '0', @@ -768,7 +768,7 @@ port map( -- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS THE_IPU_INTERFACE: trb_net16_ipu2gbe -port map( +port map( CLK => CLK, RESET => RESET, --Event information coming from CTS @@ -798,7 +798,7 @@ port map( DATA_GBE_ENABLE_IN => '1', --: in std_logic; -- IPU data is forwarded to GbE DATA_IPU_ENABLE_IN => '0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet MULTI_EVT_ENABLE_IN => '0', --: in std_logic; -- enable multi event packets - MAX_MESSAGE_SIZE_IN => x"0000_1000", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl + MAX_MESSAGE_SIZE_IN => x"0000_FDE8", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl -- PacketConstructor interface PC_WR_EN_OUT => pc_wr_en, PC_DATA_OUT => pc_data, @@ -815,7 +815,7 @@ port map( DBG_REM_CTR_OUT => ig_rem_ctr, DBG_SF_WCNT_OUT => ig_wcnt, DBG_SF_RCNT_OUT => ig_rcnt, - DBG_SF_DATA_OUT => ig_data, + DBG_SF_DATA_OUT => ig_data, DBG_SF_RD_EN_OUT => ig_rd_en, DBG_SF_WR_EN_OUT => ig_wr_en, DBG_SF_EMPTY_OUT => ig_empty, @@ -823,11 +823,11 @@ port map( DBG_SF_FULL_OUT => ig_full, DBG_SF_AFULL_OUT => ig_afull, DEBUG_OUT => ig_debug -); +); -- Second stage: Packet constructor PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr -port map( +port map( -- ports for user logic RESET => RESET, CLK => CLK, @@ -881,10 +881,10 @@ port map( DBG_ACT_QUEUE_SIZE => pc_act_queue_size, DEBUG_OUT => open ); - + -- Third stage: Frame Constructor FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr -port map( +port map( -- ports for user logic RESET => RESET, CLK => CLK, @@ -921,10 +921,10 @@ port map( BSM_CONSTR_OUT => fc_bsm_constr, BSM_TRANS_OUT => fc_bsm_trans, DEBUG_OUT => open -); - +); + FRAME_TRANSMITTER: trb_net16_gbe_frame_trans -port map( +port map( CLK => CLK, RESET => RESET, TX_MAC_CLK => serdes_clk_125, @@ -951,7 +951,7 @@ port map( DBG_INIT_DONE_OUT => open, DBG_ENABLED_OUT => open, DEBUG_OUT => open -); +); -- in case of real hardware, we use the IP cores for MAC and PHY, and also put a SerDes in imp_gen: if (DO_SIMULATION = 0) generate @@ -960,7 +960,7 @@ imp_gen: if (DO_SIMULATION = 0) generate -- Implementation -------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------- - + -- MAC part MAC: tsmac3 port map( @@ -991,7 +991,7 @@ imp_gen: if (DO_SIMULATION = 0) generate tx_sndpaustim => x"0000", tx_sndpausreq => '0', tx_fifoctrl => '0', -- always data frame - ---------------- Input signals to the Rx MAC FIFO I/F --------------- + ---------------- Input signals to the Rx MAC FIFO I/F --------------- rx_fifo_full => '0', ignore_pkt => '0', ---------------- Output signals from the GMII ----------------------- @@ -1003,13 +1003,13 @@ imp_gen: if (DO_SIMULATION = 0) generate hdataout_en_n => mac_hdata_en, hready_n => mac_hready, cpu_if_gbit_en => open, - ------------- Output signals from the Tx MAC FIFO I/F --------------- + ------------- Output signals from the Tx MAC FIFO I/F --------------- tx_macread => mac_tx_read, tx_discfrm => open, tx_staten => open, tx_statvec => open, tx_done => mac_tx_done, - ------------- Output signals from the Rx MAC FIFO I/F --------------- + ------------- Output signals from the Rx MAC FIFO I/F --------------- rx_fifo_error => open, rx_stat_vector => open, rx_dbout => open, @@ -1061,7 +1061,7 @@ imp_gen: if (DO_SIMULATION = 0) generate ); stage_stat_regs(31 downto 28) <= x"d"; - stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link status + stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link status stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm stage_stat_regs(19 downto 18) <= (others => '0'); stage_stat_regs(17) <= pcs_an_complete; @@ -1127,7 +1127,7 @@ sim_gen: if (DO_SIMULATION = 1) generate --------------- Receive FIFO interface ----------------------------------- RX_DBOUT => open, RX_FIFO_FULL => '0', - IGNORE_PKT => '0', + IGNORE_PKT => '0', RX_FIFO_ERROR => open, RX_STAT_VECTOR => open, RX_STAT_EN => open, @@ -1145,7 +1145,7 @@ sim_gen: if (DO_SIMULATION = 1) generate pcs_an_complete <= '1'; mac_tx_clk_en <= '1'; mac_rx_clk_en <= '1'; - + stage_stat_regs(31 downto 0) <= (others => '0'); pcs_stat_debug(63 downto 0) <= (others => '0'); diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd index 0507ccc..8608fa1 100755 --- a/gbe_ecp2m/trb_net16_ipu2gbe.vhd +++ b/gbe_ecp2m/trb_net16_ipu2gbe.vhd @@ -197,6 +197,9 @@ signal load_sub_ctr_comb : std_logic; signal actual_message_size : std_logic_vector(31 downto 0); signal rst_msg : std_logic; signal rst_msg_comb : std_logic; +signal more_subevents : std_logic; +signal data_phase2 : std_logic; +signal data_phase2_comb : std_logic; begin @@ -282,9 +285,9 @@ begin sf_data(15 downto 4) <= x"abc"; -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then - sf_data <= x"5555"; + sf_data <= x"5555"; --x"0001"; -- gk 15.04.10 elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then - sf_data <= x"0001"; + sf_data <= x"0001"; --x"5555"; -- gk 15.04.10 elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then sf_data <= FEE_STATUS_BITS_IN(31 downto 16); elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then @@ -514,7 +517,7 @@ port map( ------------------------------------------------------------------------------------------ -- write signal for PC data -pc_wr_en_comb <= (data_phase and sf_rd_en) or pad_phase or (load_sub and sf_rd_en); -- gk 30.03.10 +pc_wr_en_comb <= (data_phase and sf_rd_en) or pad_phase or (load_sub and sf_rd_en) or data_phase2; -- gk 30.03.10 added load_sub -- gk 20.04.10 added data_phase2 -- FIFO data delay process (also forces padding bytes to known value) THE_DATA_DELAY_PROC: process( CLK ) @@ -546,6 +549,7 @@ begin pad_data <= '0'; load_sub <= '0'; -- gk 30.03.10 rst_msg <= '0'; -- gk 08.04.10 + data_phase2 <= '0'; -- gk 20.04.10 else loadCurrentState <= loadNextState; rst_rem_ctr <= rst_rem_ctr_comb; @@ -559,6 +563,7 @@ begin pad_data <= pad_data_comb; load_sub <= load_sub_comb; -- gk 30.03.10 rst_msg <= rst_msg_comb; -- gk 08.04.10 + data_phase2 <= data_phase2_comb; -- gk 20.04.10 end if; end if; end process loadMachineProc; @@ -585,6 +590,7 @@ begin pad_data_comb <= '0'; load_sub_comb <= '0'; -- gk 30.03.10 rst_msg_comb <= '0'; -- gk 08.04.10 + data_phase2_comb <= '0'; -- gk 20.04.10 case loadCurrentState is when LIDLE => state2 <= x"0"; @@ -604,11 +610,16 @@ begin when REMOVE => state2 <= x"2"; if( remove_done = '1' ) then - if(actual_message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then + if (MULTI_EVT_ENABLE_IN = '1') then + if(actual_message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then + loadNextState <= CALCA; + calc_pad_comb <= '1'; + else + loadNextState <= CALCC; + end if; + else loadNextState <= CALCA; calc_pad_comb <= '1'; - else - loadNextState <= CALCC; end if; else loadNextState <= REMOVE; @@ -622,7 +633,12 @@ begin -- we need a branch in case of length "0"!!!! state2 <= x"4"; loadNextState <= LOAD; - data_phase_comb <= '1'; + -- gk 20.04.2010 + if (more_subevents = '0') then + data_phase_comb <= '1'; + else + data_phase2_comb <= '1'; + end if; when LOAD => state2 <= x"5"; -- gk 31.03.10 after loading subevent data read the subsubevent from sf @@ -643,9 +659,13 @@ begin state2 <= x"d"; if( load_sub_done = '1' ) then if( padding_needed = '0' ) then - loadNextState <= INIT; --CALCC; -- gk 08.04.10 - rst_rem_ctr_comb <= '1'; -- gk 08.04.10 - rst_regs_comb <= '1'; -- gk 08.04.10 + if (MULTI_EVT_ENABLE_IN = '1') then + loadNextState <= INIT; --CALCC; -- gk 08.04.10 + rst_rem_ctr_comb <= '1'; -- gk 08.04.10 + rst_regs_comb <= '1'; -- gk 08.04.10 + else + loadNextState <= CALCC; + end if; else loadNextState <= PAD0; pad_phase_comb <= '1'; @@ -671,10 +691,14 @@ begin pad_data_comb <= '1'; when PAD3 => state2 <= x"9"; - loadNextState <= INIT; --CALCC; --LOAD_SUBSUB; --CALCC; -- gk 30.03.10 -- gk 31.03.10 -- gk 08.04.10 + if (MULTI_EVT_ENABLE_IN = '1') then + loadNextState <= INIT; --CALCC; --LOAD_SUBSUB; --CALCC; -- gk 30.03.10 -- gk 31.03.10 -- gk 08.04.10 + rst_rem_ctr_comb <= '1'; -- gk 08.04.10 + rst_regs_comb <= '1'; -- gk 08.04.10 + else + loadNextState <= CALCC; + end if; pad_data_comb <= '1'; - rst_rem_ctr_comb <= '1'; -- gk 08.04.10 - rst_regs_comb <= '1'; -- gk 08.04.10 -- gk 31.03.10 the load_subsub state moved straight after load and before padding -- gk 30.03.10 -- when LOAD_SUBSUB => @@ -697,8 +721,12 @@ begin when WAIT_PC => state2 <= x"c"; if( PC_READY_IN = '1' ) then - loadNextState <= CALCA; --LIDLE; -- gk 08.04.10 - calc_pad_comb <= '1'; -- gk 08.04.10 + if (MULTI_EVT_ENABLE_IN = '1') then + loadNextState <= CALCA; --LIDLE; -- gk 08.04.10 + calc_pad_comb <= '1'; -- gk 08.04.10 + else + loadNextState <= LIDLE; + end if; else loadNextState <= WAIT_PC; end if; @@ -739,6 +767,18 @@ begin end if; end process LOAD_SUB_DONE_PROC; +-- gk 20.04.10 +MORE_SUBEVENTS_PROC : process(CLK) +begin + if rising_edge(CLK) then + if( (RESET = '1') or (rst_msg = '1') ) then + more_subevents <= '0'; + elsif (data_phase = '1') then + more_subevents <= '1'; + end if; + end if; +end process MORE_SUBEVENTS_PROC; + -- Counter for stripping the unneeded parts of the data stream, and saving the important parts THE_REMOVE_CTR: process( CLK ) begin