From: hadaq Date: Mon, 15 Jun 2009 14:58:57 +0000 (+0000) Subject: RX_K and RX_DATA delay register X-Git-Tag: oldGBE~432 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0397623444b97f4eedc4713247754de8a35f50a3;p=trbnet.git RX_K and RX_DATA delay register --- diff --git a/media_interfaces/trb_net16_med_ecp_sfp.vhd b/media_interfaces/trb_net16_med_ecp_sfp.vhd index 0177f21..eec57ec 100644 --- a/media_interfaces/trb_net16_med_ecp_sfp.vhd +++ b/media_interfaces/trb_net16_med_ecp_sfp.vhd @@ -15,11 +15,11 @@ entity trb_net16_med_ecp_sfp is SERDES_NUM : integer range 0 to 3 := 2 ); port( - CLK : in std_logic; -- SerDes clock - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; --Internal Connection MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); @@ -39,6 +39,7 @@ entity trb_net16_med_ecp_sfp is SD_REFCLK_N_IN : in std_logic; SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable -- Status and control port STAT_OP : out std_logic_vector (15 downto 0); CTRL_OP : in std_logic_vector (15 downto 0); @@ -49,6 +50,12 @@ end entity; architecture med_ecp_sfp of trb_net16_med_ecp_sfp is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of med_ecp_sfp : architecture is "MEDIA_INTERFACE_group"; + component serdes_sfp_0 port( core_txrefclk : in std_logic; @@ -232,29 +239,29 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is component trb_net16_lsm_sfp is port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available -- status signals - SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established) - SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost) - SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked) - SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked) - SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope - SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct) - SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD) - -- control signals - FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset - LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset - TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation - RX_ALLOW_OUT : out std_logic; -- allow normal receive operation - SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order) + SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established) + SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost) + SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked) + SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked) + SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct) + SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD) + -- control signals + FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset + LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset + TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation + RX_ALLOW_OUT : out std_logic; -- allow normal receive operation + SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order) -- debug signals - STAT_OP : out std_logic_vector(15 downto 0); - CTRL_OP : in std_logic_vector(15 downto 0); - STAT_DEBUG : out std_logic_vector(31 downto 0) + STAT_OP : out std_logic_vector(15 downto 0); + CTRL_OP : in std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(31 downto 0) ); end component; @@ -262,18 +269,18 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is generic( USE_STATUS_FLAGS : integer := c_YES ); - port( read_clock_in : in std_logic; - write_clock_in : in std_logic; - read_enable_in : in std_logic; - write_enable_in : in std_logic; - fifo_gsr_in : in std_logic; - write_data_in : in std_logic_vector(17 downto 0); + port( read_clock_in : in std_logic; + write_clock_in : in std_logic; + read_enable_in : in std_logic; + write_enable_in : in std_logic; + fifo_gsr_in : in std_logic; + write_data_in : in std_logic_vector(17 downto 0); read_data_out : out std_logic_vector(17 downto 0); - full_out : out std_logic; - empty_out : out std_logic; - fifostatus_out : out std_logic_vector(3 downto 0); - valid_read_out : out std_logic; - almost_empty_out : out std_logic; + full_out : out std_logic; + empty_out : out std_logic; + fifostatus_out : out std_logic_vector(3 downto 0); + valid_read_out : out std_logic; + almost_empty_out : out std_logic; almost_full_out : out std_logic ); end component; @@ -284,134 +291,180 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is DEPTH : integer := 3 ); port( - RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register - CLK0 : in std_logic; --clock for first FF - CLK1 : in std_logic; --Clock for other FF - D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input - D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output + RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register + CLK0 : in std_logic; --clock for first FF + CLK1 : in std_logic; --Clock for other FF + D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input + D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output ); end component; - signal refck2core : std_logic; - signal clock : std_logic; - --reset signals - signal ffc_quad_rst : std_logic; - signal ffc_lane_tx_rst : std_logic; - signal ffc_lane_rx_rst : std_logic; - --serdes connections - signal tx_data : std_logic_vector(15 downto 0); - signal tx_k : std_logic_vector(1 downto 0); - signal rx_data : std_logic_vector(15 downto 0); - signal rx_k : std_logic_vector(1 downto 0); - signal link_ok : std_logic_vector(0 downto 0); - signal link_error : std_logic_vector(8 downto 0); - signal ff_rxhalfclk : std_logic; - signal ff_txhalfclk : std_logic; - --rx fifo signals - signal fifo_rx_rd_en : std_logic; - signal fifo_rx_wr_en : std_logic; - signal fifo_rx_reset : std_logic; - signal fifo_rx_din : std_logic_vector(17 downto 0); - signal fifo_rx_dout : std_logic_vector(17 downto 0); - signal fifo_rx_full : std_logic; - signal fifo_rx_empty : std_logic; - --tx fifo signals - signal fifo_tx_rd_en : std_logic; - signal fifo_tx_wr_en : std_logic; - signal fifo_tx_reset : std_logic; - signal fifo_tx_din : std_logic_vector(17 downto 0); - signal fifo_tx_dout : std_logic_vector(17 downto 0); - signal fifo_tx_full : std_logic; - signal fifo_tx_empty : std_logic; + signal refck2core : std_logic; +-- signal clock : std_logic; + --reset signals + signal ffc_quad_rst : std_logic; + signal ffc_lane_tx_rst : std_logic; + signal ffc_lane_rx_rst : std_logic; + --serdes connections + signal tx_data : std_logic_vector(15 downto 0); + signal tx_k : std_logic_vector(1 downto 0); + signal rx_data : std_logic_vector(15 downto 0); -- delayed signals + signal rx_k : std_logic_vector(1 downto 0); -- delayed signals + signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP + signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP + signal link_ok : std_logic_vector(0 downto 0); + signal link_error : std_logic_vector(8 downto 0); + signal ff_rxhalfclk : std_logic; + signal ff_txhalfclk : std_logic; + --rx fifo signals + signal fifo_rx_rd_en : std_logic; + signal fifo_rx_wr_en : std_logic; + signal fifo_rx_reset : std_logic; + signal fifo_rx_din : std_logic_vector(17 downto 0); + signal fifo_rx_dout : std_logic_vector(17 downto 0); + signal fifo_rx_full : std_logic; + signal fifo_rx_empty : std_logic; + --tx fifo signals + signal fifo_tx_rd_en : std_logic; + signal fifo_tx_wr_en : std_logic; + signal fifo_tx_reset : std_logic; + signal fifo_tx_din : std_logic_vector(17 downto 0); + signal fifo_tx_dout : std_logic_vector(17 downto 0); + signal fifo_tx_full : std_logic; + signal fifo_tx_empty : std_logic; --rx path - signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_med_dataready_out : std_logic; - signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal last_rx : std_logic_vector(8 downto 0); - signal last_fifo_rx_empty : std_logic; + signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal last_rx : std_logic_vector(8 downto 0); + signal last_fifo_rx_empty : std_logic; --tx path - signal last_fifo_tx_empty : std_logic; + signal last_fifo_tx_empty : std_logic; --link status - signal link_led : std_logic; - signal rx_k_q : std_logic_vector(1 downto 0); + signal link_led : std_logic; + signal rx_k_q : std_logic_vector(1 downto 0); - signal info_led : std_logic; + signal info_led : std_logic; - signal quad_rst : std_logic; - signal lane_rst : std_logic; - signal tx_allow : std_logic; - signal rx_allow : std_logic; + signal quad_rst : std_logic; + signal lane_rst : std_logic; + signal tx_allow : std_logic; + signal rx_allow : std_logic; - signal rx_allow_q : std_logic; -- clock domain changed signal - signal tx_allow_q : std_logic; - signal swap_bytes : std_logic; - signal buf_stat_debug : std_logic_vector(31 downto 0); + signal rx_allow_q : std_logic; -- clock domain changed signal + signal tx_allow_q : std_logic; + signal swap_bytes : std_logic; + signal buf_stat_debug : std_logic_vector(31 downto 0); -- status inputs from SFP - signal sfp_prsnt_n : std_logic; -- synchronized input signals - signal sfp_los : std_logic; -- synchronized input signals + signal sfp_prsnt_n : std_logic; -- synchronized input signals + signal sfp_los : std_logic; -- synchronized input signals - signal buf_STAT_OP : std_logic_vector(15 downto 0); + signal buf_STAT_OP : std_logic_vector(15 downto 0); - signal led_counter : std_logic_vector(17 downto 0); - signal rx_led, tx_led : std_logic; + signal led_counter : std_logic_vector(17 downto 0); + signal rx_led : std_logic; + signal tx_led : std_logic; begin -------------------------------------------------------------------------- --- Main control state machine, startup control for SFP +-- Synchronizer stages -------------------------------------------------------------------------- -clock <= SYSCLK; - --- Input synchronizer +-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP) THE_SFP_STATUS_SYNC: signal_sync generic map( DEPTH => 3, WIDTH => 2 ) port map( - RESET => RESET, - D_IN(0) => SD_PRSNT_N_IN, - D_IN(1) => SD_LOS_IN, - CLK0 => clock, - CLK1 => clock, + RESET => reset, + D_IN(0) => sd_prsnt_n_in, + D_IN(1) => sd_los_in, + CLK0 => sysclk, + CLK1 => sysclk, D_OUT(0) => sfp_prsnt_n, D_OUT(1) => sfp_los ); --- Transfering the komma delimiter in the *training* phase +-- Komma delimiter transfer for training phase THE_RX_K_SYNC: signal_sync generic map( DEPTH => 3, WIDTH => 2 ) port map( - RESET => RESET, - D_IN => rx_k, + RESET => reset, + D_IN => comb_rx_k, -- rx_k CLK0 => ff_rxhalfclk, - CLK1 => clock, + CLK1 => sysclk, D_OUT => rx_k_q ); ----------------------------------------------------------------------------------------------------------- --- NEW STATEMACHINE START ----------------------------------------------------------------------------------------------------------- +-- delay line for RX_K and RX_DATA (directly from SFP to fabric logic) +THE_RX_DATA_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 16 + ) + port map( + RESET => reset, + D_IN => comb_rx_data, + CLK0 => ff_rxhalfclk, + CLK1 => ff_rxhalfclk, + D_OUT => rx_data + ); + +THE_RX_K_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset, + D_IN => comb_rx_k, + CLK0 => ff_rxhalfclk, + CLK1 => ff_rxhalfclk, + D_OUT => rx_k + ); + + +-- Transfer for ALLOW signals +THE_RX_ALLOW_SYNC: signal_sync -- really needed?!? + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => RESET, + D_IN(0) => rx_allow, + D_IN(1) => tx_allow, + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT(0) => rx_allow_q, + D_OUT(1) => tx_allow_q + ); + +-------------------------------------------------------------------------- +-- Main control state machine, startup control for SFP +-------------------------------------------------------------------------- + THE_SFP_LSM: trb_net16_lsm_sfp port map( - SYSCLK => clock, + SYSCLK => sysclk, RESET => reset, CLEAR => clear, SFP_MISSING_IN => sfp_prsnt_n, SFP_LOS_IN => sfp_los, - SD_LINK_OK_IN => link_ok(0), + SD_LINK_OK_IN => link_ok(0), SD_LOS_IN => link_error(8), SD_TXCLK_BAD_IN => link_error(5), SD_RXCLK_BAD_IN => link_error(4), SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope - SD_ALIGNMENT_IN => rx_k_q, + SD_ALIGNMENT_IN => rx_k_q, SD_CV_IN => link_error(7 downto 6), FULL_RESET_OUT => quad_rst, LANE_RESET_OUT => lane_rst, @@ -422,24 +475,8 @@ THE_SFP_LSM: trb_net16_lsm_sfp CTRL_OP => ctrl_op, STAT_DEBUG => buf_stat_debug ); ----------------------------------------------------------------------------------------------------------- --- NEW STATEMACHINE STOP ----------------------------------------------------------------------------------------------------------- - -THE_RX_ALLOW_SYNC: signal_sync -- really needed?!? - generic map( - DEPTH => 2, - WIDTH => 2 - ) - port map( - RESET => RESET, - D_IN(0) => rx_allow, - D_IN(1) => tx_allow, - CLK0 => clock, --ff_rxhalfclk, - CLK1 => clock, --ff_rxhalfclk, - D_OUT(0) => rx_allow_q, - D_OUT(1) => tx_allow_q - ); + +sd_txdis_out <= quad_rst; -------------------------------------------------------------------------- -------------------------------------------------------------------------- @@ -449,7 +486,7 @@ ffc_lane_tx_rst <= lane_rst; ffc_lane_rx_rst <= lane_rst; -- SerDes clock output to FPGA fabric -REFCLK2CORE_OUT <= refck2core; +refclk2core_out <= refck2core; -- Instantiation of serdes module gen_serdes_0 : if SERDES_NUM = 0 generate @@ -477,8 +514,8 @@ REFCLK2CORE_OUT <= refck2core; ffc_trst => '0', hdoutp0 => sd_txd_p_out, hdoutn0 => sd_txd_n_out, - ff_rxdata_ch0 => rx_data, --comb_rx_data, - ff_rx_k_cntrl_ch0 => rx_k, --comb_rx_k, + ff_rxdata_ch0 => comb_rx_data, --rx_data, + ff_rx_k_cntrl_ch0 => comb_rx_k, --rx_k, ff_rxfullclk_ch0 => open, ff_rxhalfclk_ch0 => ff_rxhalfclk, ff_disp_err_ch0 => open, @@ -522,8 +559,8 @@ REFCLK2CORE_OUT <= refck2core; ffc_trst => '0', hdoutp1 => sd_txd_p_out, hdoutn1 => sd_txd_n_out, - ff_rxdata_ch1 => rx_data, --comb_rx_data, - ff_rx_k_cntrl_ch1 => rx_k, --comb_rx_k, + ff_rxdata_ch1 => comb_rx_data, --rx_data, + ff_rx_k_cntrl_ch1 => comb_rx_k, --rx_k, ff_rxfullclk_ch1 => open, ff_rxhalfclk_ch1 => ff_rxhalfclk, ff_disp_err_ch1 => open, @@ -567,8 +604,8 @@ REFCLK2CORE_OUT <= refck2core; ffc_trst => '0', hdoutp2 => sd_txd_p_out, hdoutn2 => sd_txd_n_out, - ff_rxdata_ch2 => rx_data, --comb_rx_data, - ff_rx_k_cntrl_ch2 => rx_k, --comb_rx_k, + ff_rxdata_ch2 => comb_rx_data, --rx_data, + ff_rx_k_cntrl_ch2 => comb_rx_k, --rx_k, ff_rxfullclk_ch2 => open, ff_rxhalfclk_ch2 => ff_rxhalfclk, ff_disp_err_ch2 => open, @@ -612,8 +649,8 @@ REFCLK2CORE_OUT <= refck2core; ffc_trst => '0', hdoutp3 => sd_txd_p_out, hdoutn3 => sd_txd_n_out, - ff_rxdata_ch3 => rx_data, --comb_rx_data, - ff_rx_k_cntrl_ch3 => rx_k, --comb_rx_k, + ff_rxdata_ch3 => comb_rx_data, --rx_data, + ff_rx_k_cntrl_ch3 => comb_rx_k, --rx_k, ff_rxfullclk_ch3 => open, ff_rxhalfclk_ch3 => ff_rxhalfclk, ff_disp_err_ch3 => open, @@ -641,18 +678,18 @@ THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport generic map( USE_STATUS_FLAGS => c_NO ) -port map( read_clock_in => clock, - write_clock_in => ff_rxhalfclk, - read_enable_in => fifo_rx_rd_en, - write_enable_in => fifo_rx_wr_en, - fifo_gsr_in => fifo_rx_reset, - write_data_in => fifo_rx_din, - read_data_out => fifo_rx_dout, - full_out => fifo_rx_full, - empty_out => fifo_rx_empty +port map( read_clock_in => sysclk, + write_clock_in => ff_rxhalfclk, + read_enable_in => fifo_rx_rd_en, + write_enable_in => fifo_rx_wr_en, + fifo_gsr_in => fifo_rx_reset, + write_data_in => fifo_rx_din, + read_data_out => fifo_rx_dout, + full_out => fifo_rx_full, + empty_out => fifo_rx_empty ); -fifo_rx_reset <= RESET or not rx_allow_q; +fifo_rx_reset <= reset or not rx_allow_q; fifo_rx_rd_en <= '1'; -- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path @@ -675,9 +712,9 @@ buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and n buf_med_packet_num_out <= rx_counter; med_read_out <= tx_allow_q; -THE_SYNC_PROC: process( clock ) +THE_SYNC_PROC: process( sysclk ) begin - if( rising_edge(clock) ) then + if( rising_edge(sysclk) ) then if RESET = '1' then med_dataready_out <= '0'; else @@ -690,9 +727,9 @@ end process THE_SYNC_PROC; --rx packet counter --------------------- -THE_RX_PACKETS_PROC: process( clock ) +THE_RX_PACKETS_PROC: process( sysclk ) begin - if( rising_edge(clock) ) then + if( rising_edge(sysclk) ) then last_fifo_rx_empty <= fifo_rx_empty; if RESET = '1' or rx_allow_q = '0' then rx_counter <= c_H0; @@ -714,15 +751,15 @@ THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport generic map( USE_STATUS_FLAGS => c_NO ) -port map( read_clock_in => ff_txhalfclk, - write_clock_in => clock, - read_enable_in => fifo_tx_rd_en, - write_enable_in => fifo_tx_wr_en, - fifo_gsr_in => fifo_tx_reset, - write_data_in => fifo_tx_din, - read_data_out => fifo_tx_dout, - full_out => fifo_tx_full, - empty_out => fifo_tx_empty +port map( read_clock_in => ff_txhalfclk, + write_clock_in => sysclk, + read_enable_in => fifo_tx_rd_en, + write_enable_in => fifo_tx_wr_en, + fifo_gsr_in => fifo_tx_reset, + write_data_in => fifo_tx_din, + read_data_out => fifo_tx_dout, + full_out => fifo_tx_full, + empty_out => fifo_tx_empty ); fifo_tx_reset <= reset or not tx_allow_q; @@ -753,9 +790,9 @@ end process THE_SERDES_INPUT_PROC; --Generate LED signals ---------------------- -process(clock) +process(sysclk) begin - if rising_edge(clock) then + if rising_edge(sysclk) then led_counter <= led_counter + 1; if buf_med_dataready_out = '1' then