From: Cahit <c.ugur@gsi.de>
Date: Wed, 3 Sep 2014 08:13:42 +0000 (+0200)
Subject: conflict fix and merge
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0494cacce49864c42347e65399eaa1c55b511e72;p=trbnet.git

conflict fix and merge
---

0494cacce49864c42347e65399eaa1c55b511e72
diff --cc trb_net_std.vhd
index 9e251ee,d62e1dc..24c7a6f
--- a/trb_net_std.vhd
+++ b/trb_net_std.vhd
@@@ -149,9 -149,57 +149,58 @@@ package trb_net_std i
    --constant VERSION_NUMBER_TIME  : std_logic_vector(31 downto 0)   := conv_std_logic_vector(1234567890,32);
  
  
+   type CTRLBUS_TX is record
+     data       : std_logic_vector(31 downto 0);
+     ack        : std_logic;
+     wack,rack  : std_logic; --for the old-fashioned guys
+     unknown    : std_logic;
+     nack       : std_logic;
+   end record;
+ 
+   type CTRLBUS_RX is record
+     data       : std_logic_vector(31 downto 0);
+     addr       : std_logic_vector(15 downto 0);
+     write      : std_logic;
+     read       : std_logic;
+     timeout    : std_logic;
+   end record; 
+ 
+   
+   type READOUT_RX is record 
+     data_valid         : std_logic;
+     valid_timing_trg   : std_logic;
+     valid_notiming_trg : std_logic;
+     invalid_trg        : std_logic;
+     --
+     trg_type           : std_logic_vector( 3 downto 0);
+     trg_number         : std_logic_vector(15 downto 0);
+     trg_code           : std_logic_vector( 7 downto 0);
+     trg_information    : std_logic_vector(23 downto 0);
+     trg_int_number     : std_logic_vector(15 downto 0);    
+     --
+     trg_multiple       : std_logic;
+     trg_timeout        : std_logic;
+     trg_spurious       : std_logic;
+     trg_missing        : std_logic;
+     trg_spike          : std_logic;
+     --
+     buffer_almost_full : std_logic;
+   end record; 
+   
+   
+   type READOUT_TX is record
+     busy_release  : std_logic;
+     statusbits    : std_logic_vector(31 downto 0);
+     data          : std_logic_vector(31 downto 0);
+     data_write    : std_logic;
+     data_finished : std_logic;
+   end record;
+     
+     
+     
    type std_logic_vector_array_36 is array (integer range <>) of std_logic_vector(35 downto 0);
    type std_logic_vector_array_32 is array (integer range <>) of std_logic_vector(31 downto 0);
 +  type std_logic_vector_array_31 is array (integer range <>) of std_logic_vector(30 downto 0);
    type std_logic_vector_array_24 is array (integer range <>) of std_logic_vector(23 downto 0);
    type std_logic_vector_array_11 is array (integer range <>) of std_logic_vector(10 downto 0);
    type std_logic_vector_array_8  is array (integer range <>) of std_logic_vector(7 downto 0);