From: hadeshyp <hadeshyp>
Date: Fri, 18 Jan 2013 13:46:03 +0000 (+0000)
Subject: few changes in general remarks, JM
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=054a8732a18d18c4c5d2623c3d3e87f92a2d8e00;p=daqdocu.git

few changes in general remarks, JM
---

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index 37aed21..88d2a93 100644
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -53,8 +53,9 @@ The lower 16 Bit are used to identify the contents of the design and the AddOn b
 \begin{description*}
 \item[Central FPGA]~
 \begin{description*}
-  \item[c000]  contains a CTS
-  \item[c001]  contains a CTS, use with AddOn for trigger signals
+  \item[cXX0]  contains a CTS
+  \item[cXX1]  contains a CTS, use with AddOn for trigger signals
+  \item[8XXX]  uses RX clock as main internal clock
   \item[0e00]  contains a GbE link for slow control and read-out
   \item[0d00]  contains a GbE link for read-out only
   \item[0010]  accepts triggers from optical link SFP1
@@ -69,6 +70,7 @@ The lower 16 Bit are used to identify the contents of the design and the AddOn b
   \item[2XXX]  use with multipurpose test AddOn
   \item[3XXX]  use with SFP hub AddOn
   \item[4XXX]  use with Wasa adapter AddOn
+  \item[8XXX]  uses RX clock as main internal clock
   \item[X0nX]  contains $2^n$ TDC channels, single edge
   \item[X1nX]  contains $2^n$ TDC channels, double edge
   \item[X2XX]  contains a network hub
@@ -96,10 +98,8 @@ The initial address set with \signal{Regio\_Init\_Address} can be chosen from th
 \begin{itemize*}
  \item 0xF300 for the central FPGA
  \item 0xF305 for the peripheral FPGA
- \item 0xF301 for a design for FPGA 1 only
- \item 0xF302 for a design for FPGA 2 only
- \item 0xF303 for a design for FPGA 3 only
- \item 0xF304 for a design for FPGA 4 only
+ \item 0xF30n for a design for FPGA n only
+ \item 0xF3C0 default for a design with CTS
 \end{itemize*}
 
 
diff --git a/trb3/main.tex b/trb3/main.tex
index 932aea9..f484f01 100755
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -194,6 +194,8 @@
       \input{CtsSlowControl}
   \cleardoublepage
 
+  \section{Media Interfaces}
+    \input{MediaInterfaces}
 
 \part{Experimental Setups and Configurations}
   \section{Trigger Time vs Reference Time}