From: palka <palka>
Date: Mon, 5 May 2008 08:53:57 +0000 (+0000)
Subject: Some port signals added
X-Git-Tag: oldGBE~562
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0668e96e7220b91ae3c6e1020d7e50268ec3bcd9;p=trbnet.git

Some port signals added
---

diff --git a/optical_link/flexi_PCS_synch.vhd b/optical_link/flexi_PCS_synch.vhd
index 884017b..dd2d56b 100644
--- a/optical_link/flexi_PCS_synch.vhd
+++ b/optical_link/flexi_PCS_synch.vhd
@@ -22,7 +22,7 @@ entity flexi_PCS_synch is
     CV                     : in  std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
     MED_DATA_IN            : in  std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
     TXD_SYNCH              : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
-    TX_FORCE_DISP          : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+    TX_K                   : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
     MED_DATAREADY_IN       : in  std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
     MED_DATAREADY_OUT      : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
     FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
@@ -30,13 +30,16 @@ entity flexi_PCS_synch is
     MED_PACKET_NUM_OUT     : out std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
     MED_READ_IN            : in  std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
     MED_READ_OUT           : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
-    MED_ERROR_OUT          : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0)
+    MED_ERROR_OUT          : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
+    MED_STAT_OP           : out  std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0);
+    MED_CTRL_OP           : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0)
     );
 end flexi_PCS_synch;
 architecture flexi_PCS_synch of flexi_PCS_synch is
   component flexi_PCS_channel_synch
     port (
-      CLK              : in  std_logic;
+      SYSTEM_CLK       : in  std_logic;      
+      TX_CLK           : in  std_logic;
       RX_CLK           : in  std_logic;
       RESET            : in  std_logic;
       RXD              : in  std_logic_vector(15 downto 0);
@@ -46,21 +49,24 @@ architecture flexi_PCS_synch of flexi_PCS_synch is
       CV               : in  std_logic_vector(1 downto 0);
       TXD              : in  std_logic_vector(15 downto 0);
       TXD_SYNCH        : out std_logic_vector(15 downto 0);
-      TX_FORCE_DISP    : out std_logic_vector(1 downto 0);
+      TX_K             : out std_logic_vector(1 downto 0);
       DATA_VALID_IN    : in  std_logic;
       DATA_VALID_OUT   : out std_logic;
       FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0);
-      MED_PACKET_NUM_OUT : out std_logic_vector(1 downto 0)
+      MED_PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
+      MED_ERROR_OUT      : out std_logic_vector(2 downto 0);
+      MED_READ_IN        : in std_logic
       );
   end component;
 begin
   CHANNEL_GENERATE : for bit_index in 0 to HOW_MANY_CHANNELS-1 generate
   begin
     MED_READ_OUT <= (others => '1');
-    MED_ERROR_OUT <= (others => '0');
+
     SYNCH :flexi_PCS_channel_synch
       port map (
-          CLK              => CLK(bit_index/4),      --4 different channles clk
+          SYSTEM_CLK       => CLK(0),
+          TX_CLK           => CLK(bit_index/4),      --4 different channles clk
           RX_CLK           => RX_CLK(bit_index),                              
           RESET            => RESET,
           RXD              => RXD((bit_index*16+15) downto bit_index*16),
@@ -70,11 +76,13 @@ begin
           CV               => CV((bit_index*2+1) downto bit_index*2),
           TXD              => MED_DATA_IN((bit_index*16+15) downto bit_index*16),
           TXD_SYNCH        => TXD_SYNCH((bit_index*16+15) downto bit_index*16),
-          TX_FORCE_DISP    => TX_FORCE_DISP(bit_index*2+1 downto bit_index*2),
+          TX_K             => TX_K(bit_index*2+1 downto bit_index*2),
           DATA_VALID_IN    => MED_DATAREADY_IN(bit_index),
           DATA_VALID_OUT   => MED_DATAREADY_OUT(bit_index),
           FLEXI_PCS_STATUS => FLEXI_PCS_SYNCH_STATUS((bit_index*16+15) downto bit_index*16),
-          MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((bit_index*2+1) downto bit_index*2)
+          MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((bit_index*2+1) downto bit_index*2),
+          MED_ERROR_OUT => MED_ERROR_OUT((bit_index*3+2) downto bit_index*3),
+          MED_READ_IN   => MED_READ_IN(bit_index)
           );
   end generate CHANNEL_GENERATE;
 end flexi_PCS_synch;