From: Ludwig Maier Date: Sat, 23 Nov 2013 01:28:13 +0000 (+0100) Subject: working ts, adc almost X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0803c49b3c81ad1fed24e85941fa57f4fa0de751;p=trb3.git working ts, adc almost --- diff --git a/nxyter/source/nx_control.vhd b/nxyter/source/nx_control.vhd index 59e2e2b..068bcb0 100644 --- a/nxyter/source/nx_control.vhd +++ b/nxyter/source/nx_control.vhd @@ -19,7 +19,7 @@ entity nx_control is I2C_SM_RESET_OUT : out std_logic; I2C_REG_RESET_OUT : out std_logic; NX_TS_RESET_OUT : out std_logic; - I2C_OFFLINE_IN : in std_logic; + I2C_ONLINE_IN : in std_logic; OFFLINE_OUT : out std_logic; -- Slave bus @@ -110,7 +110,7 @@ begin DEBUG_OUT(9) <= pll_adc_sclk_lock; - DEBUG_OUT(10) <= I2C_OFFLINE_IN; + DEBUG_OUT(10) <= I2C_ONLINE_IN; DEBUG_OUT(11) <= offline_force; DEBUG_OUT(12) <= offline_force_internal; DEBUG_OUT(13) <= offline_o; @@ -147,7 +147,7 @@ begin if (offline_force = '1' or offline_force_internal = '1') then offline_o <= '1'; else - offline_o <= I2C_OFFLINE_IN; + offline_o <= not I2C_ONLINE_IN; end if; -- Offline State changes @@ -384,7 +384,7 @@ begin slv_ack_o <= '1'; when x"0004" => - slv_data_out_o(0) <= I2C_OFFLINE_IN; + slv_data_out_o(0) <= I2C_ONLINE_IN; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index a51838a..01ea1e1 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -63,8 +63,10 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- -- FIFO DC Input Handler + signal nx_timestamp_fff : std_logic_vector(7 downto 0); signal nx_timestamp_ff : std_logic_vector(7 downto 0); signal nx_fifo_full : std_logic; + signal nx_fifo_delay : unsigned(3 downto 0); signal nx_fifo_reset : std_logic; -- NX_TIMESTAMP_IN Process @@ -148,7 +150,9 @@ architecture Behavioral of nx_data_receiver is signal nx_fifo_data_valid_t : std_logic; signal nx_fifo_data_valid : std_logic; - -- NX FIFO READ + -- NX FIFO READ + type delay_array_t is array(0 to 15) of std_logic_vector(31 downto 0); + signal nx_timestamp_d : delay_array_t; signal nx_timestamp_t : std_logic_vector(31 downto 0); signal nx_new_timestamp : std_logic; signal nx_new_timestamp_ctr : unsigned(3 downto 0); @@ -177,7 +181,7 @@ architecture Behavioral of nx_data_receiver is signal adc_data_t : std_logic_vector(11 downto 0); signal adc_new_data : std_logic; signal adc_new_data_ctr : unsigned(3 downto 0); - + -- ADC TEST INPUT DATA signal adc_input_error_enable : std_logic; signal adc_input_error_ctr : unsigned(15 downto 0); @@ -217,6 +221,8 @@ architecture Behavioral of nx_data_receiver is signal debug_adc : std_logic_vector(1 downto 0); signal reset_adc_handler_r : std_logic; signal reset_handler_counter_clear : std_logic; + signal adc_bit_shift : unsigned(3 downto 0); + begin PROC_DEBUG_MULT: process(debug_adc, @@ -246,7 +252,7 @@ begin case debug_adc is when "01" => DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= '0'; + DEBUG_OUT(1) <= nx_new_frame; DEBUG_OUT(2) <= TRIGGER_IN; DEBUG_OUT(3) <= adc_data_valid; DEBUG_OUT(15 downto 4) <= adc_data; @@ -280,24 +286,22 @@ begin when others => DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= '0'; --NX_TIMESTAMP_CLK_IN; - DEBUG_OUT(2) <= TRIGGER_IN; - DEBUG_OUT(3) <= nx_fifo_full; - DEBUG_OUT(4) <= nx_fifo_write_enable; + DEBUG_OUT(1) <= TRIGGER_IN; + DEBUG_OUT(2) <= nx_fifo_full; + DEBUG_OUT(3) <= nx_fifo_write_enable; + DEBUG_OUT(4) <= nx_fifo_empty; DEBUG_OUT(5) <= nx_fifo_empty; DEBUG_OUT(6) <= nx_fifo_read_enable; DEBUG_OUT(7) <= nx_fifo_data_valid; - DEBUG_OUT(8) <= adc_data_valid; - DEBUG_OUT(9) <= nx_new_timestamp; DEBUG_OUT(10) <= adc_new_data; - - DEBUG_OUT(12 downto 11) <= STATE_d; - DEBUG_OUT(13) <= new_data_o; - - DEBUG_OUT(14) <= nx_frame_synced; - DEBUG_OUT(15) <= rs_sync_reset; +-- DEBUG_OUT(12 downto 11) <= STATE_d; + DEBUG_OUT(11) <= nx_fifo_reset; + DEBUG_OUT(12) <= '0'; + DEBUG_OUT(13) <= nx_new_frame; + DEBUG_OUT(14) <= new_data_o; + DEBUG_OUT(15) <= nx_frame_synced; end case; end process PROC_DEBUG_MULT; @@ -547,18 +551,19 @@ begin -- NX_TIMESTAMP_CLK_IN Domain ----------------------------------------------------------------------------- - nx_timestamp_ff <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); - -- Merge TS Data 8bit to 32Bit Timestamp Frame PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then if( RESET_IN = '1' ) then - frame_byte_ctr <= (others => '0'); - nx_frame_word <= (others => '0'); - nx_new_frame <= '0'; + frame_byte_ctr <= (others => '0'); + nx_frame_word <= (others => '0'); + nx_timestamp_ff <= (others => '0'); + nx_new_frame <= '0'; else - nx_new_frame <= '0'; + nx_timestamp_fff <= NX_TIMESTAMP_IN; + nx_timestamp_ff <= nx_timestamp_fff; + nx_new_frame <= '0'; case frame_byte_pos is when "11" => nx_frame_word(31 downto 24) <= nx_timestamp_ff; @@ -691,7 +696,7 @@ begin Empty => nx_fifo_empty, Full => nx_fifo_full ); - + nx_fifo_reset <= RESET_IN or data_handler_reset or fifo_reset_r; PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN) @@ -789,12 +794,12 @@ begin begin if (rising_edge(CLK_IN) ) then if( RESET_IN = '1' or fifo_reset_r = '1') then - nx_fifo_data_valid_t <= '0'; - nx_fifo_data_valid <= '0'; + nx_fifo_data_valid_t <= '0'; + nx_fifo_data_valid <= '0'; else -- Delay read signal by one CLK - nx_fifo_data_valid_t <= nx_fifo_read_enable; - nx_fifo_data_valid <= nx_fifo_data_valid_t; + nx_fifo_data_valid_t <= nx_fifo_read_enable; + nx_fifo_data_valid <= nx_fifo_data_valid_t; end if; end if; end process PROC_NX_FIFO_READ_ENABLE; @@ -806,9 +811,18 @@ begin nx_timestamp_t <= (others => '0'); nx_new_timestamp <= '0'; nx_new_timestamp_ctr <= (others => '0'); + for I in 1 to 15 loop + nx_timestamp_d(I) <= (others => '0'); + end loop; else if (nx_fifo_data_valid = '1') then - nx_timestamp_t <= nx_fifo_data; + -- Delay Data relative to ADC by 8 steps + for I in 1 to 15 loop + nx_timestamp_d(I) <= nx_timestamp_d(I - 1); + end loop; + nx_timestamp_d(0) <= nx_fifo_data; + + nx_timestamp_t <= nx_timestamp_d(to_integer(nx_fifo_delay)); nx_new_timestamp <= '1'; nx_new_timestamp_ctr <= nx_new_timestamp_ctr + 1; else @@ -819,6 +833,22 @@ begin end if; end process PROC_NX_FIFO_READ; + PROC_NX_FIFO_DELAY: process(CLK_IN) + begin + if (rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or fifo_reset_r = '1') then + + else + if (nx_fifo_data_valid = '1') then + + else + + end if; + end if; + end if; + end process PROC_NX_FIFO_DELAY; + + ----------------------------------------------------------------------------- -- Status Counters ----------------------------------------------------------------------------- @@ -886,11 +916,11 @@ begin end if; end process PROC_PARITY_ERROR_COUNTER; - ----------------------------------------------------------------------------- -- ADC Fifo Handler ----------------------------------------------------------------------------- PROC_ADC_DATA_READ: process(CLK_IN) + variable adcval : unsigned(11 downto 0) := (others => '0'); begin if (rising_edge(CLK_IN) ) then if (RESET_IN = '1' or fifo_reset_r = '1') then @@ -898,8 +928,15 @@ begin adc_new_data <= '0'; adc_new_data_ctr <= (others => '0'); else + if (adc_bit_shift(3) = '1') then + adcval := unsigned(adc_data) rol + to_integer(adc_bit_shift(2 downto 0)); + else + adcval := unsigned(adc_data) ror + to_integer(adc_bit_shift(2 downto 0)); + end if; if (adc_data_valid = '1') then - adc_data_t <= adc_data; + adc_data_t <= std_logic_vector(adcval); adc_new_data <= '1'; adc_new_data_ctr <= adc_new_data_ctr + 1; else @@ -1012,12 +1049,14 @@ begin fifo_reset_r <= '0'; debug_adc <= (others => '0'); adc_input_error_enable <= '0'; - johnson_counter_sync <= "00"; + johnson_counter_sync <= "01"; pll_adc_sample_clk_dphase <= (others => '0'); pll_adc_sample_clk_finedelb <= (others => '0'); pll_adc_not_lock_ctr_clear <= '0'; + nx_fifo_delay <= x"7"; reset_adc_handler_r <= '0'; reset_handler_counter_clear <= '0'; + adc_bit_shift <= x"0"; else slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -1097,7 +1136,7 @@ begin slv_ack_o <= '1'; when x"000b" => - slv_data_out_o(0) <= nx_data_clock_ok; + slv_data_out_o(0) <= adc_clk_ok; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; @@ -1105,12 +1144,22 @@ begin slv_data_out_o(15 downto 0) <= reset_handler_counter; slv_data_out_o(31 downto 6) <= (others => '0'); slv_ack_o <= '1'; - + + when x"000d" => + slv_data_out_o(3 downto 0) <= std_logic_vector(nx_fifo_delay); + slv_data_out_o(31 downto 4) <= (others => '0'); + slv_ack_o <= '1'; + + when x"000e" => + slv_data_out_o(3 downto 0) <= std_logic_vector(adc_bit_shift); + slv_data_out_o(31 downto 4) <= (others => '0'); + slv_ack_o <= '1'; + when x"000f" => slv_data_out_o(1 downto 0) <= debug_adc; slv_data_out_o(31 downto 2) <= (others => '0'); slv_ack_o <= '1'; - + when others => slv_unknown_addr_o <= '1'; end case; @@ -1148,18 +1197,28 @@ begin adc_input_error_enable <= SLV_DATA_IN(0); slv_ack_o <= '1'; + when x"000b" => + reset_adc_handler_r <= '1'; + slv_ack_o <= '1'; + when x"000c" => reset_handler_counter_clear <= '1'; slv_ack_o <= '1'; - + + when x"000d" => + nx_fifo_delay <= + unsigned(SLV_DATA_IN(3 downto 0)); + slv_ack_o <= '1'; + when x"000e" => - reset_adc_handler_r <= '1'; + adc_bit_shift <= + unsigned(SLV_DATA_IN(3 downto 0)); slv_ack_o <= '1'; when x"000f" => debug_adc <= SLV_DATA_IN(1 downto 0); slv_ack_o <= '1'; - + when others => slv_unknown_addr_o <= '1'; diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd index ab797b0..1f4f6e9 100644 --- a/nxyter/source/nx_trigger_handler.vhd +++ b/nxyter/source/nx_trigger_handler.vhd @@ -38,7 +38,7 @@ entity nx_trigger_handler is LVL2_TRIGGER_BUSY_IN : in std_logic; -- OUT - VALIDATE_TRIGGER_OUT : out std_logic; + VALID_TRIGGER_OUT : out std_logic; TIMESTAMP_TRIGGER_OUT : out std_logic; LVL2_TRIGGER_OUT : out std_logic; FAST_CLEAR_OUT : out std_logic; @@ -94,7 +94,7 @@ architecture Behavioral of nx_trigger_handler is -- Trigger Handler - signal validate_trigger_o : std_logic; + signal valid_trigger_o : std_logic; signal lvl2_trigger_o : std_logic; signal fast_clear_o : std_logic; signal trigger_busy_o : std_logic; @@ -102,7 +102,6 @@ architecture Behavioral of nx_trigger_handler is signal fee_trg_statusbits_o : std_logic_vector(31 downto 0); signal send_testpulse_l : std_logic; signal send_testpulse : std_logic; - signal event_buffer_clear_o : std_logic; type STATES is (S_IDLE, S_CTS_TRIGGER, @@ -155,7 +154,7 @@ begin DEBUG_OUT(5) <= INTERNAL_TRIGGER_IN; DEBUG_OUT(6) <= TRIGGER_VALIDATE_BUSY_IN; DEBUG_OUT(7) <= LVL2_TRIGGER_BUSY_IN; - DEBUG_OUT(8) <= validate_trigger_o; + DEBUG_OUT(8) <= valid_trigger_o; DEBUG_OUT(9) <= lvl2_trigger_o; DEBUG_OUT(10) <= '0'; DEBUG_OUT(11) <= fee_trg_release_o; @@ -333,22 +332,20 @@ begin begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1') then - validate_trigger_o <= '0'; + valid_trigger_o <= '0'; lvl2_trigger_o <= '0'; fee_trg_release_o <= '0'; fee_trg_statusbits_o <= (others => '0'); fast_clear_o <= '0'; - event_buffer_clear_o <= '0'; trigger_busy_o <= '0'; send_testpulse_l <= '0'; STATE <= S_IDLE; else - validate_trigger_o <= '0'; + valid_trigger_o <= '0'; lvl2_trigger_o <= '0'; fee_trg_release_o <= '0'; fee_trg_statusbits_o <= (others => '0'); fast_clear_o <= '0'; - event_buffer_clear_o <= '0'; trigger_busy_o <= '1'; send_testpulse_l <= '0'; @@ -361,31 +358,33 @@ begin case STATE is when S_IDLE => if (LVL1_VALID_NOTIMING_TRG_IN = '1') then + -- Calibration Trigger .. ignore STATE <= S_WAIT_TRG_DATA_VALID; elsif (LVL1_VALID_TIMING_TRG_IN = '1') then - if (NXYTER_OFFLINE_IN = '1') then - STATE <= S_WAIT_TRG_DATA_VALID; - else + if (NXYTER_OFFLINE_IN = '0') then + -- Normal Trigger STATE <= S_CTS_TRIGGER; + else + -- Ignore Trigger for nxyter is offline + STATE <= S_WAIT_TRG_DATA_VALID; end if; elsif (INTERNAL_TRIGGER_IN = '1') then + -- Internal Trigger, not defined yet STATE <= S_INTERNAL_TRIGGER; else trigger_busy_o <= '0'; STATE <= S_IDLE; end if; - - + when S_CTS_TRIGGER => - -- Do nothing, Just send Trigger ACK in reply - validate_trigger_o <= '1'; + valid_trigger_o <= '1'; lvl2_trigger_o <= '1'; if (reg_testpulse_enable = '1') then send_testpulse_l <= '1'; end if; STATE <= S_WAIT_TRG_DATA_VALID; - + when S_WAIT_TRG_DATA_VALID => if (LVL1_TRG_DATA_VALID_IN = '0') then STATE <= S_WAIT_TRG_DATA_VALID; @@ -413,7 +412,7 @@ begin -- Internal Trigger Handler when S_INTERNAL_TRIGGER => - validate_trigger_o <= '1'; + valid_trigger_o <= '1'; STATE <= S_WAIT_TRIGGER_VALIDATE_ACK; when S_WAIT_TRIGGER_VALIDATE_ACK => @@ -608,7 +607,7 @@ begin timestamp_trigger_o <= timestamp_trigger; -- Trigger Output - VALIDATE_TRIGGER_OUT <= validate_trigger_o; + VALID_TRIGGER_OUT <= valid_trigger_o; TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o; LVL2_TRIGGER_OUT <= lvl2_trigger_o; FAST_CLEAR_OUT <= fast_clear_o; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 509a175..41bfb51 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -247,7 +247,7 @@ component nx_control I2C_SM_RESET_OUT : out std_logic; I2C_REG_RESET_OUT : out std_logic; NX_TS_RESET_OUT : out std_logic; - I2C_OFFLINE_IN : in std_logic; + I2C_ONLINE_IN : in std_logic; OFFLINE_OUT : out std_logic; SLV_READ_IN : in std_logic; @@ -687,7 +687,7 @@ component nx_trigger_handler INTERNAL_TRIGGER_IN : in std_logic; TRIGGER_VALIDATE_BUSY_IN : in std_logic; LVL2_TRIGGER_BUSY_IN : in std_logic; - VALIDATE_TRIGGER_OUT : out std_logic; + VALID_TRIGGER_OUT : out std_logic; TIMESTAMP_TRIGGER_OUT : out std_logic; LVL2_TRIGGER_OUT : out std_logic; FAST_CLEAR_OUT : out std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index c9a44b3..185b23b 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -297,11 +297,11 @@ begin PLL_NX_CLK_LOCK_IN => PLL_NX_CLK_LOCK_IN, PLL_ADC_DCLK_LOCK_IN => PLL_ADC_DCLK_LOCK_IN, PLL_ADC_SCLK_LOCK_IN => pll_sadc_clk_lock, - + I2C_SM_RESET_OUT => i2c_sm_reset_o, I2C_REG_RESET_OUT => i2c_reg_reset_o, NX_TS_RESET_OUT => nx_ts_reset_1, - I2C_OFFLINE_IN => nxyter_online_i2c, + I2C_ONLINE_IN => nxyter_online_i2c, OFFLINE_OUT => nxyter_offline, SLV_READ_IN => slv_read(0), @@ -456,7 +456,7 @@ begin TRIGGER_VALIDATE_BUSY_IN => trigger_validate_busy, LVL2_TRIGGER_BUSY_IN => trigger_evt_busy, - VALIDATE_TRIGGER_OUT => trigger, + VALID_TRIGGER_OUT => trigger, TIMESTAMP_TRIGGER_OUT => timestamp_trigger, LVL2_TRIGGER_OUT => lvl2_trigger, FAST_CLEAR_OUT => fast_clear, @@ -524,6 +524,7 @@ begin ADC_B_IN => ADC_B_IN, ADC_NX_IN => ADC_NX_IN, ADC_D_IN => ADC_D_IN, + ADC_SCLK_LOCK_OUT => pll_sadc_clk_lock, NX_TIMESTAMP_OUT => new_timestamp, ADC_DATA_OUT => new_adc_data, @@ -539,6 +540,7 @@ begin SLV_ACK_OUT => slv_ack(2), SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), + DEBUG_OUT => debug_line(7) ); diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index 980f559..b2ee8b6 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -65,10 +65,13 @@ 0x8509 : r/w Enable Test ADC Input Data Error Test 0x850a : r ADC Input Data Error Counter (16 Bit) (only valid in case of 0x8509 is 1, see line above) -0x850b : r Nxyter Data Clock Status (1 = O.K.) +0x850b : r/w r: Nxyter Data Clock Status (1 = O.K.) + w: reset ADC Handler 0x850c : r/w r: Reset Handler Counter (16 Bit) w: Clear Counter -0x850e : w Reset ADC Handler +0x850d : r/w Nxyter Timestamp vs ADC FIFO Delay (4 Bit) +0x850e : r/w ADC Bit Shift (Bit3: Direction 0=ror, 1=rol) + (Bit2..0: Value) 0x850f : r/w Debug Multiplexer: 0: no ADC Values, normal Debug 1: ADC Value Nxyter