From: hadaq Date: Wed, 27 Mar 2013 22:24:40 +0000 (+0000) Subject: update X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=08102dc03c18d2a39aa6f58af4d066d5a5659aae;p=trb3.git update --- diff --git a/nxyter/source/nx_data_buffer.vhd b/nxyter/source/nx_data_buffer.vhd index 18f3899..e2ac0a2 100644 --- a/nxyter/source/nx_data_buffer.vhd +++ b/nxyter/source/nx_data_buffer.vhd @@ -46,19 +46,13 @@ architecture Behavioral of nx_data_buffer is signal fifo_read_done : std_logic; signal fifo_data : std_logic_vector(31 downto 0); - signal fifo_read_enable_x : std_logic; - signal fifo_read_busy_x : std_logic; - signal fifo_no_data_x : std_logic; - signal fifo_read_done_x : std_logic; - signal fifo_data_x : std_logic_vector(31 downto 0); - type STATES is (S_IDLE, S_NOP1, S_NOP2, S_READ_WORD ); - signal STATE, NEXT_STATE: STATES; + signal STATE : STATES; -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); @@ -125,69 +119,56 @@ begin -- FIFO Output Handler ----------------------------------------------------------------------------- - PROC_FIFO_READ_TRANSFER: process(CLK_IN) + PROC_FIFO_READ_WORD: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - fifo_read_enable <= '0'; - fifo_read_busy <= '0'; - fifo_data <= (others => '0'); - fifo_read_done <= '0'; - fifo_no_data <= '1'; - STATE <= S_IDLE; - else - fifo_read_enable <= fifo_read_enable_x; - fifo_read_busy <= fifo_read_busy_x; - fifo_data <= fifo_data_x; - fifo_read_done <= fifo_read_done_x; - fifo_no_data <= fifo_no_data_x; - STATE <= NEXT_STATE; - end if; - end if; - end process PROC_FIFO_READ_TRANSFER; - - PROC_FIFO_READ_WORD: process(STATE, - fifo_read_start, - fifo_empty - ) - begin - fifo_read_busy_x <= '0'; - fifo_no_data_x <= '0'; - fifo_read_done_x <= '0'; - fifo_data_x <= (others => '0'); - fifo_read_enable_x <= '0'; - - case STATE is - when S_IDLE => - if (fifo_read_start = '1') then - if (fifo_empty = '0') then - fifo_read_enable_x <= '1'; - fifo_read_busy_x <= '1'; - NEXT_STATE <= S_NOP1; - else - fifo_no_data_x <= '1'; - fifo_read_done_x <= '1'; - NEXT_STATE <= S_IDLE; - end if; - else - NEXT_STATE <= S_IDLE; - end if; + fifo_read_enable <= '0'; + fifo_read_busy <= '0'; + fifo_data <= (others => '0'); + fifo_read_done <= '0'; + fifo_no_data <= '1'; + STATE <= S_IDLE; + else + fifo_read_busy <= '0'; + fifo_no_data <= '0'; + fifo_read_done <= '0'; + fifo_data <= (others => '0'); + fifo_read_enable <= '0'; + + case STATE is + when S_IDLE => + if (fifo_read_start = '1') then + if (fifo_empty = '0') then + fifo_read_enable <= '1'; + fifo_read_busy <= '1'; + STATE <= S_NOP1; + else + fifo_no_data <= '1'; + fifo_read_done <= '1'; + STATE <= S_IDLE; + end if; + else + STATE <= S_IDLE; + end if; - when S_NOP1 => - fifo_read_busy_x <= '1'; - NEXT_STATE <= S_NOP2; + when S_NOP1 => + fifo_read_busy <= '1'; + STATE <= S_NOP2; - when S_NOP2 => - fifo_read_busy_x <= '1'; - NEXT_STATE <= S_READ_WORD; - - when S_READ_WORD => - fifo_read_busy_x <= '0'; - fifo_data_x <= fifo_o; - fifo_read_done_x <= '1'; - NEXT_STATE <= S_IDLE; - - end case; + when S_NOP2 => + fifo_read_busy <= '1'; + STATE <= S_READ_WORD; + + when S_READ_WORD => + fifo_read_busy <= '0'; + fifo_data <= fifo_o; + fifo_read_done <= '1'; + STATE <= S_IDLE; + + end case; + end if; + end if; end process PROC_FIFO_READ_WORD; diff --git a/nxyter/source/nx_timer.vhd b/nxyter/source/nx_timer.vhd index b21963f..520818b 100644 --- a/nxyter/source/nx_timer.vhd +++ b/nxyter/source/nx_timer.vhd @@ -21,66 +21,52 @@ architecture Behavioral of nx_timer is signal timer_ctr : unsigned(CTR_WIDTH - 1 downto 0); signal timer_done_o : std_logic; - signal timer_ctr_x : unsigned(CTR_WIDTH - 1 downto 0); - signal timer_done_o_x : std_logic; - type STATES is (S_IDLE, S_COUNT, S_DONE ); - signal STATE, NEXT_STATE : STATES; + signal STATE : STATES; begin - - PROC_TIMER_TRANSFER: process(CLK_IN) - begin + + PROC_TIMER: process(CLK_IN) + begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then timer_ctr <= (others => '0'); timer_done_o <= '0'; STATE <= S_IDLE; else - timer_ctr <= timer_ctr_x; - timer_done_o <= timer_done_o_x; - STATE <= NEXT_STATE; - end if; - end if; - end process PROC_TIMER_TRANSFER; - - PROC_TIMER: process(STATE, - TIMER_START_IN, - timer_ctr - ) - begin - - timer_done_o_x <= '0'; - - if (TIMER_START_IN > 0) then - timer_ctr_x <= TIMER_START_IN; - NEXT_STATE <= S_COUNT; - else - case STATE is - when S_IDLE => - if (TIMER_START_IN = 0) then - NEXT_STATE <= S_IDLE; - else - timer_ctr_x <= TIMER_START_IN; - NEXT_STATE <= S_COUNT; - end if; + timer_done_o <= '0'; + + if (TIMER_START_IN > 0) then + timer_ctr <= TIMER_START_IN; + STATE <= S_COUNT; + else + case STATE is + when S_IDLE => + if (TIMER_START_IN = 0) then + STATE <= S_IDLE; + else + timer_ctr <= TIMER_START_IN; + STATE <= S_COUNT; + end if; - when S_COUNT => - if (timer_ctr > 0) then - timer_ctr_x <= timer_ctr - 1; - NEXT_STATE <= S_COUNT; - else - NEXT_STATE <= S_DONE; - end if; + when S_COUNT => + if (timer_ctr > 0) then + timer_ctr <= timer_ctr - 1; + STATE <= S_COUNT; + else + STATE <= S_DONE; + end if; - when S_DONE => - timer_done_o_x <= '1'; - NEXT_STATE <= S_IDLE; + when S_DONE => + timer_done_o <= '1'; + STATE <= S_IDLE; - end case; + end case; + end if; + end if; end if; end process PROC_TIMER; diff --git a/nxyter/source/nx_timestamp_fifo_read.vhd b/nxyter/source/nx_timestamp_fifo_read.vhd index 7518c95..fad71c7 100644 --- a/nxyter/source/nx_timestamp_fifo_read.vhd +++ b/nxyter/source/nx_timestamp_fifo_read.vhd @@ -77,7 +77,7 @@ architecture Behavioral of nx_timestamp_fifo_read is S_SYNC_WAIT ); - signal STATE_SYNC, NEXT_STATE_SYNC: STATES_SYNC; + signal STATE_SYNC : STATES_SYNC; signal rs_sync_set : std_logic; signal rs_sync_reset : std_logic; @@ -86,12 +86,6 @@ architecture Behavioral of nx_timestamp_fifo_read is signal nx_frame_resync_ctr : unsigned(7 downto 0); signal frame_sync_wait_done : std_logic; - signal rs_sync_set_x : std_logic; - signal rs_sync_reset_x : std_logic; - signal frame_clock_ctr_inc_s_x : std_logic; - signal frame_sync_wait_ctr_x : unsigned(7 downto 0); - signal nx_frame_resync_ctr_x : unsigned(7 downto 0); - -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); signal slv_no_more_data_o : std_logic; @@ -331,7 +325,10 @@ begin ); -- Frame Sync process - PROC_SYNC_TO_NX_FRAME_TRANSFER: process(CLK_IN) + PROC_SYNC_TO_NX_FRAME: process(CLK_IN) + + variable fifo_tag_given : std_logic_vector(3 downto 0); + begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then @@ -342,87 +339,64 @@ begin frame_sync_wait_ctr <= (others => '0'); STATE_SYNC <= S_SYNC_CHECK; else - rs_sync_set <= rs_sync_set_x; - rs_sync_reset <= rs_sync_reset_x; - frame_clock_ctr_inc_s <= frame_clock_ctr_inc_s_x; - nx_frame_resync_ctr <= nx_frame_resync_ctr_x; - frame_sync_wait_ctr <= frame_sync_wait_ctr_x; - STATE_SYNC <= NEXT_STATE_SYNC; - end if; - end if; - end process PROC_SYNC_TO_NX_FRAME_TRANSFER; - - PROC_SYNC_TO_NX_FRAME: process(STATE_SYNC, - fifo_out(35), - fifo_out(26), - fifo_out(17), - fifo_out(8), - fifo_new_frame, - register_fifo_data, - frame_sync_wait_done, - reset_ctr - ) - - variable fifo_tag_given : std_logic_vector(3 downto 0); - - begin - rs_sync_set_x <= '0'; - rs_sync_reset_x <= '0'; - frame_clock_ctr_inc_s_x <= '0'; - nx_frame_resync_ctr_x <= nx_frame_resync_ctr; - frame_sync_wait_ctr_x <= (others => '0'); - - fifo_tag_given := fifo_out(35) & fifo_out(26) & - fifo_out(17) & fifo_out(8); - - case STATE_SYNC is - when S_SYNC_CHECK => - if (fifo_new_frame = '1') then - case register_fifo_data is - when x"7f7f7f06" => - rs_sync_set_x <= '1'; - NEXT_STATE_SYNC <= S_SYNC_CHECK; - - when x"067f7f7f" => - NEXT_STATE_SYNC <= S_SYNC_RESYNC; - - when x"7f067f7f" => - NEXT_STATE_SYNC <= S_SYNC_RESYNC; - - when x"7f7f067f" => - NEXT_STATE_SYNC <= S_SYNC_RESYNC; - - when others => - NEXT_STATE_SYNC <= S_SYNC_CHECK; - - end case; - else - NEXT_STATE_SYNC <= S_SYNC_CHECK; - end if; - - when S_SYNC_RESYNC => - rs_sync_reset_x <= '1'; - frame_clock_ctr_inc_s_x <= '1'; - if (reset_ctr = '0') then - nx_frame_resync_ctr_x <= nx_frame_resync_ctr + 1; - end if; - - frame_sync_wait_ctr_x <= x"14"; - NEXT_STATE_SYNC <= S_SYNC_WAIT; + rs_sync_set <= '0'; + rs_sync_reset <= '0'; + frame_clock_ctr_inc_s <= '0'; + nx_frame_resync_ctr <= nx_frame_resync_ctr; + frame_sync_wait_ctr <= (others => '0'); - when S_SYNC_WAIT => - if (frame_sync_wait_done = '0') then - NEXT_STATE_SYNC <= S_SYNC_WAIT; - else - NEXT_STATE_SYNC <= S_SYNC_CHECK; - end if; + fifo_tag_given := fifo_out(35) & fifo_out(26) & + fifo_out(17) & fifo_out(8); + + case STATE_SYNC is + when S_SYNC_CHECK => + if (fifo_new_frame = '1') then + case register_fifo_data is + when x"7f7f7f06" => + rs_sync_set <= '1'; + STATE_SYNC <= S_SYNC_CHECK; + + when x"067f7f7f" => + STATE_SYNC <= S_SYNC_RESYNC; + + when x"7f067f7f" => + STATE_SYNC <= S_SYNC_RESYNC; + + when x"7f7f067f" => + STATE_SYNC <= S_SYNC_RESYNC; + + when others => + STATE_SYNC <= S_SYNC_CHECK; + + end case; + else + STATE_SYNC <= S_SYNC_CHECK; + end if; + + when S_SYNC_RESYNC => + rs_sync_reset <= '1'; + frame_clock_ctr_inc_s <= '1'; + if (reset_ctr = '0') then + nx_frame_resync_ctr <= nx_frame_resync_ctr + 1; + end if; + + frame_sync_wait_ctr <= x"14"; + STATE_SYNC <= S_SYNC_WAIT; + + when S_SYNC_WAIT => + if (frame_sync_wait_done = '0') then + STATE_SYNC <= S_SYNC_WAIT; + else + STATE_SYNC <= S_SYNC_CHECK; + end if; - end case; - - if (reset_ctr = '1') then - nx_frame_resync_ctr_x <= (others => '0'); + end case; + + if (reset_ctr = '1') then + nx_frame_resync_ctr <= (others => '0'); + end if; + end if; end if; - end process PROC_SYNC_TO_NX_FRAME; ----------------------------------------------------------------------------- diff --git a/nxyter/source/nx_timestamp_process.vhd b/nxyter/source/nx_timestamp_process.vhd index b87c531..c4c0b89 100644 --- a/nxyter/source/nx_timestamp_process.vhd +++ b/nxyter/source/nx_timestamp_process.vhd @@ -71,17 +71,11 @@ architecture Behavioral of nx_timestamp_process is -- Process Trigger Handler signal store_to_fifo : std_logic; - signal store_to_fifo_x : std_logic; signal data_fifo_reset_o : std_logic; - signal data_fifo_reset_o_x : std_logic; signal process_busy_o : std_logic; - signal process_busy_o_x : std_logic; signal wait_timer_init : unsigned(11 downto 0); - signal wait_timer_init_x : unsigned(11 downto 0); signal token_return_ctr : unsigned(3 downto 0); - signal token_return_ctr_x : unsigned(3 downto 0); signal ch_status_cmd_tr : CS_CMDS; - signal ch_status_cmd_tr_x : CS_CMDS; type STATES is (S_IDLE, S_TRIGGER, @@ -90,15 +84,11 @@ architecture Behavioral of nx_timestamp_process is S_WAIT_PROCESS_END, S_WRITE_TRAILER ); - signal STATE, NEXT_STATE : STATES; + signal STATE : STATES; signal t_data_o : std_logic_vector(31 downto 0); - signal t_data_o_x : std_logic_vector(31 downto 0); signal t_data_clk_o : std_logic; - signal t_data_clk_o_x : std_logic; - signal busy_time_ctr : unsigned(11 downto 0); - signal busy_time_ctr_x : unsigned(11 downto 0); -- Timer signal wait_timer_done : std_logic; @@ -269,9 +259,8 @@ begin -- Trigger Handler ----------------------------------------------------------------------------- - PROC_TRIGGER_HANDLER_TRANSFER: process(CLK_IN) - begin - + PROC_TRIGGER_HANDLER: process(CLK_IN) + begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1') then store_to_fifo <= '0'; @@ -285,91 +274,77 @@ begin ch_status_cmd_tr <= CS_RESET; STATE <= S_IDLE; else - store_to_fifo <= store_to_fifo_x; - data_fifo_reset_o <= data_fifo_reset_o_x; - process_busy_o <= process_busy_o_x; - wait_timer_init <= wait_timer_init_x; - t_data_o <= t_data_o_x; - t_data_clk_o <= t_data_clk_o_x; - busy_time_ctr <= busy_time_ctr_x; - token_return_ctr <= token_return_ctr_x; - ch_status_cmd_tr <= ch_status_cmd_tr_x; - STATE <= NEXT_STATE; - end if; - end if; - end process PROC_TRIGGER_HANDLER_TRANSFER; + store_to_fifo <= '0'; + data_fifo_reset_o <= '0'; + wait_timer_init <= (others => '0'); + process_busy_o <= '1'; + t_data_o <= (others => '0'); + t_data_clk_o <= '0'; + token_return_ctr <= token_return_ctr; + ch_status_cmd_tr <= CS_NONE; + case STATE is + + when S_IDLE => + if (TRIGGER_IN = '1') then + busy_time_ctr <= (others => '0'); + STATE <= S_TRIGGER; + else + process_busy_o <= '0'; + STATE <= S_IDLE; + end if; + + when S_TRIGGER => + ch_status_cmd_tr <= CS_RESET; + data_fifo_reset_o <= '1'; + wait_timer_init <= x"020"; -- wait 320ns for first event + STATE <= S_WAIT_DATA; + + when S_WAIT_DATA => + if (wait_timer_done = '0') then + STATE <= S_WAIT_DATA; + else + STATE <= S_PROCESS_START; + end if; + + when S_PROCESS_START => + token_return_ctr <= (others => '0'); + wait_timer_init <= readout_time_max; + store_to_fifo <= '1'; + STATE <= S_WAIT_PROCESS_END; + + when S_WAIT_PROCESS_END => + if (wait_timer_done = '1' or + channel_all_done = '1' or + NX_NOMORE_DATA_IN = '1') then + STATE <= S_WRITE_TRAILER; + else + store_to_fifo <= '1'; + STATE <= S_WAIT_PROCESS_END; + + -- Check Token_Return + if (readout_mode = x"0" and NX_TOKEN_RETURN_IN = '1') then + if (token_return_ctr > 0) then + ch_status_cmd_tr <= CS_TOKEN_UPDATE; + end if; + token_return_ctr <= token_return_ctr + 1; + end if; + end if; - PROC_TRIGGER_HANDLER: process(TRIGGER_IN) - begin - store_to_fifo_x <= '0'; - data_fifo_reset_o_x <= '0'; - wait_timer_init_x <= (others => '0'); - process_busy_o_x <= '1'; - t_data_o_x <= (others => '0'); - t_data_clk_o_x <= '0'; - token_return_ctr_x <= token_return_ctr; - ch_status_cmd_tr_x <= CS_NONE; - case STATE is - - when S_IDLE => - if (TRIGGER_IN = '1') then - busy_time_ctr_x <= (others => '0'); - NEXT_STATE <= S_TRIGGER; - else - process_busy_o_x <= '0'; - NEXT_STATE <= S_IDLE; - end if; - - when S_TRIGGER => - ch_status_cmd_tr_x <= CS_RESET; - data_fifo_reset_o_x <= '1'; - wait_timer_init_x <= x"020"; -- wait 320ns for first event - NEXT_STATE <= S_WAIT_DATA; - - when S_WAIT_DATA => - if (wait_timer_done = '0') then - NEXT_STATE <= S_WAIT_DATA; - else - NEXT_STATE <= S_PROCESS_START; - end if; - - when S_PROCESS_START => - token_return_ctr_x <= (others => '0'); - wait_timer_init_x <= readout_time_max; - store_to_fifo_x <= '1'; - NEXT_STATE <= S_WAIT_PROCESS_END; - - when S_WAIT_PROCESS_END => - if (wait_timer_done = '1' or - channel_all_done = '1' or - NX_NOMORE_DATA_IN = '1') then - NEXT_STATE <= S_WRITE_TRAILER; - else - store_to_fifo_x <= '1'; - NEXT_STATE <= S_WAIT_PROCESS_END; - - -- Check Token_Return - if (readout_mode = x"0" and NX_TOKEN_RETURN_IN = '1') then - if (token_return_ctr > 0) then - ch_status_cmd_tr_x <= CS_TOKEN_UPDATE; - end if; - token_return_ctr_x <= token_return_ctr + 1; - end if; - end if; - - when S_WRITE_TRAILER => - t_data_o_x <= x"deadaffe"; - t_data_clk_o_x <= '1'; - ch_status_cmd_tr_x <= CS_RESET; - NEXT_STATE <= S_IDLE; - - end case; - - if (STATE /= S_IDLE) then - busy_time_ctr_x <= busy_time_ctr + 1; - end if; - + when S_WRITE_TRAILER => + t_data_o <= x"deadaffe"; + t_data_clk_o <= '1'; + ch_status_cmd_tr <= CS_RESET; + STATE <= S_IDLE; + + end case; + + if (STATE /= S_IDLE) then + busy_time_ctr <= busy_time_ctr + 1; + end if; + + end if; + end if; end process PROC_TRIGGER_HANDLER; ----------------------------------------------------------------------------- diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd index 3ba2ca9..70f4179 100644 --- a/nxyter/source/nx_trigger_generator.vhd +++ b/nxyter/source/nx_trigger_generator.vhd @@ -33,15 +33,10 @@ architecture Behavioral of nx_trigger_generator is signal start_cycle : std_logic; signal trigger_cycle_ctr : unsigned(7 downto 0); - signal trigger_cycle_ctr_x : unsigned(7 downto 0); signal wait_timer_init : unsigned(15 downto 0); - signal wait_timer_init_x : unsigned(15 downto 0); signal wait_timer_done : std_logic; signal trigger_o : std_logic; - signal trigger_o_x : std_logic; signal ts_reset_o : std_logic; - signal ts_reset_o_x : std_logic; - signal testpulse_o_x : std_logic; signal testpulse_o : std_logic; type STATES is (S_IDLE, @@ -49,7 +44,7 @@ architecture Behavioral of nx_trigger_generator is S_SET_TESTPULSE, S_WAIT_TRIGGER_END ); - signal STATE, NEXT_STATE : STATES; + signal STATE : STATES; -- TRBNet Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); @@ -88,9 +83,9 @@ begin ----------------------------------------------------------------------------- -- Gernerate Trigger ----------------------------------------------------------------------------- - - PROC_TRIGGER_OUT_TRANSFER: process (CLK_IN) - begin + + PROC_TRIGGER_OUT: process(CLK_IN) + begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1') then trigger_o <= '0'; @@ -100,78 +95,61 @@ begin trigger_cycle_ctr <= (others => '0'); STATE <= S_IDLE; else - trigger_o <= trigger_o_x; - testpulse_o <= testpulse_o_x; - ts_reset_o <= ts_reset_o_x; - wait_timer_init <= wait_timer_init_x; - trigger_cycle_ctr <= trigger_cycle_ctr_x; - STATE <= NEXT_STATE; + trigger_o <= '0'; + testpulse_o <= '0'; + ts_reset_o <= '0'; + wait_timer_init <= (others => '0'); + trigger_cycle_ctr <= trigger_cycle_ctr; + + case STATE is + when S_IDLE => + if (start_cycle = '1') then + trigger_cycle_ctr <= reg_trigger_num_cycles; + if (reg_reset_on = '1') then + ts_reset_o <= '1'; + wait_timer_init <= reg_trigger_period; + STATE <= S_WAIT_TRIGGER_END; + else + STATE <= S_NEXT_CYCLE; + end if; + else + STATE <= S_IDLE; + end if; + + when S_NEXT_CYCLE => + if (trigger_cycle_ctr > 0) then + trigger_o <= '1'; + trigger_cycle_ctr <= trigger_cycle_ctr - 1; + if (reg_testpulse_length > 0) then + wait_timer_init <= reg_testpulse_length; + STATE <= S_SET_TESTPULSE; + else + wait_timer_init <= reg_trigger_period; + STATE <= S_WAIT_TRIGGER_END; + end if; + else + STATE <= S_IDLE; + end if; + + when S_SET_TESTPULSE => + testpulse_o <= '1'; + if (wait_timer_done = '0') then + STATE <= S_SET_TESTPULSE; + else + wait_timer_init <= reg_trigger_period - reg_testpulse_length; + STATE <= S_WAIT_TRIGGER_END; + end if; + + when S_WAIT_TRIGGER_END => + if (wait_timer_done = '0') then + STATE <= S_WAIT_TRIGGER_END; + else + STATE <= S_NEXT_CYCLE; + end if; + + end case; end if; end if; - end process PROC_TRIGGER_OUT_TRANSFER; - - PROC_TRIGGER_OUT: process(STATE, - start_cycle, - reg_trigger_num_cycles, - reg_trigger_period, - reg_reset_on, - reg_testpulse_length, - wait_timer_done - ) - begin - trigger_o_x <= '0'; - testpulse_o_x <= '0'; - ts_reset_o_x <= '0'; - wait_timer_init_x <= (others => '0'); - trigger_cycle_ctr_x <= trigger_cycle_ctr; - - case STATE is - when S_IDLE => - if (start_cycle = '1') then - trigger_cycle_ctr_x <= reg_trigger_num_cycles; - if (reg_reset_on = '1') then - ts_reset_o_x <= '1'; - wait_timer_init_x <= reg_trigger_period; - NEXT_STATE <= S_WAIT_TRIGGER_END; - else - NEXT_STATE <= S_NEXT_CYCLE; - end if; - else - NEXT_STATE <= S_IDLE; - end if; - - when S_NEXT_CYCLE => - if (trigger_cycle_ctr > 0) then - trigger_o_x <= '1'; - trigger_cycle_ctr_x <= trigger_cycle_ctr - 1; - if (reg_testpulse_length > 0) then - wait_timer_init_x <= reg_testpulse_length; - NEXT_STATE <= S_SET_TESTPULSE; - else - wait_timer_init_x <= reg_trigger_period; - NEXT_STATE <= S_WAIT_TRIGGER_END; - end if; - else - NEXT_STATE <= S_IDLE; - end if; - - when S_SET_TESTPULSE => - testpulse_o_x <= '1'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_SET_TESTPULSE; - else - wait_timer_init_x <= reg_trigger_period - reg_testpulse_length; - NEXT_STATE <= S_WAIT_TRIGGER_END; - end if; - - when S_WAIT_TRIGGER_END => - if (wait_timer_done = '0') then - NEXT_STATE <= S_WAIT_TRIGGER_END; - else - NEXT_STATE <= S_NEXT_CYCLE; - end if; - - end case; end process PROC_TRIGGER_OUT; ----------------------------------------------------------------------------- diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd index 281d8cf..7fb5480 100644 --- a/nxyter/source/nx_trigger_handler.vhd +++ b/nxyter/source/nx_trigger_handler.vhd @@ -38,20 +38,16 @@ architecture Behavioral of nx_trigger_handler is signal start_cycle : std_logic; signal wait_timer_init : unsigned(7 downto 0); - signal wait_timer_init_x : unsigned(7 downto 0); signal wait_timer_done : std_logic; signal trigger_o : std_logic; - signal trigger_o_x : std_logic; signal timestamp_hold_o : std_logic; - signal timestamp_hold_o_x : std_logic; signal trigger_busy_o : std_logic; - signal trigger_busy_o_x : std_logic; type STATES is (S_IDLE, S_START, S_WAIT_TRIGGER_RELEASE ); - signal STATE, NEXT_STATE : STATES; + signal STATE : STATES; -- TRBNet Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); @@ -87,8 +83,8 @@ begin -- Trigger Handler ----------------------------------------------------------------------------- - PROC_TRIGGER_HANDLER_TRANSFER: process (CLK_IN) - begin + PROC_TRIGGER_HANDLER: process(CLK_IN) + begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1') then trigger_o <= '0'; @@ -97,47 +93,35 @@ begin wait_timer_init <= (others => '0'); STATE <= S_IDLE; else - trigger_o <= trigger_o_x; - timestamp_hold_o <= timestamp_hold_o_x; - trigger_busy_o <= trigger_busy_o_x; - wait_timer_init <= wait_timer_init_x; - STATE <= NEXT_STATE; + trigger_o <= '0'; + timestamp_hold_o <= '0'; + trigger_busy_o <= '1'; + wait_timer_init <= (others => '0'); + + case STATE is + when S_IDLE => + if (TRIGGER_IN = '1') then + trigger_o <= '1'; + timestamp_hold_o <= '1'; + STATE <= S_START; + else + trigger_busy_o <= '0'; + STATE <= S_IDLE; + end if; + + when S_START => + STATE <= S_WAIT_TRIGGER_RELEASE; + + when S_WAIT_TRIGGER_RELEASE => + if (TRIGGER_RELEASE_IN = '0') then + STATE <= S_WAIT_TRIGGER_RELEASE; + else + STATE <= S_IDLE; + end if; + + end case; end if; end if; - end process PROC_TRIGGER_HANDLER_TRANSFER; - - PROC_TRIGGER_HANDLER: process(STATE, - TRIGGER_IN, - TRIGGER_RELEASE_IN - ) - begin - trigger_o_x <= '0'; - timestamp_hold_o_x <= '0'; - trigger_busy_o_x <= '1'; - wait_timer_init_x <= (others => '0'); - - case STATE is - when S_IDLE => - if (TRIGGER_IN = '1') then - trigger_o_x <= '1'; - timestamp_hold_o_x <= '1'; - NEXT_STATE <= S_START; - else - trigger_busy_o_x <= '0'; - NEXT_STATE <= S_IDLE; - end if; - - when S_START => - NEXT_STATE <= S_WAIT_TRIGGER_RELEASE; - - when S_WAIT_TRIGGER_RELEASE => - if (TRIGGER_RELEASE_IN = '0') then - NEXT_STATE <= S_WAIT_TRIGGER_RELEASE; - else - NEXT_STATE <= S_IDLE; - end if; - - end case; end process PROC_TRIGGER_HANDLER; ----------------------------------------------------------------------------- diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd index 5b1b1c5..01e38af 100644 --- a/nxyter/source/nxyter.vhd +++ b/nxyter/source/nxyter.vhd @@ -456,7 +456,7 @@ begin ------------------------------------------------------------------------------- -- FPGA Timestamp ------------------------------------------------------------------------------- - + nx_fpga_timestamp_1: nx_fpga_timestamp port map ( CLK_IN => clk_256_o, @@ -648,67 +648,31 @@ begin ------------------------------------------------------------------------------- -- ADC 9228 Handler ------------------------------------------------------------------------------- --- adc_ad9222_1: adc_ad9222 + +-- adc_ad9222_1: entity work.adc_ad9222 -- generic map ( --- CHANNELS => 4, --- DEVICES => 2, +-- CHANNELS => 4, +-- DEVICES => 1, -- RESOLUTION => 12 -- ) -- port map ( -- CLK => CLK_IN, --- CLK_ADCREF => adc_ref_clk, --- CLK_ADCDAT => adc_dat_clk, --- RESTART_IN => adc_restart, --- ADCCLK_OUT => ADC_SC_CLK32_OUT, --- ADC_DATA(0) => ADC_NX_IN, --- ADC_DATA(7 downto 1) => open, --- ADC_DCO(0) => ADC_DCLK_IN, --- ADC_DCO(1) => ADC_DCLK_IN, --- ADC_FCO(0) => ADC_FCLK_IN, --- ADC_FCO(1) => open, --- DATA_OUT(11 downto 0) => adc_data_word, --- DATA_OUT(95 downto 12) => open, --- FCO_OUT => open, --- -- FCO_OUT(23 downto 1) => open, --- DATA_VALID_OUT(0) => adc_data_valid, --- DATA_VALID_OUT(1) => open, +-- CLK_ADCREF => nx_frame_clock_o, -- adc_ref_clk, +-- CLK_ADCDAT => nx_frame_clock_o, -- adc_dat_clk, +-- RESTART_IN => '0', -- adc_restart, +-- ADCCLK_OUT => ADC_SC_CLK32_OUT, -- adc_sc_clk32_o, +-- ADC_DATA(0) => ADC_A_IN, -- adc_data_i, +-- ADC_DATA(1) => ADC_B_IN, -- adc_data_i, +-- ADC_DATA(2) => ADC_NX_IN, -- adc_data_i, +-- ADC_DATA(3) => ADC_D_IN, -- adc_data_i, +-- ADC_DCO(0) => ADC_DCLK_IN, -- adc_dat_clk_i, +-- ADC_FCO(0) => ADC_FCLK_IN, -- adc_fco_clk_i, +-- DATA_OUT(0) => DEBUG_LINE_OUT(0), -- adc_data_word, +-- FCO_OUT(0) => DEBUG_LINE_OUT(1), -- adc_fco, +-- DATA_VALID_OUT(0) => DEBUG_LINE_OUT(2), -- adc_data_valid, -- DEBUG => open -- ); --- nx_frame_clock_o - - adc_ad9222_1: entity work.adc_ad9222 - generic map ( - CHANNELS => 4, - DEVICES => 1, - RESOLUTION => 12 - ) - port map ( - CLK => CLK_IN, - CLK_ADCREF => nx_frame_clock_o, -- adc_ref_clk, - CLK_ADCDAT => nx_frame_clock_o, -- adc_dat_clk, - RESTART_IN => '0', -- adc_restart, - ADCCLK_OUT => ADC_SC_CLK32_OUT, -- adc_sc_clk32_o, - ADC_DATA(0) => ADC_A_IN, -- adc_data_i, - ADC_DATA(1) => ADC_B_IN, -- adc_data_i, - ADC_DATA(2) => ADC_NX_IN, -- adc_data_i, - ADC_DATA(3) => ADC_D_IN, -- adc_data_i, - ADC_DCO(0) => ADC_DCLK_IN, -- adc_dat_clk_i, - ADC_FCO(0) => ADC_FCLK_IN, -- adc_fco_clk_i, - DATA_OUT(0) => DEBUG_LINE_OUT(0), -- adc_data_word, - FCO_OUT(0) => DEBUG_LINE_OUT(1), -- adc_fco, - DATA_VALID_OUT(0) => DEBUG_LINE_OUT(2), -- adc_data_valid, - DEBUG => open - ); - - --- adc_ref_clk <= adc_10MHz_clock; --- adc_dat_clk <= '0'; --- adc_restart <= RESET_IN; --- adc_data_i(0) <= adc_nx_i; --- adc_data_i(7 downto 1) <= (others => '0'); - - ------------------------------------------------------------------------------- -- nXyter Signals ------------------------------------------------------------------------------- @@ -719,25 +683,15 @@ begin ------------------------------------------------------------------------------- -- ADC Signals ------------------------------------------------------------------------------- - --ADC_SC_CLK32_OUT <= adc_sc_clk32_o; - --ADC_SC_CLK32_OUT <= nx_frame_clock_o; --- adc_fclk_i <= ADC_FCLK_IN; --- adc_dclk_i <= ADC_DCLK_IN; --- adc_a_i <= ADC_A_IN; --- adc_b_i <= ADC_B_IN; --- adc_nx_i <= ADC_NX_IN; --- adc_d_i <= ADC_D_IN; --- + + ------------------------------------------------------------------------------- -- I2C Signals ------------------------------------------------------------------------------- I2C_SM_RESET_OUT <= not i2c_sm_reset_o; I2C_REG_RESET_OUT <= not i2c_reg_reset_o; - - - ------------------------------------------------------------------------------- -- END diff --git a/nxyter/source/nxyter_data_handler.vhd b/nxyter/source/nxyter_data_handler.vhd index 96af811..fc1ffea 100644 --- a/nxyter/source/nxyter_data_handler.vhd +++ b/nxyter/source/nxyter_data_handler.vhd @@ -65,22 +65,16 @@ architecture Behavioral of nXyter_data_handler is -- LV2 Data Out Handler signal fee_trg_release_o : std_logic; - signal fee_trg_release_o_x : std_logic; signal fee_trg_statusbits_o : std_logic_vector(31 downto 0); - signal fee_trg_statusbits_o_x : std_logic_vector(31 downto 0); signal fee_data_o : std_logic_vector(31 downto 0); - signal fee_data_o_x : std_logic_vector(31 downto 0); signal fee_data_write_o : std_logic; - signal fee_data_write_o_x : std_logic; signal fee_data_finished_o : std_logic; - signal fee_data_finished_o_x : std_logic; - type STATES is (S_IDLE, S_SEND_DATA, S_END ); - signal STATE, NEXT_STATE : STATES; + signal STATE : STATES; begin @@ -98,7 +92,7 @@ begin DEBUG_LINE_OUT(8) <= FEE_DATA_ALMOST_FULL_IN; DEBUG_LINE_OUT(15 downto 9) <= LVL1_TRG_NUMBER_IN(6 downto 0); - PROC_DATA_HANDLER_TRANSFER: process(CLK_IN) + PROC_DATA_HANDLER: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then @@ -108,39 +102,30 @@ begin fee_data_finished_o <= '0'; STATE <= S_IDLE; else - fee_trg_release_o <= fee_trg_release_o_x; - fee_data_o <= fee_data_o_x; - fee_data_write_o <= fee_data_write_o_x; - fee_data_finished_o <= fee_data_finished_o_x; - STATE <= NEXT_STATE; + fee_trg_release_o <= '0'; + fee_data_o <= (others => '0'); + fee_data_write_o <= '0'; + fee_data_finished_o <= '0'; + + case STATE is + when S_IDLE => + if (LVL1_TRG_DATA_VALID_IN = '1') then + STATE <= S_SEND_DATA; + end if; + + when S_SEND_DATA => + fee_data_o <= x"deadbeef"; + fee_data_write_o <= '1'; + STATE <= S_END; + + when S_END => + fee_trg_release_o <= '1'; + fee_data_finished_o <= '1'; + STATE <= S_IDLE; + + end case; end if; end if; - end process PROC_DATA_HANDLER_TRANSFER; - - PROC_DATA_HANDLER: process(STATE) - begin - fee_trg_release_o_x <= '0'; - fee_data_o_x <= (others => '0'); - fee_data_write_o_x <= '0'; - fee_data_finished_o_x <= '0'; - - case STATE is - when S_IDLE => - if (LVL1_TRG_DATA_VALID_IN = '1') then - NEXT_STATE <= S_SEND_DATA; - end if; - - when S_SEND_DATA => - fee_data_o_x <= x"deadbeef"; - fee_data_write_o_x <= '1'; - NEXT_STATE <= S_END; - - when S_END => - fee_trg_release_o_x <= '1'; - fee_data_finished_o_x <= '1'; - NEXT_STATE <= S_IDLE; - - end case; end process PROC_DATA_HANDLER; diff --git a/nxyter/source/nxyter_registers.vhd b/nxyter/source/nxyter_registers.vhd index 50fb19f..5842bd8 100644 --- a/nxyter/source/nxyter_registers.vhd +++ b/nxyter/source/nxyter_registers.vhd @@ -45,7 +45,6 @@ architecture Behavioral of nxyter_registers is signal i2c_sm_reset_o : std_logic; signal i2c_reg_reset_o : std_logic; signal nx_ts_reset_o : std_logic; - signal wait_timer_init_x : unsigned(7 downto 0); type STATES is (S_IDLE, S_I2C_SM_RESET, @@ -55,7 +54,7 @@ architecture Behavioral of nxyter_registers is S_NX_TS_RESET ); - signal STATE, NEXT_STATE : STATES; + signal STATE : STATES; -- Wait Timer signal wait_timer_init : unsigned(7 downto 0); @@ -87,74 +86,67 @@ begin -- I2C SM Reset ----------------------------------------------------------------------------- - PROC_I2C_SM_RESET_TRANSFER: process(CLK_IN) - begin + PROC_I2C_SM_RESET: process(CLK_IN) + begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - wait_timer_init <= (others => '0'); - STATE <= S_IDLE; + wait_timer_init <= (others => '0'); + i2c_sm_reset_o <= '0'; + i2c_reg_reset_o <= '0'; + nx_ts_reset_o <= '0'; + STATE <= S_IDLE; else - wait_timer_init <= wait_timer_init_x; - STATE <= NEXT_STATE; + i2c_sm_reset_o <= '0'; + i2c_reg_reset_o <= '0'; + nx_ts_reset_o <= '0'; + wait_timer_init <= (others => '0'); + + case STATE is + when S_IDLE => + if (i2c_sm_reset_start = '1') then + STATE <= S_I2C_SM_RESET; + elsif (i2c_reg_reset_start = '1') then + STATE <= S_I2C_REG_RESET; + elsif (nx_ts_reset_start = '1') then + STATE <= S_NX_TS_RESET; + else + STATE <= S_IDLE; + end if; + + when S_I2C_SM_RESET => + i2c_sm_reset_o <= '1'; + wait_timer_init <= x"8f"; + STATE <= S_I2C_SM_RESET_WAIT; + + when S_I2C_SM_RESET_WAIT => + i2c_sm_reset_o <= '1'; + if (wait_timer_done = '0') then + STATE <= S_I2C_SM_RESET_WAIT; + else + STATE <= S_IDLE; + end if; + + when S_I2C_REG_RESET => + i2c_reg_reset_o <= '1'; + wait_timer_init <= x"8f"; + STATE <= S_I2C_REG_RESET_WAIT; + + when S_I2C_REG_RESET_WAIT => + i2c_reg_reset_o <= '1'; + if (wait_timer_done = '0') then + STATE <= S_I2C_REG_RESET_WAIT; + else + STATE <= S_IDLE; + end if; + + when S_NX_TS_RESET => + nx_ts_reset_o <= '1'; + STATE <= S_IDLE; + + end case; end if; end if; - end process PROC_I2C_SM_RESET_TRANSFER; - - PROC_I2C_SM_RESET: process(STATE, - i2c_sm_reset_start, - i2c_reg_reset_start, - nx_ts_reset_start, - wait_timer_done - ) - begin - i2c_sm_reset_o <= '0'; - i2c_reg_reset_o <= '0'; - nx_ts_reset_o <= '0'; - wait_timer_init_x <= (others => '0'); - case STATE is - when S_IDLE => - if (i2c_sm_reset_start = '1') then - NEXT_STATE <= S_I2C_SM_RESET; - elsif (i2c_reg_reset_start = '1') then - NEXT_STATE <= S_I2C_REG_RESET; - elsif (nx_ts_reset_start = '1') then - NEXT_STATE <= S_NX_TS_RESET; - else - NEXT_STATE <= S_IDLE; - end if; - - when S_I2C_SM_RESET => - i2c_sm_reset_o <= '1'; - wait_timer_init_x <= x"8f"; - NEXT_STATE <= S_I2C_SM_RESET_WAIT; - - when S_I2C_SM_RESET_WAIT => - i2c_sm_reset_o <= '1'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_I2C_SM_RESET_WAIT; - else - NEXT_STATE <= S_IDLE; - end if; - - when S_I2C_REG_RESET => - i2c_reg_reset_o <= '1'; - wait_timer_init_x <= x"8f"; - NEXT_STATE <= S_I2C_REG_RESET_WAIT; - - when S_I2C_REG_RESET_WAIT => - i2c_reg_reset_o <= '1'; - if (wait_timer_done = '0') then - NEXT_STATE <= S_I2C_REG_RESET_WAIT; - else - NEXT_STATE <= S_IDLE; - end if; - - when S_NX_TS_RESET => - nx_ts_reset_o <= '1'; - NEXT_STATE <= S_IDLE; - - end case; end process PROC_I2C_SM_RESET; -----------------------------------------------------------------------------