From: hadeshyp Date: Wed, 6 Oct 2010 13:22:09 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~160 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0879f79823bd72a23c5667e053e333fac955b0f7;p=trbnet.git *** empty log message *** --- diff --git a/media_interfaces/trb_net16_rx_comma_handler.vhd b/media_interfaces/trb_net16_rx_comma_handler.vhd index 21d59e1..3bc3e7f 100644 --- a/media_interfaces/trb_net16_rx_comma_handler.vhd +++ b/media_interfaces/trb_net16_rx_comma_handler.vhd @@ -121,6 +121,9 @@ signal crc_reset : std_logic; signal start_toc : unsigned(7 downto 0); signal start_toc_c : std_logic; +-- gk 06.10.10 +signal crc_comma_position : unsigned(3 downto 0); + begin ---------------------------------------------------------------------- @@ -232,6 +235,21 @@ rst_toggle <= '1' when ( ((comma_idle = '1') and (comma_toggle = '0') and (comma -- count correctly received IDLE commas ce_toggle <= '1' when ( (comma_idle = '1') and (comma_toggle = '1') and (comma_locked_x = '0') ) else '0'; +-- gk 06.10.10 +CRC_COMMA_POSITION_PROC : process +begin + if rising_edge(CLK_IN) then + if (RESET_IN = '1') or (c_stx_x = '1') then + crc_comma_position <= (others => '0'); + else + crc_comma_position <= crc_comma_position + to_unsigned(1, 1); + end if; + end if; +end process CRC_COMMA_POSITION_PROC; + +-- gk 06.10.10 +crc_comma_pos_wrong <= '1' when (crc_comma_position = to_unsigned(10, 4)) and (c_crc_x = '0') else '0'; + -- reference toggle bit for 16bit reconstruction THE_COMMA_TOGGLE_PROC: process( CLK_IN ) begin @@ -279,7 +297,8 @@ begin elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') and c_reset_x = '0' ) or ((crc_match = '0' or buf_rx_cv = '1') and comma_crc_x = '1' and crc_active = '1') or c_invalid_k_x = '1' - or START_GONE_WRONG_IN = '1' then + or START_GONE_WRONG_IN = '1' + or crc_comma_pos_wrong = '1' then -- gk 06.10.10 fifo_inhibit <= '1'; end if; end if; @@ -289,7 +308,7 @@ end process THE_FIFO_INHIBIT_PROC; START_TOC_PROC : process(CLK_IN) begin if rising_edge(CLK_IN) then - if (RESET_IN = '1') or (fifo_inhibit = '0') or start_toc_c = '1' then + if (RESET_IN = '1') or (fifo_inhibit = '0') or (start_toc_c = '1') then start_toc <= (others => '0'); elsif (fifo_inhibit = '1') and (comma_stx = '0') then start_toc <= start_toc + to_unsigned(1,1);