From: Jan Michel Date: Thu, 30 Jun 2022 20:07:45 +0000 (+0200) Subject: fixed new standalone endpoint for slow control X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=08945de9c3c58eefdc97144dfb1f9ac0d2ffa73b;p=trbnet.git fixed new standalone endpoint for slow control --- diff --git a/trb_net16_endpoint_standalone_sctrl.vhd b/trb_net16_endpoint_standalone_sctrl.vhd index ad0576c..bedd0b3 100644 --- a/trb_net16_endpoint_standalone_sctrl.vhd +++ b/trb_net16_endpoint_standalone_sctrl.vhd @@ -17,9 +17,10 @@ entity trb_net16_endpoint_standalone_sctrl is APL_WRITE_ALL_WORDS : integer := c_NO; ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; - REGIO_USE_1WIRE_INTERFACE : integer range 0 to 4 := c_YES + REGIO_USE_1WIRE_INTERFACE : integer range 0 to 5 := c_YES ); port( @@ -29,15 +30,16 @@ entity trb_net16_endpoint_standalone_sctrl is CLK_EN : in std_logic := '1'; --Port to GbE - GSC_INIT_DATAREADY_IN : in std_logic; - GSC_INIT_DATA_IN : in std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_INIT_READ_OUT : out std_logic; - GSC_REPLY_DATAREADY_OUT : out std_logic; - GSC_REPLY_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_REPLY_READ_IN : in std_logic; - GBE_MAKE_RESET_IN : in std_logic; --for monitoring only + GSC_INIT_DATAREADY_IN : in std_logic; + GSC_INIT_DATA_IN : in std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_INIT_READ_OUT : out std_logic; + GSC_REPLY_DATAREADY_OUT : out std_logic; + GSC_REPLY_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_REPLY_READ_IN : in std_logic; + GSC_BUSY_OUT : out std_logic; + GBE_MAKE_RESET_IN : in std_logic; --for monitoring only --Slow Control Port --common registers 0x00-0x2F @@ -61,49 +63,47 @@ entity trb_net16_endpoint_standalone_sctrl is TIMERS_OUT : out TIMERS; --clock ticks, temperature, unique id MY_ADDRESS_OUT : out std_logic_vector(15 downto 0) - - ); + ); end entity; architecture arch of trb_net16_endpoint_standalone_sctrl is - signal temperature_i : std_logic_vector (11 downto 0); - signal unique_id_i : std_logic_vector (63 downto 0); - signal my_address_i : std_logic_vector (15 downto 0); - signal regio_rx : CTRLBUS_RX; - signal make_trbnet_reset : std_logic; - signal last_make_trbnet_reset : std_logic; - signal link_and_reset_status : std_logic_vector(3 downto 0); + signal temperature_i : std_logic_vector (11 downto 0); + signal unique_id_i : std_logic_vector (63 downto 0); + signal my_address_i : std_logic_vector (15 downto 0); + signal regio_rx : CTRLBUS_RX; + signal make_trbnet_reset : std_logic; + signal last_make_trbnet_reset : std_logic; + signal link_and_reset_status : unsigned(3 downto 0); - signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0); - signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); - signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); - signal buf_IDRAM_WR_IN : std_logic; - signal buf_stat_onewire : std_logic_vector(31 downto 0); + signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0); + signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); + signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); + signal buf_IDRAM_WR_IN : std_logic; + signal buf_stat_onewire : std_logic_vector(31 downto 0); signal buf_COMMON_STAT_REG_IN : std_logic_vector(std_COMSTATREG*32-1 downto 0); signal buf_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0); signal buf_COMMON_STAT_REG_STROBE : std_logic_vector(std_COMSTATREG-1 downto 0); signal buf_COMMON_CTRL_REG_STROBE : std_logic_vector(std_COMCTRLREG-1 downto 0); - signal buf_APL_DATA_IN : std_logic_vector(15 downto 0); - signal buf_APL_PACKET_NUM_IN : std_logic_vector(2 downto 0); - signal buf_APL_DATAREADY_IN : std_logic; - signal buf_APL_READ_OUT : std_logic; - signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0); - signal buf_APL_DTYPE_IN : std_logic_vector(3 downto 0); - signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(31 downto 0); - signal buf_APL_SEND_IN : std_logic; - signal buf_APL_DATA_OUT : std_logic_vector(15 downto 0); - signal buf_APL_PACKET_NUM_OUT : std_logic_vector(2 downto 0); - signal buf_APL_DATAREADY_OUT : std_logic; - signal buf_APL_READ_IN : std_logic; - signal buf_APL_TYP_OUT : std_logic_vector(2 downto 0); - signal buf_APL_RUN_OUT : std_logic; - signal buf_APL_SEQNR_OUT : std_logic_vector(7 downto 0); + signal buf_APL_DATA_IN : std_logic_vector(15 downto 0); + signal buf_APL_PACKET_NUM_IN : std_logic_vector(2 downto 0); + signal buf_APL_DATAREADY_IN : std_logic; + signal buf_APL_READ_OUT : std_logic; + signal buf_APL_SHORT_TRANSFER_IN : std_logic; + signal buf_APL_DTYPE_IN : std_logic_vector(3 downto 0); + signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(31 downto 0); + signal buf_APL_SEND_IN : std_logic; + signal buf_APL_DATA_OUT : std_logic_vector(15 downto 0); + signal buf_APL_PACKET_NUM_OUT : std_logic_vector(2 downto 0); + signal buf_APL_DATAREADY_OUT : std_logic; + signal buf_APL_READ_IN : std_logic; + signal buf_APL_TYP_OUT : std_logic_vector(2 downto 0); + signal buf_APL_RUN_OUT : std_logic; + signal buf_APL_SEQNR_OUT : std_logic_vector(7 downto 0); + signal stat_fifo_to_int_i : std_logic_vector(31 downto 0); - - begin DAT_PASSIVE_API: trb_net16_api_base @@ -123,53 +123,55 @@ begin ) port map ( -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => '1', + CLK => CLK, + RESET => RESET, + CLK_EN => '1', -- APL Transmitter port - APL_DATA_IN => buf_APL_DATA_IN, - APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN, - APL_DATAREADY_IN => buf_APL_DATAREADY_IN, - APL_READ_OUT => buf_APL_READ_OUT, - APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => buf_APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN, - APL_SEND_IN => buf_APL_SEND_IN, - APL_TARGET_ADDRESS_IN => (others => '0'), - -- Receiver port - APL_DATA_OUT => buf_APL_DATA_OUT, - APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT, - APL_TYP_OUT => buf_APL_TYP_OUT, - APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT, - APL_READ_IN => buf_APL_READ_IN, - -- APL Control port - APL_RUN_OUT => buf_APL_RUN_OUT, - APL_MY_ADDRESS_IN => my_address_i, - APL_SEQNR_OUT => buf_APL_SEQNR_OUT, - APL_LENGTH_IN => (others => '1'), + APL_DATA_IN => buf_APL_DATA_IN, + APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN, + APL_DATAREADY_IN => buf_APL_DATAREADY_IN, + APL_READ_OUT => buf_APL_READ_OUT, + APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN, + APL_DTYPE_IN => buf_APL_DTYPE_IN, + APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN, + APL_SEND_IN => buf_APL_SEND_IN, + APL_TARGET_ADDRESS_IN => (others => '0'), + -- Receiver port + APL_DATA_OUT => buf_APL_DATA_OUT, + APL_PACKET_NUM_OUT => buf_APL_PACKET_NUM_OUT, + APL_TYP_OUT => buf_APL_TYP_OUT, + APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT, + APL_READ_IN => buf_APL_READ_IN, + -- APL Control port + APL_RUN_OUT => buf_APL_RUN_OUT, + APL_MY_ADDRESS_IN => my_address_i, + APL_SEQNR_OUT => buf_APL_SEQNR_OUT, + APL_LENGTH_IN => (others => '1'), -- Internal direction port - INT_MASTER_DATAREADY_OUT => open, - INT_MASTER_DATA_OUT => open, - INT_MASTER_PACKET_NUM_OUT=> open, - INT_MASTER_READ_IN => '1', - INT_MASTER_DATAREADY_IN => GSC_INIT_DATAREADY_IN, - INT_MASTER_DATA_IN => GSC_INIT_DATA_IN, - INT_MASTER_PACKET_NUM_IN => GSC_INIT_PACKET_NUM_IN, - INT_MASTER_READ_OUT => GSC_INIT_READ_OUT, - INT_SLAVE_DATAREADY_OUT => GSC_REPLY_DATAREADY_OUT, - INT_SLAVE_DATA_OUT => GSC_REPLY_DATA_OUT, - INT_SLAVE_PACKET_NUM_OUT => GSC_REPLY_PACKET_NUM_OUT, - INT_SLAVE_READ_IN => GSC_REPLY_READ_IN, - INT_SLAVE_DATAREADY_IN => '0', - INT_SLAVE_DATA_IN => x"0000", - INT_SLAVE_PACKET_NUM_IN => "000", - INT_SLAVE_READ_OUT => open, + INT_MASTER_DATAREADY_OUT => GSC_REPLY_DATAREADY_OUT, + INT_MASTER_DATA_OUT => GSC_REPLY_DATA_OUT, + INT_MASTER_PACKET_NUM_OUT => GSC_REPLY_PACKET_NUM_OUT, + INT_MASTER_READ_IN => GSC_REPLY_READ_IN, + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => x"0000", + INT_MASTER_PACKET_NUM_IN => "000", + INT_MASTER_READ_OUT => open, + INT_SLAVE_DATAREADY_OUT => open, + INT_SLAVE_DATA_OUT => open, + INT_SLAVE_PACKET_NUM_OUT => open, + INT_SLAVE_READ_IN => '1', + INT_SLAVE_DATAREADY_IN => GSC_INIT_DATAREADY_IN, + INT_SLAVE_DATA_IN => GSC_INIT_DATA_IN, + INT_SLAVE_PACKET_NUM_IN => GSC_INIT_PACKET_NUM_IN, + INT_SLAVE_READ_OUT => GSC_INIT_READ_OUT, -- Status and control port - CTRL_SEQNR_RESET => buf_COMMON_CTRL_REG_OUT(10), - STAT_FIFO_TO_INT => open, - STAT_FIFO_TO_APL => open - ); + CTRL_SEQNR_RESET => buf_COMMON_CTRL_REG_OUT(10), + STAT_FIFO_TO_INT => stat_fifo_to_int_i, + STAT_FIFO_TO_APL => open + ); + -- Hack from Jan... + GSC_BUSY_OUT <= '1' when stat_fifo_to_int_i(31 downto 29) /= "000" else '0'; regIO : trb_net16_regIO generic map( @@ -178,6 +180,7 @@ begin INIT_CTRL_REGS => (others => '0'), USED_CTRL_REGS => (others => '0'), USED_CTRL_BITMASK => (others => '0'), + INIT_ADDRESS => INIT_ADDRESS, INCLUDED_FEATURES => INCLUDED_FEATURES, HARDWARE_VERSION => HARDWARE_INFO, CLOCK_FREQ => CLOCK_FREQUENCY @@ -314,6 +317,28 @@ begin ); end generate; + gen_i2c_tc : if REGIO_USE_1WIRE_INTERFACE = c_I2C_TC generate + i2c_interface2 : trb_net_i2cwire2 + generic map( + USE_TEMPERATURE_READOUT => c_YES, + CLK_PERIOD => 10 + ) + port map( + CLK => CLK, + RESET => RESET, + READOUT_ENABLE_IN => '1', + --connection to I2C interface + SCL_INOUT => I2C_SCL, + SDA_INOUT => I2C_SDA, + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT => buf_IDRAM_DATA_IN, + ADDR_OUT => buf_IDRAM_ADDR_IN, + WRITE_OUT => buf_IDRAM_WR_IN, + TEMP_OUT => temperature_i, + ID_OUT => unique_id_i, + STAT => buf_stat_onewire + ); + end generate; ------------------------------------------------- -- Common Status Register @@ -322,7 +347,7 @@ begin begin buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN; buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature_i; - buf_COMMON_STAT_REG_IN(131 downto 128) <= link_and_reset_status(3 downto 0); + buf_COMMON_STAT_REG_IN(131 downto 128) <= std_logic_vector(link_and_reset_status(3 downto 0)); buf_COMMON_STAT_REG_IN(319 downto 288) <= buf_stat_onewire; end process; @@ -332,7 +357,7 @@ begin if rising_edge(CLK) then if make_trbnet_reset = '1' then - link_and_reset_status(3 downto 0) <= link_and_reset_status(3 downto 0) + '1'; + link_and_reset_status(3 downto 0) <= link_and_reset_status(3 downto 0) + 1; end if; if buf_COMMON_CTRL_REG_OUT(5) = '1' then