From: hadeshyp Date: Thu, 30 Jul 2009 13:43:59 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~407 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0899cdfc15675ef4328fe72bab05966fb8d887be;p=trbnet.git *** empty log message *** --- diff --git a/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd b/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd index e8b9131..3e42dbd 100755 --- a/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd +++ b/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd @@ -420,7 +420,7 @@ begin --------------------------------------------------------------------- gen_normal_serdes : if REVERSE_ORDER = c_NO generate - THE_SERDES: serdes_sfp_full_quad + THE_SERDES: serdes_gbe_all port map( core_txrefclk => clk, core_rxrefclk => clk, @@ -559,7 +559,7 @@ begin end generate; gen_twisted_serdes : if REVERSE_ORDER = c_YES generate - THE_SERDES: serdes_sfp_full_quad + THE_SERDES: serdes_gbe_all port map( core_txrefclk => clk, core_rxrefclk => clk, @@ -818,7 +818,7 @@ begin if( rising_edge(ff_txhalfclk) ) then last_fifo_tx_empty(i) <= fifo_tx_empty(i); if( (last_fifo_tx_empty(i) = '1') ) then -- or (tx_allow_qtx(i) = '0') - tx_data(i*16+15 downto i*16) <= x"c5bc"; + tx_data(i*16+15 downto i*16) <= x"50bc"; tx_k(i*2+1 downto i*2) <= "01"; else tx_data(i*16+15 downto i*16) <= fifo_tx_dout(i*18+15 downto i*18+0); diff --git a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd index 7b2e2fb..6a5fa14 100755 --- a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd +++ b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd @@ -80,7 +80,7 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp_gbe is ffc_rxpwdnb_ch2 : IN std_logic; ffc_macro_rst : IN std_logic; ffc_quad_rst : IN std_logic; - ffc_trst : IN std_logic; + ffc_trst : IN std_logic; hdoutp2 : OUT std_logic; hdoutn2 : OUT std_logic; ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0); @@ -464,7 +464,7 @@ begin if( rising_edge(ff_txhalfclk) ) then last_fifo_tx_empty <= fifo_tx_empty; if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then - tx_data <= x"c5bc"; + tx_data <= x"50bc"; tx_k <= "01"; -- elsif send_resync = '1' then -- tx_data <= x"7F7F"; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 98d5e1f..69cb232 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -806,6 +806,49 @@ package trb_net_components is + + component trb_net16_med_ecp_sfp_gbe is + generic( + SERDES_NUM : integer range 0 to 3 := 0; + EXT_CLOCK : integer range 0 to 1 := c_NO + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + + component trb_net16_med_ecp_sfp_8bit_4 is generic( REVERSE_ORDER : integer range 0 to 1 := c_NO @@ -889,6 +932,47 @@ package trb_net_components is + component trb_net16_med_ecp_sfp_4_gbe is + generic( + REVERSE_ORDER : integer range 0 to 1 := c_NO + -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0); + MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); + MED_READ_IN : in std_logic_vector(3 downto 0); + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(3 downto 0); + SD_RXD_N_IN : in std_logic_vector(3 downto 0); + SD_TXD_P_OUT : out std_logic_vector(3 downto 0); + SD_TXD_N_OUT : out std_logic_vector(3 downto 0); + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); + SD_LOS_IN : in std_logic_vector(3 downto 0); + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); + -- Status and control port + STAT_OP : out std_logic_vector (4*16-1 downto 0); + CTRL_OP : in std_logic_vector (4*16-1 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + component trb_net16_med_tlk is