From: hadeshyp <hadeshyp>
Date: Mon, 18 Feb 2008 16:16:50 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~594
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=091fb230c035f10603a6514fc32f4ffc126813b2;p=trbnet.git

*** empty log message ***
---

diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd
index 27ea0d8..0afaa82 100644
--- a/trb_net16_io_multiplexer.vhd
+++ b/trb_net16_io_multiplexer.vhd
@@ -364,10 +364,10 @@ ARBITER: trb_net_priority_arbiter
     variable k : integer range 0 to 2**c_MUX_WIDTH-1 := 0;
     begin
 --       j := get_bit_position(current_INT_READ_OUT);
---       current_mux_buffer(c_DATA_WIDTH-1 downto 0) <= INT_DATA_IN(c_DATA_WIDTH*(j+1)-1 downto c_DATA_WIDTH*j);
---       current_mux_buffer(c_DATA_WIDTH+c_NUM_WIDTH-1 downto c_DATA_WIDTH) <= INT_PACKET_NUM_IN(c_NUM_WIDTH*(j+1)-1 downto c_NUM_WIDTH*j);
---       if INT_PACKET_NUM_IN(c_NUM_WIDTH*(j+1)-1 downto c_NUM_WIDTH*j) = "00" then
---         current_mux_buffer(3+c_MUX_WIDTH-1 downto 3) <= conv_std_logic_vector(j, c_MUX_WIDTH);
+--       var_mux_buffer(c_DATA_WIDTH-1 downto 0) := INT_DATA_IN(c_DATA_WIDTH*(j+1)-1 downto c_DATA_WIDTH*j);
+--       var_mux_buffer(c_DATA_WIDTH+c_NUM_WIDTH-1 downto c_DATA_WIDTH) := INT_PACKET_NUM_IN(c_NUM_WIDTH*(j+1)-1 downto c_NUM_WIDTH*j);
+--       if var_mux_buffer(c_DATA_WIDTH+c_NUM_WIDTH-1 downto c_DATA_WIDTH) = "00" then
+--         var_mux_buffer(3+c_MUX_WIDTH-1 downto 3) := conv_std_logic_vector(j, c_MUX_WIDTH);
 --       end if;
       k := 0;
       var_mux_buffer := (others => '0');
diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd
index 857eb66..743e994 100644
--- a/trb_net16_med_tlk.vhd
+++ b/trb_net16_med_tlk.vhd
@@ -148,19 +148,17 @@ begin
       );
 
   fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) ) and rx_allow;
-  fifo_din_a <= fifo_almost_empty_a & (reg_RX_DV and not reg_RX_ER) & reg_RXD;
   fifo_rd_en_a <=   rx_allow;
-  buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_underflow_a;
 
 
 --   fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) or fifo_almost_empty_a) and rx_allow;
---   fifo_din_a <= fifo_almost_empty_a & (reg_RX_DV and not reg_RX_ER) & reg_RXD;
 --   fifo_rd_en_a <= not fifo_almost_empty_a and rx_allow;
---   buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_underflow_a  and rx_allow;
--- 
 
+
+  buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_underflow_a  and rx_allow;
   MED_ERROR_OUT <= buf_MED_ERROR_OUT;
   fifo_reset <= internal_reset;
+  fifo_din_a <= fifo_almost_empty_a & (reg_RX_DV and not reg_RX_ER) & reg_RXD;
 
   process(CLK)
     begin
@@ -205,6 +203,7 @@ begin
   STAT(56 downto 55) <= fifo_din_a(17 downto 16);
   STAT(57) <= fifo_underflow_a;
   STAT(58) <= fifo_underflow_m;
+  STAT(59) <= TLK_CLK_neg;
   --STAT(63 downto 57) <= (others => '0');
   
 
diff --git a/trb_net_std.vhd b/trb_net_std.vhd
index c3ac250..605c68e 100644
--- a/trb_net_std.vhd
+++ b/trb_net_std.vhd
@@ -157,13 +157,13 @@ package body trb_net_std is
     variable tmp : integer := 0;
     begin
       tmp := 0;
-      for i in arg'range loop
+      for i in  arg'range loop
         if arg(i) = '1' then
-          tmp := i;
+          return i;
         end if;
         --exit when arg(i) = '1';
       end loop;  -- i
-      return tmp;
+      return 0;
   end get_bit_position;