From: Manuel Penschuck Date: Wed, 25 Jun 2014 08:57:05 +0000 (+0200) Subject: CBMNet: Relaxed some time critical components. Design currently broken; back-up X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=09dcbdbbab9162d0e4c6e1755576399505bcff5c;p=trb3.git CBMNet: Relaxed some time critical components. Design currently broken; back-up --- diff --git a/cbmnet/code/cbmnet_phy_ecp3.vhd b/cbmnet/code/cbmnet_phy_ecp3.vhd index 5bd00a0..8530364 100755 --- a/cbmnet/code/cbmnet_phy_ecp3.vhd +++ b/cbmnet/code/cbmnet_phy_ecp3.vhd @@ -14,7 +14,7 @@ use work.cbmnet_phy_pkg.all; entity cbmnet_phy_ecp3 is generic( IS_SYNC_SLAVE : integer := c_YES; --select slave mode - DETERMINISTIC_LATENCY : integer := c_NO; -- if selected proper alignment of barrel shifter and word alignment is enforced (link may come up slower) + DETERMINISTIC_LATENCY : integer := c_YES; -- if selected proper alignment of barrel shifter and word alignment is enforced (link may come up slower) IS_SIMULATED : integer := c_NO; INCL_DEBUG_AIDS : integer := c_YES ); @@ -77,7 +77,6 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is -- Clocks and global resets signal clk_125_local : std_logic; -- local 125 MHz reference clock driven by clock generators - signal clk_125_i : std_logic; -- in FEE mode, driven by recovered clock, in Master mode, driven by local clock signal rclk_250_i : std_logic; -- recovered word clock signal rclk_125_i : std_logic; -- rclk_250_i divided by two. aligned s.t. the rising edge corresponds to the lower received word signal clk_tx_full_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL @@ -86,9 +85,6 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal rst_i : std_logic; -- High-active reset driven by external logic signal rst_n_i : std_logic; -- Low-active version of rst_i - - signal clk_serdes_rx_ref : std_logic; - signal clk_serdes_tx_ref : std_logic; -- SERDES/PCS -- status @@ -98,6 +94,7 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal lsm_status_i : std_logic; signal rx_dec_error_i: std_logic; + signal rx_dec_errors2_i : std_logic_vector(1 downto 0); signal rx_dec_error_125_i, rx_dec_error_125_buf_i: std_logic_vector(1 downto 0); signal rx_error_delay : std_logic_vector(3 downto 0); -- shift register to detect a "stable error condition" @@ -237,6 +234,10 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal rx_data_sp_i0, rx_data_sp_i1, rx_data_sp_i2, rx_data_sp_i3 : std_logic_vector(17 downto 0); + --signal see_dlm_lb_i, see_dlm_lb_buf_i : std_logic_vector(15 downto 0) := (others => '0'); + --signal see_dlm_lb_aggr_i, see_dlm_hb_i, see_dlm_hb_buf_i : std_logic; + --signal stat_sync_dlm_counter_i, stat_sync_dlm_inv_counter_i : unsigned(7 downto 0); + begin assert IS_SYNC_SLAVE = c_YES report "Support of clock master PHY is not tested anymore and probably broken" @@ -245,7 +246,7 @@ begin DETERMINISTIC_LATENCY_C <= '1' when DETERMINISTIC_LATENCY = c_YES else '0'; clk_125_local <= CLK; - CLK_RX_HALF_OUT <= rclk_125_i when IS_SYNC_SLAVE = c_YES else clk_tx_half_i; + CLK_RX_HALF_OUT <= rclk_125_i; CLK_RX_FULL_OUT <= rclk_250_i; SD_TXDIS_OUT <= '0'; @@ -253,18 +254,6 @@ begin rst_i <= (CLEAR or CTRL_OP(0)); rst_n_i <= not rst_i; - gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate - clk_125_i <= rclk_125_i; - clk_serdes_rx_ref <= clk_125_local; - clk_serdes_tx_ref <= rclk_125_i; - end generate; - - gen_master_clock : if IS_SYNC_SLAVE = c_NO generate - clk_125_i <= clk_tx_half_i; - clk_serdes_rx_ref <= clk_tx_half_i; - clk_serdes_tx_ref <= clk_125_local; - end generate; - ------------------------------------------------- -- Serdes ------------------------------------------------- @@ -283,9 +272,9 @@ begin tx_full_clk_ch0 => clk_tx_full_i, tx_half_clk_ch0 => open, - fpga_rxrefclk_ch0 => clk_serdes_rx_ref, - fpga_txrefclk => clk_serdes_tx_ref, - txiclk_ch0 => clk_tx_full_i, + fpga_rxrefclk_ch0 => clk_125_local, + fpga_txrefclk => rclk_125_i, + txiclk_ch0 => rclk_250_i, -- RESETS rst_qd_c => rst_qd_i, @@ -323,7 +312,7 @@ begin rx_los_low_ch0_s => rx_los_low_i, rx_cdr_lol_ch0_s => rx_cdr_lol_i, lsm_status_ch0_s => lsm_status_i, - + SCI_WRDATA => sci_data_in_i, SCI_RDDATA => sci_data_out_i, SCI_ADDR => sci_addr_i(5 downto 0), @@ -332,7 +321,48 @@ begin SCI_RD => sci_read_i, SCI_WRN => sci_write_i ); + + THE_RX_GEAR: CBMNET_PHY_RX_GEAR + generic map ( + IS_SYNC_SLAVE => IS_SYNC_SLAVE + ) port map ( + -- SERDES PORT + CLK_250_IN => rclk_250_i, -- in std_logic; + PCS_READY_IN => rx_rst_fsm_ready_i, -- in std_logic; + SERDES_RESET_OUT=> gear_to_fsm_rst_i, -- out std_logic; + DATA_IN => rx_data_from_serdes_i, -- in std_logic_vector( 8 downto 0); + + -- RM PORT + RM_RESET_IN => rm_rx_to_gear_reset_i, -- in std_logic; + CLK_125_OUT => rclk_125_i, -- out std_logic; + RESET_OUT => gear_to_rm_rst_i, -- out std_logic; + DATA_OUT => rx_data_from_gear_i, -- out std_logic_vector(17 downto 0) + + DEBUG_OUT => rx_gear_debug_i + ); + + rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local); + + THE_TX_GEAR: CBMNET_PHY_TX_GEAR + generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE) + port map ( + CLK_250_IN => clk_tx_full_i, -- in std_logic; + CLK_125_IN => rclk_125_i, -- in std_logic; + CLK_125_OUT => clk_tx_half_i, + + RESET_IN => tx_gear_reset_i, -- in std_logic; + ALLOW_RELOCK_IN => tx_gear_allow_relock_i, -- in std_logic + + TX_READY_OUT => tx_gear_ready_i, + + DATA_IN => tx_data_i, -- in std_logic_vector(17 downto 0) + DATA_OUT => tx_data_to_serdes_i -- out std_logic_vector(8 downto 0); + ); + tx_gear_reset_i <= not tx_rst_fsm_ready_i; + tx_gear_allow_relock_i <= '0'; + + tx_serdes_rst_i <= '0'; --no function serdes_rst_qd_i <= '0'; --included in rst_qd_i @@ -369,7 +399,7 @@ begin rx_error_delay <= rx_error_delay(rx_error_delay'high - 2 downto 0) & rx_dec_error_125_buf_i when rising_edge(clk_125_local); process is begin - wait until rising_edge(clk_125_i); + wait until rising_edge(rclk_125_i); if RESET='1' then stat_decode_error_counter_i <= (others => '0'); elsif rx_dec_error_125_buf_i = "11" then @@ -405,81 +435,6 @@ begin tx_rst_fsm_ready_i <= '1'; end if; end process; - - THE_RX_GEAR: CBMNET_PHY_RX_GEAR - generic map ( - IS_SYNC_SLAVE => IS_SYNC_SLAVE - ) port map ( - -- SERDES PORT - CLK_250_IN => rclk_250_i, -- in std_logic; - PCS_READY_IN => rx_rst_fsm_ready_i, -- in std_logic; - SERDES_RESET_OUT=> gear_to_fsm_rst_i, -- out std_logic; - DATA_IN => rx_data_from_serdes_i, -- in std_logic_vector( 8 downto 0); - - -- RM PORT - RM_RESET_IN => rm_rx_to_gear_reset_i, -- in std_logic; - CLK_125_OUT => rclk_125_i, -- out std_logic; - RESET_OUT => gear_to_rm_rst_i, -- out std_logic; - DATA_OUT => rx_data_from_gear_i, -- out std_logic_vector(17 downto 0) - - DEBUG_OUT => rx_gear_debug_i - ); - - process is - variable state_v : std_logic; - variable data_buf_v : std_logic_vector(8 downto 0); - begin - wait until rising_edge(rclk_250_i); - - if state_v = '0' then - rx_data_debug_i(7 downto 0) <= data_buf_v(7 downto 0); - rx_data_debug_i(16) <= data_buf_v(8); - else - rx_data_debug_i(15 downto 8) <= data_buf_v(7 downto 0); - rx_data_debug_i(17) <= data_buf_v(8); - end if; - - data_buf_v := data_buf_v; - state_v := not state_v; - end process; - - rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local) or (IS_SYNC_SLAVE = c_YES); - - THE_TX_GEAR: CBMNET_PHY_TX_GEAR - generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE) - port map ( - CLK_250_IN => clk_tx_full_i, -- in std_logic; - CLK_125_IN => clk_serdes_tx_ref, -- in std_logic; - CLK_125_OUT => clk_tx_half_i, - - RESET_IN => tx_gear_reset_i, -- in std_logic; - ALLOW_RELOCK_IN => tx_gear_allow_relock_i, -- in std_logic - - TX_READY_OUT => tx_gear_ready_i, - - DATA_IN => tx_data_i, -- in std_logic_vector(17 downto 0) - - DATA_OUT => tx_data_to_serdes_i -- out std_logic_vector(8 downto 0); - ); - tx_gear_reset_i <= not tx_rst_fsm_ready_i; - tx_gear_allow_relock_i <= (not tx_rst_fsm_ready_i and not CTRL_OP(1) and DETERMINISTIC_LATENCY_C) or CTRL_OP(2); - --- process is --- begin --- wait until rising_edge(clk_tx_full_i); --- --- tx_data_debug_state_i <= not tx_data_debug_state_i; --- --- if tx_data_debug_state_i = '1' then --- tx_data_debug_i(7 downto 0) <= tx_data_to_serdes_i(7 downto 0); --- tx_data_debug_i(16) <= tx_data_to_serdes_i(8); --- --- else --- tx_data_debug_i(15 downto 8) <= tx_data_to_serdes_i(7 downto 0); --- tx_data_debug_i(17) <= tx_data_to_serdes_i(8); --- --- end if; --- end process; ------------------------------------------------- -- CBMNet Ready Modules @@ -492,7 +447,7 @@ begin INCL_8B10B_DEC => 0 ) port map ( - rx_clk => clk_125_i, -- in std_logic; + rx_clk => rclk_125_i, -- in std_logic; res_n_rx => gear_to_rm_n_rst_i, -- in std_logic; rxpcs_reinit => rm_tx_to_rx_reinit_i, -- in std_logic; -- Reinit RXPCS rxdata_in(17 downto 0) => rx_data_i, @@ -516,23 +471,18 @@ begin PHY_RXDATA_OUT <= rx_data_i(15 downto 0); PHY_RXDATA_K_OUT <= rx_data_i(17 downto 16); - gear_to_rm_n_rst_i <= not gear_to_rm_rst_i when rising_edge(clk_125_i); + gear_to_rm_n_rst_i <= not gear_to_rm_rst_i when rising_edge(rclk_125_i); THE_TX_READY: cn_tx_pcs_wrapper generic map ( --- READY_CHAR0 => , --std_logic_vector( 7 downto 0) := K284; --- READY_CHAR1 => , --std_logic_vector( 7 downto 0) := K287; --- ALIGN_CHAR => , --std_logic_vector( 7 downto 0) := K285; --- PMA_INIT_CHAR => , --std_logic_vector(19 downto 0) := x"aaaaa"; - REVERSE_OUTPUT => 0, --integer range 0 to 1 := 1; LINK_MASTER => 0, --integer range 0 to 1 := 1; SYNC_SIGNALS => 1, --integer range 0 to 1 := 1; INCL_8B10B_ENC => 0 --integer range 0 to 1 := 1 ) port map ( - tx_clk => clk_125_i, --in std_logic; + tx_clk => rclk_125_i, --in std_logic; res_n_tx => tx_rst_fsm_ready_buf_i, --in std_logic; pcs_restart => CTRL_OP(14), --in std_logic; -- restart pcs layer pma_ready => tx_gear_ready_i, --in std_logic; @@ -558,9 +508,9 @@ begin rm_rx_status_for_tx_i <= rm_rx_almost_ready_i or rm_rx_ready_i; - -- clock domain crossing from clk_125_local to clk_125_i + -- clock domain crossing from clk_125_local to rclk_125_i PROC_SYNC_FSM_READY: process is begin - wait until rising_edge(clk_125_i); + wait until rising_edge(rclk_125_i); if IS_SYNC_SLAVE = c_YES then tx_rst_fsm_ready_buf_i <= tx_rst_fsm_ready_i and not gear_to_rm_rst_i; @@ -571,7 +521,7 @@ begin end if; end process; - serdes_ready_i <= rm_tx_ready_i and rm_rx_rxpcs_ready_i when rising_edge(clk_125_i); + serdes_ready_i <= rm_tx_ready_i and rm_rx_rxpcs_ready_i when rising_edge(rclk_125_i); led_ok_i <= serdes_ready_i; SERDES_ready <= serdes_ready_i; @@ -678,49 +628,9 @@ begin last_rx_serdes_rst_i := rx_serdes_rst_i; end process; --- PROC_SENSE_RX_DLM0: process is --- variable detected_first_word_v : std_logic := '0'; --- begin --- wait until rising_edge(rclk_250_i); --- low_level_rx_see_dlm0 <= '0'; --- --- if detected_first_word_v = '0' then --- if rx_data_from_serdes_i = "1" & x"fb" then --- detected_first_word_v := '1'; --- end if; --- --- else --- detected_first_word_v := '0'; --- if rx_data_from_serdes_i = "001101010" then --- low_level_rx_see_dlm0 <= '1'; --- end if; --- --- end if; --- end process; - --- PROC_SENSE_TX_DLM0: process is --- variable detected_first_word_v : std_logic := '0'; --- begin --- wait until rising_edge(clk_tx_full_i); --- low_level_tx_see_dlm0 <= '0'; --- --- if detected_first_word_v = '0' then --- if tx_data_to_serdes_i = "1" & x"fb" then --- detected_first_word_v := '1'; --- end if; --- --- else --- detected_first_word_v := '0'; --- if tx_data_to_serdes_i = "001101010" then --- low_level_tx_see_dlm0 <= '1'; --- end if; --- --- end if; --- end process; - PROC_SENSE_TX_DLM125: process is begin - wait until rising_edge(clk_125_i); + wait until rising_edge(rclk_125_i); low_level_tx_see_dlm0_125 <= '0'; if tx_data_i = "10" & x"fb6a" then @@ -728,34 +638,24 @@ begin end if; end process; - proc_sense_init_ack: process is - begin - wait until rising_edge(clk_125_i); - if reset = '1' then - stat_init_ack_counter_i <= (others => '0'); - elsif rx_data_i = "11" & K297 & K283 then - stat_init_ack_counter_i <= stat_init_ack_counter_i + 1; - end if; - end process; - - process is + process is variable rx_v, tx_v : std_logic_vector(17 downto 0); - begin - wait until rising_edge(clk_125_i); - + begin + wait until rising_edge(rclk_125_i); + if reset = '1' or rx_v /= rx_data_i then rx_stab_i <= (others => '0'); - else rx_stab_i <= rx_stab_i + 1; end if; + else rx_stab_i <= rx_stab_i + 1; end if; if reset = '1' or tx_v /= tx_data_i then tx_stab_i <= (others => '0'); else tx_stab_i <= tx_stab_i + 1; end if; - - rx_v := rx_data_i; - tx_v := tx_data_i; - end process; + + rx_v := rx_data_i; + tx_v := tx_data_i; + end process; PROC_SENSE_DLMS: process begin - wait until rising_edge(clk_125_i); + wait until rising_edge(rclk_125_i); if serdes_ready_i = '0' then stat_dlm_counter_i <= (others => '0'); @@ -796,40 +696,86 @@ begin DEBUG_OUT(315 downto 244) <= rx_data_sp_i3(17 downto 0) & rx_data_sp_i2(17 downto 0) & rx_data_sp_i1(17 downto 0) & rx_data_sp_i0(17 downto 0); DEBUG_OUT(333 downto 316) <= PHY_TXDATA_K_IN(1 downto 0) & PHY_TXDATA_IN(15 downto 0); + --DEBUG_OUT(341 downto 334) <= stat_sync_dlm_inv_counter_i(7 downto 0) when rising_edge(rclk_125_i); + --DEBUG_OUT(349 downto 342) <= stat_sync_dlm_counter_i(7 downto 0) when rising_edge(rclk_125_i); + + --DEBUG_OUT(255 downto 170) <= (others => '0'); -- DEBUG_OUT_END - process is - begin - wait until rising_edge(rclk_125_i); - if rx_data_i /= "10" & x"fcc3" then - rx_data_sp_i0 <= rx_data_i; - rx_data_sp_i1 <= rx_data_sp_i0; - rx_data_sp_i2 <= rx_data_sp_i1; - rx_data_sp_i3 <= rx_data_sp_i2; - end if; - end process; + process is + begin + wait until rising_edge(rclk_125_i); + if rx_data_i /= "10" & x"fcc3" then + rx_data_sp_i0 <= rx_data_i; + rx_data_sp_i1 <= rx_data_sp_i0; + rx_data_sp_i2 <= rx_data_sp_i1; + rx_data_sp_i3 <= rx_data_sp_i2; + end if; + end process; + --PROC_SEE_FAST_DLM: process is + --variable saw_lb_v, saw_hb_v : std_logic; + --begin + --wait until rising_edge(rclk_250_i); + + --see_dlm_hb_i <= '0' ; + --if rx_data_from_serdes_i = '1' & K277 then + --see_dlm_hb_i <= '1'; + --end if; + --see_dlm_hb_buf_i <= see_dlm_hb_i; + + --see_dlm_lb_aggr_i <= '0'; + --if rx_data_from_serdes_i = '1' & K277 then + --see_dlm_lb_aggr_i <= OR_ALL(see_dlm_lb_buf_i); + --end if; + + + + --if rst_i = '1' then + --stat_sync_dlm_counter_i <= (others => '0'); + --stat_sync_dlm_inv_counter_i <= (others => '0'); + --saw_lb_v := '0'; + --saw_hb_v := '0'; + + --else + --if see_dlm_hb_buf_i = '1' and saw_lb_v = '1' then + --stat_sync_dlm_counter_i <= stat_sync_dlm_counter_i + 1; + --end if; + + --if see_dlm_lb_aggr_i = '1' and saw_hb_v = '1' then + --stat_sync_dlm_inv_counter_i <= stat_sync_dlm_inv_counter_i + 1; + --end if; + + --saw_lb_v := see_dlm_lb_aggr_i; + --saw_hb_v := see_dlm_hb_buf_i; + --end if; + --end process; + + --see_dlm_lb_i(0) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(10, 3) else '0'; + --see_dlm_lb_i(1) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(14, 1) else '0'; + --see_dlm_lb_i(2) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(20, 1) else '0'; + --see_dlm_lb_i(3) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(20, 6) else '0'; + + --see_dlm_lb_i(4) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(22, 3) else '0'; + --see_dlm_lb_i(5) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(28, 2) else '0'; + --see_dlm_lb_i(6) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(28, 5) else '0'; + --see_dlm_lb_i(7) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(06, 2) else '0'; + + --see_dlm_lb_i(8) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(14, 6) else '0'; + --see_dlm_lb_i(9) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 3, 1) else '0'; + --see_dlm_lb_i(10)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(11, 2) else '0'; + --see_dlm_lb_i(11)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(17, 2) else '0'; + + --see_dlm_lb_i(12)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(25, 3) else '0'; + --see_dlm_lb_i(13)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(17, 5) else '0'; + --see_dlm_lb_i(14)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 3, 6) else '0'; + --see_dlm_lb_i(15)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 5, 3) else '0'; + + --see_dlm_lb_buf_i <= see_dlm_lb_i when rising_edge(rclk_250_i); --- DEBUG_OUT(127 downto 108) <= "00" & tx_data_debug_i(17 downto 0); --- DEBUG_OUT(147 downto 128) <= "00" & rx_data_debug_i(17 downto 0) when rising_edge(clk_125_local); - - -- STAT_OP REGISTER --- STAT_OP <= tx_data_i(15 downto 0) when CTRL_OP(9 downto 8) = "01" else --- rx_data_i(15 downto 0) when CTRL_OP(9 downto 8) = "10" else --- test_line_i; --- --- test_line_i <= test_line_i(14 downto 0) & test_line_i(15) when rising_edge(clk_125_local); --- STAT_OP(6 downto 0) <= tx_data_to_serdes_i(6 downto 0); --- STAT_OP( 7) <= low_level_rx_see_dlm0; --- STAT_OP( 8) <= clk_125_local; --- STAT_OP( 9) <= rclk_250_i; --- STAT_OP(10) <= rclk_125_i; --- STAT_OP(11) <= clk_tx_full_i; --- STAT_OP(12) <= clk_tx_half_i; --- STAT_OP(13) <= low_level_tx_see_dlm0; end generate; end architecture; \ No newline at end of file diff --git a/cbmnet/code/cbmnet_phy_pkg.vhd b/cbmnet/code/cbmnet_phy_pkg.vhd old mode 100644 new mode 100755 index 4a2ef6e..a767558 --- a/cbmnet/code/cbmnet_phy_pkg.vhd +++ b/cbmnet/code/cbmnet_phy_pkg.vhd @@ -181,7 +181,18 @@ package cbmnet_phy_pkg is ); end component; + + function EBTB_D_ENCODE( + constant x : integer range 0 to 31; + constant y : integer range 0 to 7 + ) return std_logic_vector; + end package cbmnet_phy_pkg; package body cbmnet_phy_pkg is + function EBTB_D_ENCODE(constant x : integer range 0 to 31; constant y : integer range 0 to 7) return std_logic_vector + is begin + return STD_LOGIC_VECTOR(TO_UNSIGNED(x, 5)) & STD_LOGIC_VECTOR(TO_UNSIGNED(y, 3)); + end EBTB_D_ENCODE; + end package body; \ No newline at end of file diff --git a/cbmnet/code/cbmnet_phy_tx_gear.vhd b/cbmnet/code/cbmnet_phy_tx_gear.vhd index a552f69..7d7df39 100644 --- a/cbmnet/code/cbmnet_phy_tx_gear.vhd +++ b/cbmnet/code/cbmnet_phy_tx_gear.vhd @@ -40,8 +40,9 @@ architecture CBMNET_PHY_TX_GEAR_ARCH of CBMNET_PHY_TX_GEAR is signal data_in_buf125_i : std_logic_vector(17 downto 0); signal data_in_buf250_i : std_logic_vector(17 downto 0); + signal data_in_buf250_0_i : std_logic_vector(17 downto 0); - signal low_data_i : std_logic_vector(8 downto 0); + signal delay_data_i : std_logic_vector(8 downto 0); signal clk_125_xfer_i : std_logic := '0'; signal clk_125_xfer_buf_i : std_logic := '0'; @@ -56,7 +57,9 @@ begin delay_counter_i <= TO_UNSIGNED(0,16); end if; - data_in_buf250_i <= data_in_buf125_i; + data_in_buf250_0_i <= data_in_buf250_i; + data_in_buf250_i <= data_in_buf250_0_i; + clk_125_xfer_buf_i <= clk_125_xfer_i; clk_125_xfer_del_i <= clk_125_xfer_buf_i; @@ -66,18 +69,18 @@ begin when FSM_HIGH => CLK_125_OUT <= '1'; - low_data_i <= data_in_buf250_i(17) & data_in_buf250_i(15 downto 8); - DATA_OUT <= data_in_buf250_i(16) & data_in_buf250_i( 7 downto 0); + delay_data_i <= data_in_buf250_i(17) & data_in_buf250_i(15 downto 8); + DATA_OUT <= data_in_buf250_i(16) & data_in_buf250_i( 7 downto 0); fsm_i <= FSM_LOW; - if clk_125_xfer_buf_i /= clk_125_xfer_del_i and ALLOW_RELOCK_IN = '1' then - fsm_i <= FSM_HIGH; - delay_counter_i <= delay_counter_i + 1; - end if; +-- if clk_125_xfer_buf_i /= clk_125_xfer_del_i and ALLOW_RELOCK_IN = '1' then +-- fsm_i <= FSM_HIGH; +-- delay_counter_i <= delay_counter_i + 1; +-- end if; when others => - DATA_OUT <= low_data_i; + DATA_OUT <= delay_data_i; fsm_i <= FSM_HIGH; end case; end process; @@ -91,5 +94,5 @@ begin clk_125_xfer_i <= not clk_125_xfer_i; end process; - DEBUG_OUT <= x"0000" & STD_LOGIC_VECTOR( delay_counter_i ); + DEBUG_OUT <= (others => '0'); -- x"0000" & STD_LOGIC_VECTOR( delay_counter_i ); end architecture CBMNET_PHY_TX_GEAR_ARCH; \ No newline at end of file diff --git a/cbmnet/compile_constraints.pl b/cbmnet/compile_constraints.pl index 276744b..04aafbc 100755 --- a/cbmnet/compile_constraints.pl +++ b/cbmnet/compile_constraints.pl @@ -28,6 +28,7 @@ unless(-e $workdir) { chdir($workdir); system ("$back/../../base/linkdesignfiles.sh '$back'"); symlink "$back/../cores/cbmnet_sfp1.txt", 'cbmnet_sfp1.txt'; +symlink "$back/../cores/cbmnet_sfp1_slow.txt", 'cbmnet_sfp1_slow.txt'; chdir($script_dir); diff --git a/cbmnet/compile_periph_frankfurt.pl b/cbmnet/compile_periph_frankfurt.pl index d6ae4cf..f311bcc 100755 --- a/cbmnet/compile_periph_frankfurt.pl +++ b/cbmnet/compile_periph_frankfurt.pl @@ -15,12 +15,12 @@ my $CbmNetPath = "../../cbmnet"; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; -my $lattice_path = '/d/jspc29/lattice/diamond/2.2_x64/'; +#my $lattice_path = '/d/jspc29/lattice/diamond/2.2_x64/'; #my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; -my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/'; +#my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/'; -#my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/'; -#my $lattice_path = '/d/jspc29/lattice/diamond/3.1/'; +my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/'; +my $lattice_path = '/d/jspc29/lattice/diamond/3.1/'; ################################################################################### my $btype = 'slave'; @@ -113,23 +113,38 @@ $c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $ execute($c); -system("rm $TOPNAME.ncd"); - -#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; -#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|; -$c=qq|$lattice_path/bin/lin/mpartrce -p "../$TOPNAME.p2t" -f "../$TOPNAME.p3t" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; -execute($c); - -#Make Bitfile -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; + system("rm $TOPNAME.ncd"); + +# #$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +# #$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|; +# $c=qq|$lattice_path/bin/lin/mpartrce -p "../$TOPNAME.p2t" -f "../$TOPNAME.p3t" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; +# execute($c); +# +# #Make Bitfile +# $c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +# execute($c); +# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +# execute($c); +# +# +# # IOR IO Timing Report +# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +# execute($c); +# +# # TWR Timing Report +# $c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +# execute($c); +# +# $c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +# execute($c); + +#$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; +# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 4 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|; execute($c); - - # IOR IO Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); +# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +# execute($c); # TWR Timing Report $c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; @@ -138,6 +153,12 @@ execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; +# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); chdir ".."; diff --git a/cbmnet/test/info.pl b/cbmnet/test/info.pl index c6d4019..640cdac 100755 --- a/cbmnet/test/info.pl +++ b/cbmnet/test/info.pl @@ -127,6 +127,38 @@ sub show8b10bWord { show8b10b( ($data >> 0) & 0xff, ($data >> 16) & 1 ); } +sub cbmnet_definitions { + my $inp = shift; + my %cbmnet_defs = ( + "K.28.3 D.14.1", "SOP0 ", "K.27.7 D.03.1", "DLM9 ", + "K.28.3 D.20.1", "SOP1 ", "K.27.7 D.11.2", "DLM10 ", + "K.28.3 D.20.6", "SOP2 ", "K.27.7 D.17.2", "DLM11 ", + "K.28.3 D.22.3", "SOP3 ", "K.27.7 D.25.3", "DLM12 ", + "K.28.3 D.28.2", "SOSC0 ", "K.27.7 D.17.5", "DLM13 ", + "K.28.3 D.28.5", "SOSC1 ", "K.27.7 D.03.6", "DLM14 ", + "K.28.3 D.06.2", "SOSC2 ", "K.27.7 D.05.3", "DLM15 ", + "K.28.3 D.14.6", "SOSC3 ", "K.28.7 D.10.3", "NACK0 ", + "K.28.3 D.03.1", "ACK0 ", "K.28.7 D.14.1", "NACK1 ", + "K.28.3 D.11.2", "ACK1 ", "K.28.7 D.20.1", "NACK2 ", + "K.28.3 D.17.2", "ACK2 ", "K.28.7 D.20.6", "NACK3 ", + "K.28.3 D.25.3", "ACK3 ", "K.28.7 D.22.3", "NACK00 ", + "K.28.3 D.17.5", "ACK00 ", "K.28.7 D.28.2", "NACK01 ", + "K.28.3 D.03.6", "ACK01 ", "K.28.7 D.28.5", "NACK02 ", + "K.28.3 D.05.3", "ACK02 ", "K.28.7 D.06.2", "NACK03 ", + "K.28.3 D.10.3", "ACK03 ", "K.28.7 D.03.1", "EOP_ERR ", + "K.27.7 D.10.3", "DLM0 ", "K.28.7 D.11.2", "EOP_C ", + "K.27.7 D.14.1", "DLM1 ", "K.28.7 D.17.2", "EOP ", + "K.27.7 D.20.1", "DLM2 ", "K.28.7 D.17.5", "RETRANS ", + "K.27.7 D.20.6", "DLM3 ", "K.28.7 D.03.6", "IDLESYNC", + "K.27.7 D.22.3", "DLM4 ", "K.28.7 D.05.3", "INIT ", + "K.27.7 D.28.2", "DLM5 ", "K.29.7 K.28.3", "ACK_INIT", + "K.27.7 D.28.5", "DLM6 ", "K.28.7 D.14.6", "SLAVE1 ", + "K.27.7 D.06.2", "DLM7 ", "K.28.7 D.25.3", "SLAVE2 ", + "K.27.7 D.14.6", "DLM8 ", "K.30.7 K.28.3", "SLAVE3 ", + "D.00.0 K.28.4", "READY0 ", "D.00.0 K.28.7", "READY1 ", + "D.00.0 K.28.5", "ALIGN "); + return exists $cbmnet_defs{$inp} ? $cbmnet_defs{$inp} : " "; +} my @old_results; my $first_one = 1; @@ -141,7 +173,8 @@ while (1) { my $len = $def->[2]; my $text = sprintf($len == 1 ? "%x" : "0x%0" . (ceil(($len+3) / 4.0)) . "x", ($reg >> $idx) & ((1 << $len) - 1)); if ($len == 18) { - $text .= " " . show8b10bWord(($reg >> $idx) & ((1 << $len) - 1)); + my $ebtb = show8b10bWord(($reg >> $idx) & ((1 << $len) - 1)); + $text .= " " . $ebtb . ": " . cbmnet_definitions($ebtb); } push @slices, $text; } @@ -167,8 +200,8 @@ while (1) { } @old_results = @results; - - + +print `trbcmd rm 0x8001 0xa010 7 0`; sleep 1; print $first_one ? `clear` : chr(27) . "[1;1H"; $first_one = 0; diff --git a/cbmnet/trb3_periph_cbmnet.vhd b/cbmnet/trb3_periph_cbmnet.vhd index 78e5513..0d44a12 100755 --- a/cbmnet/trb3_periph_cbmnet.vhd +++ b/cbmnet/trb3_periph_cbmnet.vhd @@ -302,7 +302,7 @@ architecture trb3_periph_arch of trb3_periph_cbmnet is signal dummy : std_logic; - type SEND_FSM_T is (START, SEND_HEADER, SEND_LENGTH, SEND_DATA, SEND_FOOTER, AFTER_SEND_WAIT); + type SEND_FSM_T is (START, SEND_HEADER, SEND_PACK_NUM, SEND_LENGTH, SEND_DATA, SEND_FOOTER, AFTER_SEND_WAIT); signal send_fsm_i : SEND_FSM_T; signal send_length_i : unsigned(4 downto 0); signal send_num_pack_counter_i : unsigned(15 downto 0); @@ -565,12 +565,16 @@ begin if cbm_link_active='1' and cbm_data2send_stop = "0" then send_fsm_i <= SEND_HEADER; send_num_pack_counter_i <= send_num_pack_counter_i + 1; - send_length_i <= "1" & send_num_pack_counter_i(3 downto 0); + send_length_i <= "0" & send_num_pack_counter_i(3 downto 0); end if; when SEND_HEADER => cbm_data2send <= x"f123"; cbm_data2send_start <= "1"; + send_fsm_i <= SEND_PACK_NUM; + + when SEND_PACK_NUM => + cbm_data2send <= send_num_pack_counter_i; send_fsm_i <= SEND_LENGTH; when SEND_LENGTH => @@ -595,7 +599,7 @@ begin when AFTER_SEND_WAIT => send_wait_counter_i <= STD_LOGIC_VECTOR( UNSIGNED(send_wait_counter_i) + 1 ); - if send_wait_counter_i = send_wait_threshold_i then + if send_wait_counter_i >= send_wait_threshold_i then send_fsm_i <= START; end if; diff --git a/cbmnet/trb3_periph_cbmnet_constraints.lpf b/cbmnet/trb3_periph_cbmnet_constraints.lpf old mode 100644 new mode 100755 index e4d52a5..063fbd6 --- a/cbmnet/trb3_periph_cbmnet_constraints.lpf +++ b/cbmnet/trb3_periph_cbmnet_constraints.lpf @@ -25,36 +25,33 @@ USE PRIMARY NET "CLK_GPLL_LEFT"; GSR_NET NET "GSR_N"; -################################################################ -# Locate Serdes and media interfaces -################################################################# -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; -REGION "MEDIA_UPLINK" "R102C95D" 13 25; +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ; +REGION "MEDIA_UPLINK" "R102C95D" 13 25 DEVSIZE; LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; - LOCATE COMP "THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSB" ; +#LOCATE COMP "THE_CBM_PHY/GEN_EASY_SERDES/THE_EASY_SERDES/PCSD_INST" SITE "PCSB" ; REGION "CBM_PHY" "R102C49D" 13 25; LOCATE UGROUP "THE_CBM_PHY/cbmnet_phy_group" REGION "CBM_PHY"; - -REGION "CBM_PHY_RX_GEAR" "R102C50D" 13 15; -LOCATE UGROUP "THE_CBM_PHY/THE_RX_GEAR/cbmnet_phy_rx_gear" REGION "CBM_PHY_RX_GEAR"; - -REGION "CBM_PHY_TX_GEAR" "R102C50D" 13 15; -LOCATE UGROUP "THE_CBM_PHY/THE_TX_GEAR/cbmnet_phy_tx_gear" REGION "CBM_PHY_TX_GEAR"; - - +REGION "CBM_PHY_RX_GEAR" "R102C50D" 13 15 DEVSIZE; +LOCATE UGROUP "THE_CBM_PHY/THE_RX_GEAR/cbmnet_phy_rx_gear" REGION "CBM_PHY_RX_GEAR" ; +REGION "CBM_PHY_TX_GEAR" "R102C50D" 13 15 DEVSIZE; +LOCATE UGROUP "THE_CBM_PHY/THE_TX_GEAR/cbmnet_phy_tx_gear" REGION "CBM_PHY_TX_GEAR" ; ################################################################# # Relax some of the timing constraints ################################################################# -MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; -FREQUENCY NET "rclk_125_i" 125.000000 MHz ; -FREQUENCY NET "phy_stat_op[11]" 250.000000 MHz ; -FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ; -FREQUENCY NET "clk_200_i" 200.000000 MHz ; -FREQUENCY NET "clk_100_i_c" 100.000000 MHz ; -FREQUENCY NET "CLK_RX_FULL_OUT" 250.000000 MHz ; +FREQUENCY PORT "CLK_GPLL_LEFT" 200 MHz ; +FREQUENCY NET "clk_200_i" 200 MHz ; +FREQUENCY NET "clk_100_i_c" 100 MHz ; +FREQUENCY NET "CLK_RX_FULL_OUT" 250 MHz ; +FREQUENCY NET "THE_CBM_PHY/clk_tx_full_i" 250 MHz ; +FREQUENCY NET "THE_MEDIA_UPLINK/un1_THE_MEDIA_UPLINK_2_c" 100 MHz ; +FREQUENCY NET "THE_CBM_PHY/THE_RX_GEAR/clk_125_i_i" 125 MHz ; +FREQUENCY NET "rclk_125_i" 125 MHz ; + +DEFINE BUS "rx_data" NET "THE_CBM_PHY/rx_data_from_serdes_i[0]" NET "THE_CBM_PHY/rx_data_from_serdes_i[1]" NET "THE_CBM_PHY/rx_data_from_serdes_i[2]" NET "THE_CBM_PHY/rx_data_from_serdes_i[3]" NET "THE_CBM_PHY/rx_data_from_serdes_i[4]" NET "THE_CBM_PHY/rx_data_from_serdes_i[5]" NET "THE_CBM_PHY/rx_data_from_serdes_i[6]" NET "THE_CBM_PHY/rx_data_from_serdes_i[7]" NET "THE_CBM_PHY/rx_data_from_serdes_i[8]"; +DEFINE BUS "tx_data" NET "THE_CBM_PHY/tx_data_to_serdes_i[0]" NET "THE_CBM_PHY/tx_data_to_serdes_i[1]" NET "THE_CBM_PHY/tx_data_to_serdes_i[2]" NET "THE_CBM_PHY/tx_data_to_serdes_i[3]" NET "THE_CBM_PHY/tx_data_to_serdes_i[4]" NET "THE_CBM_PHY/tx_data_to_serdes_i[5]" NET "THE_CBM_PHY/tx_data_to_serdes_i[6]" NET "THE_CBM_PHY/tx_data_to_serdes_i[7]" NET "THE_CBM_PHY/tx_data_to_serdes_i[8]"; -MULTICYCLE FROM CLKNET "CLK_RX_FULL_OUT" TO CLKNET "rclk_125_i" 2.000000 X_DEST ; \ No newline at end of file +PRIORITIZE BUS "rx_data" 51; +PRIORITIZE BUS "tx_data" 50; \ No newline at end of file