From: hadeshyp Date: Wed, 27 Mar 2013 19:08:26 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=09deb70878d407a5eca04b02339f6cf681d75dc4;p=trb3.git *** empty log message *** --- diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index 007e426..2b914bb 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -133,6 +133,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" @@ -175,7 +176,6 @@ add_file -vhdl -lib "work" "./source/nx_trigger_generator.vhd" add_file -vhdl -lib "work" "./source/nx_trigger_handler.vhd" add_file -vhdl -lib "work" "./source/nx_timestamp_sim.vhd" -add_file -vhdl -lib "work" "./source/clock10MHz.vhd" # Needed by ADC9222 Entity add_file -vhdl -lib "work" "../base/cores/dqsinput.vhd" diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index f53a5a0..096f3a9 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -1,6 +1,6 @@ -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK RD_DURING_WR_PATHS ; +# BLOCK RESETPATHS ; +# BLOCK ASYNCPATHS ; +# BLOCK RD_DURING_WR_PATHS ; ################################################################# # Basic Settings @@ -14,12 +14,12 @@ BLOCK RD_DURING_WR_PATHS ; FREQUENCY PORT CLK_GPLL_LEFT 200 MHz; #Put the names of your DCO inputs here: - FREQUENCY PORT NX1_ADC_SC_CLK32_OUT 360 MHz; - FREQUENCY PORT NX2_ADC_SC_CLK32_OUT 360 MHz; + FREQUENCY PORT NX1_ADC_DCLK_IN 192 MHz; + FREQUENCY PORT NX2_ADC_DCLK_IN 192 MHz; #Change the next two lines to the clk_fast signal of the ADC - USE PRIMARY2EDGE NET "THE_ADC/clk_fast"; - USE PRIMARY NET "THE_ADC/clk_fast"; + USE PRIMARY2EDGE NET "nXyter_FEE_board_1/adc_ad9222_1/clk_fast"; + USE PRIMARY NET "nXyter_FEE_board_1/adc_ad9222_1/clk_fast"; USE PRIMARY NET "CLK_PCLK_LEFT"; USE PRIMARY NET "CLK_PCLK_LEFT_c";