From: Michael Traxler <M.Traxler@gsi.de>
Date: Mon, 15 Apr 2024 11:01:58 +0000 (+0200)
Subject: added new farich, mt
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0a02a7e4a7043d4714ffade2c0d828e8d2d35fce;p=daqtools.git

added new farich, mt
---

diff --git a/base/serials_farich_concentrator.db b/base/serials_farich_concentrator.db
index 76a9fc4..ca792ed 100644
--- a/base/serials_farich_concentrator.db
+++ b/base/serials_farich_concentrator.db
@@ -1,2 +1,4 @@
 # concentrator/combiner for FaRICH
    0010      0x6c00000c890ac828
+   0020      0x8000000c88a6ae28
+   
diff --git a/users/gsi_ee_trb84/db/addresses_farich.db b/users/gsi_ee_trb84/db/addresses_farich.db
index 39a1b48..8811172 100644
--- a/users/gsi_ee_trb84/db/addresses_farich.db
+++ b/users/gsi_ee_trb84/db/addresses_farich.db
@@ -195,3 +195,5 @@
 0x13c6      198     1
 0x13c7      199     1
 0x13c8      200     1
+
+
diff --git a/users/gsi_ee_trb84/db/addresses_farich_concentrator.db b/users/gsi_ee_trb84/db/addresses_farich_concentrator.db
index e75876d..73756bd 100644
--- a/users/gsi_ee_trb84/db/addresses_farich_concentrator.db
+++ b/users/gsi_ee_trb84/db/addresses_farich_concentrator.db
@@ -1,3 +1,4 @@
 # concentrator/combiner
 0x8500	   001   0
+0x8501	   002   0
 
diff --git a/users/gsi_ee_trb84/db/addresses_trb3.db b/users/gsi_ee_trb84/db/addresses_trb3.db
index 2c92e8c..b074eda 100644
--- a/users/gsi_ee_trb84/db/addresses_trb3.db
+++ b/users/gsi_ee_trb84/db/addresses_trb3.db
@@ -16,7 +16,7 @@
 0x8611 	    61 	   1
 0x1612 	    61	   2
 0x1613 	    61	   3
-0x8610      61 	   5
+0x861f      61 	   5
 
 #slave
 0x1130 	   113     0
diff --git a/users/gsi_ee_trb84/db/addresses_trb3sc.db b/users/gsi_ee_trb84/db/addresses_trb3sc.db
index e023203..50ca326 100644
--- a/users/gsi_ee_trb84/db/addresses_trb3sc.db
+++ b/users/gsi_ee_trb84/db/addresses_trb3sc.db
@@ -81,7 +81,7 @@
 0xa058      458     1
 0xa059      459     1
 0xa060      460     1
-0xa061      461     1
+#0xa061      461     1
 0xa062      462     1
 0xa063      463     1
 0xa064      464     1
@@ -387,7 +387,7 @@
 0x16ca   458   1
 0x16cb   459   1
 0x16cc   460   1
-0x16cd   461   1
+0xc001   461   1
 0x16ce   462   1
 0x16cf   463   1
 0x16d0   464   1
diff --git a/users/gsi_ee_trb84/db/register_configgbe.db b/users/gsi_ee_trb84/db/register_configgbe.db
index 4af226b..4c51d0e 100644
--- a/users/gsi_ee_trb84/db/register_configgbe.db
+++ b/users/gsi_ee_trb84/db/register_configgbe.db
@@ -16,6 +16,8 @@
    0x1692      0       0x8002          1            0        0xffffff         1      
    0x1504      0       0x8006          1            0        0xffffff         1      
    0x16ce      0       0x8007          1            0        0xffffff         1      
+   0x8501      0       0x8008          0            0        0xffffff         1      
+   0x2049      0       0x8009          1            0        0xffffff         1      
 #  0x8113      0       0x8001          1            0        0xffffff         1      
 #  0x8158      0       0x8002          1            0        0xffffff         1      
 #  0xa002      0       0x8003          0            0        0xffffff         1       0x2000
diff --git a/users/gsi_ee_trb84/db/register_configgbe_ip.db b/users/gsi_ee_trb84/db/register_configgbe_ip.db
index db434df..412e3ac 100644
--- a/users/gsi_ee_trb84/db/register_configgbe_ip.db
+++ b/users/gsi_ee_trb84/db/register_configgbe_ip.db
@@ -35,5 +35,7 @@
  0x1692    0    0xcb9e97c5    0x6045    0xc0a80009    50092     0xc350
  0x1504    0    0xcb9e97c5    0x6045    0xc0a80009    50093     0xc350
  0x16ce    0    0xcb9e97c5    0x6045    0xc0a80009    50094     0xc350
+# 0x8501    0    0xcb9e97c5    0x6045    0xc0a80009    50095     0xc350
+ 0x2049    0    0xcb9e97c5    0x6045    0xc0a80009    50049     0xc350
 # 0x8113	   0    0xcb9e97c5    0x6045    0xc0a80009    50113     0xc350
 # 0x8158	   0    0xcb9e97c5    0x6045    0xc0a80009    50158	0xc350
diff --git a/users/gsi_ee_trb84/db/register_configtdc.db b/users/gsi_ee_trb84/db/register_configtdc.db
index 95ff983..0721a13 100644
--- a/users/gsi_ee_trb84/db/register_configtdc.db
+++ b/users/gsi_ee_trb84/db/register_configtdc.db
@@ -19,7 +19,7 @@
 0xfe71		0   0x00000000	 0x00000000   0x00000000   0x00000000   0x00000000   0x00000000	# trb3sc padiwa 4Conn backplane
 #0xfe51		0   0x00000000	 0x00000000   0x00000000   0x00000000   0x00000000   0x00000000	# dirich
 0xfe57		0   0x00000000	 0x00000000   0x00000000   0x00000000   0x00000000   0x00000000	# dirich5s
-
+0xfe58		0   0x00000000	 0x00000000   0x00000000   0x00000000   0x00000000   0x00000000	# dirich5d
 
 
 #0xfe48		0   0x50003000	 0x80640064   0xffffffff   0xffffffff   0x00009018   0x00000000 # 32PinAddOn
@@ -31,6 +31,7 @@
 0xfe71		0   0x50003000	 0x80640064   0x00000000   0x00000000   0x00000078   0x00000000	# trb3sc padiwa 4Conn backplane
 #0xfe51		0   0x50003000	 0x00640064   0x00000000   0x00000000   0x00000078   0x00000000	# dirich
 0xfe57		0   0x50003000	 0x00640064   0x000000ff   0x00000000   0x00000010   0x00000000	# dirich5s
+0xfe58		0   0x50003000	 0x00640064   0x000000ff   0x00000000   0x00000010   0x00000000	# dirich5d
 
 
 
diff --git a/users/gsi_ee_trb84/first.C b/users/gsi_ee_trb84/first.C
index 9696fa7..e90606c 100644
--- a/users/gsi_ee_trb84/first.C
+++ b/users/gsi_ee_trb84/first.C
@@ -24,7 +24,7 @@ void first()
    // 4 - use common statistic for both rising and falling edge
    hadaq::TrbProcessor::SetDefaults(33, 2);
 
-   hadaq::TdcProcessor::SetTriggerDWindow(-5, 70);
+   hadaq::TdcProcessor::SetTriggerDWindow(-5, 90);
 //   hadaq::TdcProcessor::SetToTRange(30, 50, 80);
 
    // [min..max] range for TDC ids
@@ -33,6 +33,7 @@ void first()
 
    // [min..max] range for HUB ids
    hadaq::TrbProcessor::SetHUBRange(0x8000, 0x8FFF);
+   //hadaq::TrbProcessor::SetHUBRange(0xc000, 0xcfff);
 
    // Histogramming for ToT: first: nr. of bins, 2nd: TOT range
    hadaq::TdcProcessor::SetDefaults(600, 1000);
@@ -132,6 +133,7 @@ extern "C" void after_create(hadaq::HldProcessor* hld)
       // This gives a factor of 1.5625, so the calibration pulse has a length of
       // 31.25ns
       //tdc->SetToTRange(31.25, 40, 70);
+      tdc->SetToTRange(31.25, 30, 70);
 
       // in new dirich5s design the correct PLL is included, so no correction necessary!