From: hadeshyp Date: Tue, 12 Jan 2010 10:31:05 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~350 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0a97dbdd668d86c20e7cabb8de72f68ab65ec7c2;p=trbnet.git *** empty log message *** --- diff --git a/lattice/ecp2m/dll_in100_out100.lpc b/lattice/ecp2m/dll_in100_out100.lpc new file mode 100644 index 0000000..7cd4976 --- /dev/null +++ b/lattice/ecp2m/dll_in100_out100.lpc @@ -0,0 +1,39 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DLL +CoreRevision=3.4 +ModuleName=dll_in100_out100 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=07/06/2009 +Time=16:50:52 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +dlltype=Clock Injection Delay Removal +fin=100 +clkos_div=1 +clkos_ph=0 +Mode=CLKOP +Freq=CLKI +Smiports=0 +RSTNport=0 +reset_en=0 +DCNTL=0 diff --git a/lattice/ecp2m/dll_in100_out100.vhd b/lattice/ecp2m/dll_in100_out100.vhd new file mode 100644 index 0000000..1f4e64b --- /dev/null +++ b/lattice/ecp2m/dll_in100_out100.vhd @@ -0,0 +1,133 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 3.4 +--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n dll_in100_out100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dll -dll_type cid -fin 100 -clkos_div 1 -fb_mode 0 -e + +-- Mon Jul 6 16:50:53 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity dll_in100_out100 is + port ( + clk: in std_logic; + aluhold: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic); + attribute dont_touch : string; + attribute dont_touch of dll_in100_out100 : entity is "true"; +end dll_in100_out100; + +architecture Structure of dll_in100_out100 is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal clkos_t: std_logic; + signal scuba_vhi: std_logic; + signal clkop_t: std_logic; + signal clk_t: std_logic; + + -- local component declarations + component CIDDLLA + -- synopsys translate_off + generic (ALU_INIT_CNTVAL : in Integer; + ALU_UNLOCK_CNT : in Integer; ALU_LOCK_CNT : in Integer; + GSR : in String; CLKOS_DIV : in Integer; + CLKI_DIV : in Integer; CLKOS_FPHASE : in Integer; + CLKOS_PHASE : in Integer; CLKOP_PHASE : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; + RSTN: in std_logic; ALUHOLD: in std_logic; + SMIADDR9: in std_logic; SMIADDR8: in std_logic; + SMIADDR7: in std_logic; SMIADDR6: in std_logic; + SMIADDR5: in std_logic; SMIADDR4: in std_logic; + SMIADDR3: in std_logic; SMIADDR2: in std_logic; + SMIADDR1: in std_logic; SMIADDR0: in std_logic; + SMIRD: in std_logic; SMIWR: in std_logic; + SMICLK: in std_logic; SMIWDATA: in std_logic; + SMIRSTN: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; LOCK: out std_logic; + SMIRDATA: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute GSR : string; + attribute CLKFB_PDEL : string; + attribute CLKI_PDEL : string; + attribute ALU_INIT_CNTVAL : string; + attribute ALU_UNLOCK_CNT : string; + attribute ALU_LOCK_CNT : string; + attribute CLKI_DIV : string; + attribute CLKOS_DIV : string; + attribute CLKOS_FPHASE : string; + attribute CLKOS_PHASE : string; + attribute CLKOP_PHASE : string; + attribute FREQUENCY_PIN_CLKOS of dll_in100_out100_0_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKOP of dll_in100_out100_0_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKI of dll_in100_out100_0_0 : label is "100.000000"; + attribute GSR of dll_in100_out100_0_0 : label is "DISABLED"; + attribute CLKFB_PDEL of dll_in100_out100_0_0 : label is "DEL0"; + attribute CLKI_PDEL of dll_in100_out100_0_0 : label is "DEL0"; + attribute ALU_INIT_CNTVAL of dll_in100_out100_0_0 : label is "0"; + attribute ALU_UNLOCK_CNT of dll_in100_out100_0_0 : label is "3"; + attribute ALU_LOCK_CNT of dll_in100_out100_0_0 : label is "3"; + attribute CLKI_DIV of dll_in100_out100_0_0 : label is "1"; + attribute CLKOS_DIV of dll_in100_out100_0_0 : label is "1"; + attribute CLKOS_FPHASE of dll_in100_out100_0_0 : label is "0"; + attribute CLKOS_PHASE of dll_in100_out100_0_0 : label is "270"; + attribute CLKOP_PHASE of dll_in100_out100_0_0 : label is "270"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + dll_in100_out100_0_0: CIDDLLA + -- synopsys translate_off + generic map (GSR=> "DISABLED", ALU_INIT_CNTVAL=> 0, + ALU_UNLOCK_CNT=> 3, ALU_LOCK_CNT=> 3, CLKI_DIV=> 1, CLKOS_DIV=> 1, + CLKOS_FPHASE=> 0, CLKOS_PHASE=> 270, CLKOP_PHASE=> 270) + -- synopsys translate_on + port map (CLKI=>clk_t, CLKFB=>clkop_t, RSTN=>scuba_vhi, + ALUHOLD=>aluhold, SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, + SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, + SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, + SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, + SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, + SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, + SMIRSTN=>scuba_vlo, CLKOP=>clkop_t, CLKOS=>clkos_t, + LOCK=>lock, SMIRDATA=>open); + + clkos <= clkos_t; + clkop <= clkop_t; + clk_t <= clk; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of dll_in100_out100 is + for Structure + for all:CIDDLLA use entity ecp2m.CIDDLLA(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/dll_in200_out100.lpc b/lattice/ecp2m/dll_in200_out100.lpc new file mode 100644 index 0000000..4225c05 --- /dev/null +++ b/lattice/ecp2m/dll_in200_out100.lpc @@ -0,0 +1,39 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DLL +CoreRevision=3.5 +ModuleName=dll_in200_out100 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=12/18/2009 +Time=17:54:29 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +dlltype=Clock Injection Delay Removal +fin=200 +clkos_div=2 +clkos_ph=0 +Mode=CLKOP +Freq=CLKI +Smiports=0 +RSTNport=0 +reset_en=0 +DCNTL=0 diff --git a/lattice/ecp2m/dll_in200_out100.vhd b/lattice/ecp2m/dll_in200_out100.vhd new file mode 100644 index 0000000..0734b22 --- /dev/null +++ b/lattice/ecp2m/dll_in200_out100.vhd @@ -0,0 +1,133 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 3.5 +--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n dll_in200_out100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dll -dll_type cid -fin 200 -clkos_div 2 -fb_mode 0 -e + +-- Fri Dec 18 17:54:30 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity dll_in200_out100 is + port ( + clk: in std_logic; + aluhold: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of dll_in200_out100 : entity is true; +end dll_in200_out100; + +architecture Structure of dll_in200_out100 is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal clkos_t: std_logic; + signal scuba_vhi: std_logic; + signal clkop_t: std_logic; + signal clk_t: std_logic; + + -- local component declarations + component CIDDLLA + -- synopsys translate_off + generic (ALU_INIT_CNTVAL : in Integer; + ALU_UNLOCK_CNT : in Integer; ALU_LOCK_CNT : in Integer; + GSR : in String; CLKOS_DIV : in Integer; + CLKI_DIV : in Integer; CLKOS_FPHASE : in Integer; + CLKOS_PHASE : in Integer; CLKOP_PHASE : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; + RSTN: in std_logic; ALUHOLD: in std_logic; + SMIADDR9: in std_logic; SMIADDR8: in std_logic; + SMIADDR7: in std_logic; SMIADDR6: in std_logic; + SMIADDR5: in std_logic; SMIADDR4: in std_logic; + SMIADDR3: in std_logic; SMIADDR2: in std_logic; + SMIADDR1: in std_logic; SMIADDR0: in std_logic; + SMIRD: in std_logic; SMIWR: in std_logic; + SMICLK: in std_logic; SMIWDATA: in std_logic; + SMIRSTN: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; LOCK: out std_logic; + SMIRDATA: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute GSR : string; + attribute CLKFB_PDEL : string; + attribute CLKI_PDEL : string; + attribute ALU_INIT_CNTVAL : string; + attribute ALU_UNLOCK_CNT : string; + attribute ALU_LOCK_CNT : string; + attribute CLKI_DIV : string; + attribute CLKOS_DIV : string; + attribute CLKOS_FPHASE : string; + attribute CLKOS_PHASE : string; + attribute CLKOP_PHASE : string; + attribute FREQUENCY_PIN_CLKOS of dll_in200_out100_0_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKOP of dll_in200_out100_0_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKI of dll_in200_out100_0_0 : label is "200.000000"; + attribute GSR of dll_in200_out100_0_0 : label is "DISABLED"; + attribute CLKFB_PDEL of dll_in200_out100_0_0 : label is "DEL0"; + attribute CLKI_PDEL of dll_in200_out100_0_0 : label is "DEL0"; + attribute ALU_INIT_CNTVAL of dll_in200_out100_0_0 : label is "0"; + attribute ALU_UNLOCK_CNT of dll_in200_out100_0_0 : label is "3"; + attribute ALU_LOCK_CNT of dll_in200_out100_0_0 : label is "3"; + attribute CLKI_DIV of dll_in200_out100_0_0 : label is "1"; + attribute CLKOS_DIV of dll_in200_out100_0_0 : label is "2"; + attribute CLKOS_FPHASE of dll_in200_out100_0_0 : label is "0"; + attribute CLKOS_PHASE of dll_in200_out100_0_0 : label is "180"; + attribute CLKOP_PHASE of dll_in200_out100_0_0 : label is "180"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + dll_in200_out100_0_0: CIDDLLA + -- synopsys translate_off + generic map (GSR=> "DISABLED", ALU_INIT_CNTVAL=> 0, + ALU_UNLOCK_CNT=> 3, ALU_LOCK_CNT=> 3, CLKI_DIV=> 1, CLKOS_DIV=> 2, + CLKOS_FPHASE=> 0, CLKOS_PHASE=> 180, CLKOP_PHASE=> 180) + -- synopsys translate_on + port map (CLKI=>clk_t, CLKFB=>clkop_t, RSTN=>scuba_vhi, + ALUHOLD=>aluhold, SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, + SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, + SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, + SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, + SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, + SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, + SMIRSTN=>scuba_vlo, CLKOP=>clkop_t, CLKOS=>clkos_t, + LOCK=>lock, SMIRDATA=>open); + + clkos <= clkos_t; + clkop <= clkop_t; + clk_t <= clk; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of dll_in200_out100 is + for Structure + for all:CIDDLLA use entity ecp2m.CIDDLLA(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/fifo_sbuf.lpc b/lattice/ecp2m/fifo_sbuf.lpc new file mode 100644 index 0000000..b842767 --- /dev/null +++ b/lattice/ecp2m/fifo_sbuf.lpc @@ -0,0 +1,44 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=4.7 +ModuleName=fifo_sbuf +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=12/14/2009 +Time=14:20:53 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=LUT Based +Depth=8 +Width=19 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=5 +PfDeassert=506 +RDataCount=0 +EnECC=0 diff --git a/lattice/ecp2m/fifo_sbuf.vhd b/lattice/ecp2m/fifo_sbuf.vhd new file mode 100644 index 0000000..fa33c9c --- /dev/null +++ b/lattice/ecp2m/fifo_sbuf.vhd @@ -0,0 +1,696 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 4.7 +--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 8 -width 19 -depth 8 -no_enable -pe -1 -pf 5 -e + +-- Mon Dec 14 14:20:53 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_sbuf is + port ( + Data: in std_logic_vector(18 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(18 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_sbuf; + +architecture Structure of fifo_sbuf is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal cnt_con_inv: std_logic; + signal r_nw_inv: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co1: std_logic; + signal cnt_con: std_logic; + signal co0: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal wren_i: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co1_1: std_logic; + signal wcount_3: std_logic; + signal co0_3: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co1_2: std_logic; + signal rcount_3: std_logic; + signal co0_4: std_logic; + signal cmp_ci_2: std_logic; + signal fcnt_en_inv: std_logic; + signal r_nw: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_5: std_logic; + signal scuba_vhi: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal af_d: std_logic; + signal af_d_c: std_logic; + signal rdataout18: std_logic; + signal rdataout17: std_logic; + signal rdataout16: std_logic; + signal rdataout15: std_logic; + signal rdataout14: std_logic; + signal rdataout13: std_logic; + signal rdataout12: std_logic; + signal rdataout11: std_logic; + signal rdataout10: std_logic; + signal rdataout9: std_logic; + signal rdataout8: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rcount_2: std_logic; + signal rcount_1: std_logic; + signal rcount_0: std_logic; + signal dec0_wre3: std_logic; + signal scuba_vlo: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal wcount_0: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4A + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + attribute initval : string; + attribute GSR : string; + attribute initval of LUT4_2 : label is "0x3232"; + attribute initval of LUT4_1 : label is "0x3232"; + attribute initval of LUT4_0 : label is "0x8000"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x8000") + -- synopsys translate_on + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_29: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_27: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_26: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_25: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_24: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_23: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_22: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_21: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_20: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_19: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(0)); + + FF_18: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(1)); + + FF_17: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(2)); + + FF_16: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(3)); + + FF_15: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(4)); + + FF_14: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(5)); + + FF_13: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(6)); + + FF_12: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(7)); + + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(8)); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(9)); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(10)); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(11)); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(12)); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(13)); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout14, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(14)); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout15, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(15)); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout16, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(16)); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout17, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(17)); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout18, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(18)); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i_inv, + CI=>co0_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_1, + NC0=>iwcount_2, NC1=>iwcount_3); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_2, + NC0=>ircount_2, NC1=>ircount_3); + + af_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, + S1=>open); + + af_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv, B1=>r_nw, + CI=>cmp_ci_2, GE=>co0_5); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vhi, + B1=>scuba_vlo, CI=>co0_5, GE=>af_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); + + fifo_pfu_0_0: DPR16X4A + port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18), + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, + RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>scuba_vlo, + WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, + WAD3=>scuba_vlo, DO0=>rdataout16, DO1=>rdataout17, + DO2=>rdataout18, DO3=>open); + + fifo_pfu_0_1: DPR16X4A + port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), + DI3=>Data(15), WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, + RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>scuba_vlo, + WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, + WAD3=>scuba_vlo, DO0=>rdataout12, DO1=>rdataout13, + DO2=>rdataout14, DO3=>rdataout15); + + fifo_pfu_0_2: DPR16X4A + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, + RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>scuba_vlo, + WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, + WAD3=>scuba_vlo, DO0=>rdataout8, DO1=>rdataout9, + DO2=>rdataout10, DO3=>rdataout11); + + fifo_pfu_0_3: DPR16X4A + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>scuba_vlo, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>scuba_vlo, + DO0=>rdataout4, DO1=>rdataout5, DO2=>rdataout6, + DO3=>rdataout7); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_pfu_0_4: DPR16X4A + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>scuba_vlo, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>scuba_vlo, + DO0=>rdataout0, DO1=>rdataout1, DO2=>rdataout2, + DO3=>rdataout3); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_sbuf is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:ALEB2 use entity ecp2m.ALEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:CB2 use entity ecp2m.CB2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:DPR16X4A use entity ecp2m.DPR16X4A(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/pll_100.lpc b/lattice/ecp2m/pll_100.lpc new file mode 100644 index 0000000..e8818dc --- /dev/null +++ b/lattice/ecp2m/pll_100.lpc @@ -0,0 +1,56 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.0 +ModuleName=pll_100 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=07/06/2009 +Time=13:44:39 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=100 +OFrq=100.000000 +KFrq= +U_OFrq=100 +U_KFrq=50 +OP_Tol=0.0 +OK_Tol=0.0 +Div=1 +Mult=1 +Post=8 +SecD=2 +fb_mode=CLKOP +PhaseDuty=Static +DelayControl=AUTO_NO_DELAY +External=DISABLED +PCDR=0 +ClkOPBp=0 +EnCLKOS=0 +ClkOSBp=0 +Phase=0.0 +Duty=8 +DPD=50% Duty +EnCLKOK=0 +ClkOKBp=0 +ClkRst=0 diff --git a/lattice/ecp2m/pll_100.vhd b/lattice/ecp2m/pll_100.vhd new file mode 100644 index 0000000..3491af7 --- /dev/null +++ b/lattice/ecp2m/pll_100.vhd @@ -0,0 +1,120 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.0 +--/d/sugar/lattice/ispLever7.2/isptools/ispfpga/bin/lin/scuba -w -n pll_100 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -noclkos -noclkok -norst -e + +-- Mon Jul 6 13:45:53 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity pll_100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : string; + attribute dont_touch of pll_100 : entity is "true"; +end pll_100; + +architecture Structure of pll_100 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + signal CLK_t: std_logic; + + -- local component declarations + component VLO + port (Z: out std_logic); + end component; + component EPLLD + -- synopsys translate_off + generic (PLLCAP : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + DUTY : in Integer; PHASEADJ : in String; + PHASE_CNTL : in String; CLKOK_DIV : in Integer; + CLKFB_DIV : in Integer; CLKOP_DIV : in Integer; + CLKI_DIV : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; + CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + attribute PLLCAP : string; + attribute PLLTYPE : string; + attribute CLKOK_BYPASS : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute CLKOK_DIV : string; + attribute CLKOS_BYPASS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute CLKOP_BYPASS : string; + attribute PHASE_CNTL : string; + attribute FDEL : string; + attribute DUTY : string; + attribute PHASEADJ : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute CLKOP_DIV : string; + attribute CLKFB_DIV : string; + attribute CLKI_DIV : string; + attribute FIN : string; + attribute PLLCAP of PLLDInst_0 : label is "DISABLED"; + attribute PLLTYPE of PLLDInst_0 : label is "AUTO"; + attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000"; + attribute CLKOK_DIV of PLLDInst_0 : label is "2"; + attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "100.000000"; + attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC"; + attribute FDEL of PLLDInst_0 : label is "0"; + attribute DUTY of PLLDInst_0 : label is "8"; + attribute PHASEADJ of PLLDInst_0 : label is "0.0"; + attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "100.000000"; + attribute CLKOP_DIV of PLLDInst_0 : label is "8"; + attribute CLKFB_DIV of PLLDInst_0 : label is "1"; + attribute CLKI_DIV of PLLDInst_0 : label is "1"; + attribute FIN of PLLDInst_0 : label is "100.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLDInst_0: EPLLD + -- synopsys translate_off + generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED", + CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 8, + CLKFB_DIV=> 1, CLKI_DIV=> 1) + -- synopsys translate_on + port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, + LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; + CLK_t <= CLK; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of pll_100 is + for Structure + for all:VLO use entity ecp2m.VLO(V); end for; + for all:EPLLD use entity ecp2m.EPLLD(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/pll_in200_out100.lpc b/lattice/ecp2m/pll_in200_out100.lpc new file mode 100644 index 0000000..d1d54f2 --- /dev/null +++ b/lattice/ecp2m/pll_in200_out100.lpc @@ -0,0 +1,56 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.1 +ModuleName=pll_in200_out100 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=12/18/2009 +Time=18:26:57 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +OFrq=100.000000 +KFrq= +U_OFrq=100 +U_KFrq=50 +OP_Tol=0.0 +OK_Tol=0.0 +Div=2 +Mult=1 +Post=8 +SecD=2 +fb_mode=CLKOP +PhaseDuty=Static +DelayControl=AUTO_NO_DELAY +External=DISABLED +PCDR=0 +ClkOPBp=0 +EnCLKOS=0 +ClkOSBp=0 +Phase=0.0 +Duty=8 +DPD=50% Duty +EnCLKOK=0 +ClkOKBp=0 +ClkRst=0 diff --git a/lattice/ecp2m/pll_in200_out100.vhd b/lattice/ecp2m/pll_in200_out100.vhd new file mode 100644 index 0000000..65def48 --- /dev/null +++ b/lattice/ecp2m/pll_in200_out100.vhd @@ -0,0 +1,120 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 5.1 +--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 200 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -noclkos -noclkok -norst -e + +-- Fri Dec 18 18:26:57 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity pll_in200_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in200_out100 : entity is true; +end pll_in200_out100; + +architecture Structure of pll_in200_out100 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + signal CLK_t: std_logic; + + -- local component declarations + component VLO + port (Z: out std_logic); + end component; + component EPLLD + -- synopsys translate_off + generic (PLLCAP : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + DUTY : in Integer; PHASEADJ : in String; + PHASE_CNTL : in String; CLKOK_DIV : in Integer; + CLKFB_DIV : in Integer; CLKOP_DIV : in Integer; + CLKI_DIV : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; + CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + attribute PLLCAP : string; + attribute PLLTYPE : string; + attribute CLKOK_BYPASS : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute CLKOK_DIV : string; + attribute CLKOS_BYPASS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute CLKOP_BYPASS : string; + attribute PHASE_CNTL : string; + attribute FDEL : string; + attribute DUTY : string; + attribute PHASEADJ : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute CLKOP_DIV : string; + attribute CLKFB_DIV : string; + attribute CLKI_DIV : string; + attribute FIN : string; + attribute PLLCAP of PLLDInst_0 : label is "DISABLED"; + attribute PLLTYPE of PLLDInst_0 : label is "AUTO"; + attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000"; + attribute CLKOK_DIV of PLLDInst_0 : label is "2"; + attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "100.000000"; + attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC"; + attribute FDEL of PLLDInst_0 : label is "0"; + attribute DUTY of PLLDInst_0 : label is "8"; + attribute PHASEADJ of PLLDInst_0 : label is "0.0"; + attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "200.000000"; + attribute CLKOP_DIV of PLLDInst_0 : label is "8"; + attribute CLKFB_DIV of PLLDInst_0 : label is "1"; + attribute CLKI_DIV of PLLDInst_0 : label is "2"; + attribute FIN of PLLDInst_0 : label is "200.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLDInst_0: EPLLD + -- synopsys translate_off + generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED", + CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 8, + CLKFB_DIV=> 1, CLKI_DIV=> 2) + -- synopsys translate_on + port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, + LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; + CLK_t <= CLK; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of pll_in200_out100 is + for Structure + for all:VLO use entity ecp2m.VLO(V); end for; + for all:EPLLD use entity ecp2m.EPLLD(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/pll_in25_out100.lpc b/lattice/ecp2m/pll_in25_out100.lpc new file mode 100644 index 0000000..cabe73a --- /dev/null +++ b/lattice/ecp2m/pll_in25_out100.lpc @@ -0,0 +1,56 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=4.2 +ModuleName=pll_in25_out100 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=03/06/2009 +Time=17:43:28 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=25 +OFrq=100.000000 +KFrq= +U_OFrq=100 +U_KFrq=50 +OP_Tol=0.0 +OK_Tol=0.0 +Div=1 +Mult=4 +Post=8 +SecD=2 +fb_mode=CLKOP +PhaseDuty=Static +DelayControl=AUTO_NO_DELAY +External=AUTO +PCDR=0 +ClkOPBp=0 +EnCLKOS=0 +ClkOSBp=0 +Phase=0.0 +Duty=8 +DPD=50% Duty +EnCLKOK=0 +ClkOKBp=0 +ClkRst=0 diff --git a/media_interfaces/ecp2m_sfp/msg_file.log b/media_interfaces/ecp2m_sfp/msg_file.log index e518ed9..e446a6a 100644 --- a/media_interfaces/ecp2m_sfp/msg_file.log +++ b/media_interfaces/ecp2m_sfp/msg_file.log @@ -1,13 +1,14 @@ - Module Name: serdes_gbe_0_extclock + Module Name: serdes_gbe_0_200_ext Core Name: PCS - LPC file : serdes_gbe_0_extclock.lpc - Parameter File : serdes_gbe_0_extclock.pp - Command line: /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_extclock.pp + LPC file : serdes_gbe_0_200_ext.lpc + Parameter File : serdes_gbe_0_200_ext.pp + Command line: /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_200_ext.pp Return Value: + Module PCS has been generated in /home/hadaq/jan/cvs/trbnet/media_interfaces/ecp2m_sfp/. successfully! -/home/hadaq/.isplever_lin/ispcpld/bin/hdl2jhd -tfi -mod serdes_gbe_0_extclock -ext readme -out serdes_gbe_0_extclock -tpl serdes_gbe_0_extclock.tft serdes_gbe_0_extclock.vhd +/home/hadaq/.isplever_lin/ispcpld/bin/hdl2jhd -tfi -mod serdes_gbe_0_200_ext -ext readme -out serdes_gbe_0_200_ext -tpl serdes_gbe_0_200_ext.tft serdes_gbe_0_200_ext.vhd Done successfully! diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_0_200.lpc b/media_interfaces/ecp2m_sfp/serdes_gbe_0_200.lpc new file mode 100644 index 0000000..517d610 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_0_200.lpc @@ -0,0 +1,145 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=8.0 +ModuleName=serdes_gbe_0_200 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=12/21/2009 +Time=10:34:04 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Protocol=Quad +mode=Gigabit Ethernet +Channel0=SINGLE +Channel1=DISABLE +Channel2=DISABLE +Channel3=DISABLE +Rate0=None +Rate1=None +Rate2=None +Rate3=None +TxRefClk=CORE_TXREFCLK +RxRefClk=CORE_RXREFCLK +ClkRate=2 +ClkMult=10X +CalClkRate=200 +DataWidth=16 +FPGAClkRate=100 +TxRefClkCM=REFCLK +RxRefClk0CM=REFCLK +RxRefClk1CM=REFCLK +RxRefClk2CM=REFCLK +RxRefClk3CM=REFCLK +ClkRateH=1.0 +ClkMultH=10XH +CalClkRateH=200.0 +DataWidthH=8 +FPGAClkRateH=100.0 +VCh0=0 +VCh1=0 +VCh2=0 +VCh3=0 +PreCh0=DISABLE +PreCh1=DISABLE +PreCh2=DISABLE +PreCh3=DISABLE +TxCh0=50 +TxCh1=50 +TxCh2=50 +TxCh3=50 +EqCh0=DISABLE +EqCh1=DISABLE +EqCh2=DISABLE +EqCh3=DISABLE +RxTermCh0=50 +RxTermCh1=50 +RxTermCh2=50 +RxTermCh3=50 +RxCoupCh0=DC +RxCoupCh1=AC +RxCoupCh2=AC +RxCoupCh3=AC +Loss=0 +CDRLoss=0 +TxTerm=50 +TxCoup=DC +TxPllLoss=0 +TxInvCh0=NORMAL +TxInvCh1=NORMAL +TxInvCh2=NORMAL +TxInvCh3=NORMAL +RxInvCh0=NORMAL +RxInvCh1=NORMAL +RxInvCh2=NORMAL +RxInvCh3=NORMAL +RxModeCh0=NORMAL +RxModeCh1=NORMAL +RxModeCh2=NORMAL +RxModeCh3=NORMAL +Plus=1100000101 +Minus=0011111010 +Mask=1111111111 +Align=AUTO +CTCCh0=NORMAL +CTCCh1=NORMAL +CTCCh2=NORMAL +CTCCh3=NORMAL +CC_MATCH1=0000000000 +CC_MATCH2=0000000000 +CC_MATCH3=0110111100 +CC_MATCH4=0001010000 +MinIPG=3 +High=9 +Low=7 +CC_MATCH_MODE=MATCH_3_4 +RxDataCh0=FALSE +RxDataCh1=FALSE +RxDataCh2=FALSE +RxDataCh3=FALSE +AlignerCh0=FALSE +AlignerCh1=FALSE +AlignerCh2=FALSE +AlignerCh3=FALSE +DetectCh0=FALSE +DetectCh1=FALSE +DetectCh2=FALSE +DetectCh3=FALSE +ELSMCh0=FALSE +ELSMCh1=FALSE +ELSMCh2=FALSE +ELSMCh3=FALSE +_teidleCh0=FALSE +_teidleCh1=FALSE +_teidleCh2=FALSE +_teidleCh3=FALSE +Ports0=FALSE +rdoPorts0=Serial Loopback +Ports1=TRUE +Ports2=TRUE +Ports3=FALSE +Ports3_1=FALSE +Ports4=FALSE +_rst_gen=DISABLED +_rx_los_port0=Internal +_rx_los_port1=Internal +_rx_los_port2=Internal +_rx_los_port3=Internal diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_0_200.vhd b/media_interfaces/ecp2m_sfp/serdes_gbe_0_200.vhd new file mode 100644 index 0000000..2b8297a --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_0_200.vhd @@ -0,0 +1,2208 @@ + + +--synopsys translate_off + +library pcsc_work; +use pcsc_work.all; +library IEEE; +use IEEE.std_logic_1164.all; + +entity PCSC is +GENERIC( + CONFIG_FILE : String := "serdes_gbe_0_200.txt" + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); + +end PCSC; + +architecture PCSC_arch of PCSC is + +component PCSC_sim +GENERIC( + CONFIG_FILE : String + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); +end component; + +begin + +PCSC_sim_inst : PCSC_sim +generic map ( + CONFIG_FILE => CONFIG_FILE) +port map ( + HDINN0 => HDINN0, + HDINN1 => HDINN1, + HDINN2 => HDINN2, + HDINN3 => HDINN3, + HDINP0 => HDINP0, + HDINP1 => HDINP1, + HDINP2 => HDINP2, + HDINP3 => HDINP3, + REFCLKN => REFCLKN, + REFCLKP => REFCLKP, + CIN11 => CIN11, + CIN10 => CIN10, + CIN9 => CIN9, + CIN8 => CIN8, + CIN7 => CIN7, + CIN6 => CIN6, + CIN5 => CIN5, + CIN4 => CIN4, + CIN3 => CIN3, + CIN2 => CIN2, + CIN1 => CIN1, + CIN0 => CIN0, + CYAWSTN => CYAWSTN, + FF_EBRD_CLK_3 => FF_EBRD_CLK_3, + FF_EBRD_CLK_2 => FF_EBRD_CLK_2, + FF_EBRD_CLK_1 => FF_EBRD_CLK_1, + FF_EBRD_CLK_0 => FF_EBRD_CLK_0, + FF_RXI_CLK_3 => FF_RXI_CLK_3, + FF_RXI_CLK_2 => FF_RXI_CLK_2, + FF_RXI_CLK_1 => FF_RXI_CLK_1, + FF_RXI_CLK_0 => FF_RXI_CLK_0, + + FF_TX_D_0_0 => FF_TX_D_0_0, + FF_TX_D_0_1 => FF_TX_D_0_1, + FF_TX_D_0_2 => FF_TX_D_0_2, + FF_TX_D_0_3 => FF_TX_D_0_3, + FF_TX_D_0_4 => FF_TX_D_0_4, + FF_TX_D_0_5 => FF_TX_D_0_5, + FF_TX_D_0_6 => FF_TX_D_0_6, + FF_TX_D_0_7 => FF_TX_D_0_7, + FF_TX_D_0_8 => FF_TX_D_0_8, + FF_TX_D_0_9 => FF_TX_D_0_9, + FF_TX_D_0_10 => FF_TX_D_0_10, + FF_TX_D_0_11 => FF_TX_D_0_11, + FF_TX_D_0_12 => FF_TX_D_0_12, + FF_TX_D_0_13 => FF_TX_D_0_13, + FF_TX_D_0_14 => FF_TX_D_0_14, + FF_TX_D_0_15 => FF_TX_D_0_15, + FF_TX_D_0_16 => FF_TX_D_0_16, + FF_TX_D_0_17 => FF_TX_D_0_17, + FF_TX_D_0_18 => FF_TX_D_0_18, + FF_TX_D_0_19 => FF_TX_D_0_19, + FF_TX_D_0_20 => FF_TX_D_0_20, + FF_TX_D_0_21 => FF_TX_D_0_21, + FF_TX_D_0_22 => FF_TX_D_0_22, + FF_TX_D_0_23 => FF_TX_D_0_23, + FF_TX_D_1_0 => FF_TX_D_1_0, + FF_TX_D_1_1 => FF_TX_D_1_1, + FF_TX_D_1_2 => FF_TX_D_1_2, + FF_TX_D_1_3 => FF_TX_D_1_3, + FF_TX_D_1_4 => FF_TX_D_1_4, + FF_TX_D_1_5 => FF_TX_D_1_5, + FF_TX_D_1_6 => FF_TX_D_1_6, + FF_TX_D_1_7 => FF_TX_D_1_7, + FF_TX_D_1_8 => FF_TX_D_1_8, + FF_TX_D_1_9 => FF_TX_D_1_9, + FF_TX_D_1_10 => FF_TX_D_1_10, + FF_TX_D_1_11 => FF_TX_D_1_11, + FF_TX_D_1_12 => FF_TX_D_1_12, + FF_TX_D_1_13 => FF_TX_D_1_13, + FF_TX_D_1_14 => FF_TX_D_1_14, + FF_TX_D_1_15 => FF_TX_D_1_15, + FF_TX_D_1_16 => FF_TX_D_1_16, + FF_TX_D_1_17 => FF_TX_D_1_17, + FF_TX_D_1_18 => FF_TX_D_1_18, + FF_TX_D_1_19 => FF_TX_D_1_19, + FF_TX_D_1_20 => FF_TX_D_1_20, + FF_TX_D_1_21 => FF_TX_D_1_21, + FF_TX_D_1_22 => FF_TX_D_1_22, + FF_TX_D_1_23 => FF_TX_D_1_23, + FF_TX_D_2_0 => FF_TX_D_2_0, + FF_TX_D_2_1 => FF_TX_D_2_1, + FF_TX_D_2_2 => FF_TX_D_2_2, + FF_TX_D_2_3 => FF_TX_D_2_3, + FF_TX_D_2_4 => FF_TX_D_2_4, + FF_TX_D_2_5 => FF_TX_D_2_5, + FF_TX_D_2_6 => FF_TX_D_2_6, + FF_TX_D_2_7 => FF_TX_D_2_7, + FF_TX_D_2_8 => FF_TX_D_2_8, + FF_TX_D_2_9 => FF_TX_D_2_9, + FF_TX_D_2_10 => FF_TX_D_2_10, + FF_TX_D_2_11 => FF_TX_D_2_11, + FF_TX_D_2_12 => FF_TX_D_2_12, + FF_TX_D_2_13 => FF_TX_D_2_13, + FF_TX_D_2_14 => FF_TX_D_2_14, + FF_TX_D_2_15 => FF_TX_D_2_15, + FF_TX_D_2_16 => FF_TX_D_2_16, + FF_TX_D_2_17 => FF_TX_D_2_17, + FF_TX_D_2_18 => FF_TX_D_2_18, + FF_TX_D_2_19 => FF_TX_D_2_19, + FF_TX_D_2_20 => FF_TX_D_2_20, + FF_TX_D_2_21 => FF_TX_D_2_21, + FF_TX_D_2_22 => FF_TX_D_2_22, + FF_TX_D_2_23 => FF_TX_D_2_23, + FF_TX_D_3_0 => FF_TX_D_3_0, + FF_TX_D_3_1 => FF_TX_D_3_1, + FF_TX_D_3_2 => FF_TX_D_3_2, + FF_TX_D_3_3 => FF_TX_D_3_3, + FF_TX_D_3_4 => FF_TX_D_3_4, + FF_TX_D_3_5 => FF_TX_D_3_5, + FF_TX_D_3_6 => FF_TX_D_3_6, + FF_TX_D_3_7 => FF_TX_D_3_7, + FF_TX_D_3_8 => FF_TX_D_3_8, + FF_TX_D_3_9 => FF_TX_D_3_9, + FF_TX_D_3_10 => FF_TX_D_3_10, + FF_TX_D_3_11 => FF_TX_D_3_11, + FF_TX_D_3_12 => FF_TX_D_3_12, + FF_TX_D_3_13 => FF_TX_D_3_13, + FF_TX_D_3_14 => FF_TX_D_3_14, + FF_TX_D_3_15 => FF_TX_D_3_15, + FF_TX_D_3_16 => FF_TX_D_3_16, + FF_TX_D_3_17 => FF_TX_D_3_17, + FF_TX_D_3_18 => FF_TX_D_3_18, + FF_TX_D_3_19 => FF_TX_D_3_19, + FF_TX_D_3_20 => FF_TX_D_3_20, + FF_TX_D_3_21 => FF_TX_D_3_21, + FF_TX_D_3_22 => FF_TX_D_3_22, + FF_TX_D_3_23 => FF_TX_D_3_23, + FF_TXI_CLK_0 => FF_TXI_CLK_0, + FF_TXI_CLK_1 => FF_TXI_CLK_1, + FF_TXI_CLK_2 => FF_TXI_CLK_2, + FF_TXI_CLK_3 => FF_TXI_CLK_3, + FFC_CK_CORE_RX => FFC_CK_CORE_RX, + FFC_CK_CORE_TX => FFC_CK_CORE_TX, + FFC_EI_EN_0 => FFC_EI_EN_0, + FFC_EI_EN_1 => FFC_EI_EN_1, + FFC_EI_EN_2 => FFC_EI_EN_2, + FFC_EI_EN_3 => FFC_EI_EN_3, + FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, + FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, + FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, + FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, + FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, + FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, + FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, + FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, + FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, + FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, + FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, + FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, + FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, + FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, + FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, + FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, + FFC_MACRO_RST => FFC_MACRO_RST, + FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, + FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, + FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, + FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, + FFC_PCIE_CT_0 => FFC_PCIE_CT_0, + FFC_PCIE_CT_1 => FFC_PCIE_CT_1, + FFC_PCIE_CT_2 => FFC_PCIE_CT_2, + FFC_PCIE_CT_3 => FFC_PCIE_CT_3, + FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, + FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, + FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, + FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, + FFC_QUAD_RST => FFC_QUAD_RST, + FFC_RRST_0 => FFC_RRST_0, + FFC_RRST_1 => FFC_RRST_1, + FFC_RRST_2 => FFC_RRST_2, + FFC_RRST_3 => FFC_RRST_3, + FFC_RXPWDNB_0 => FFC_RXPWDNB_0, + FFC_RXPWDNB_1 => FFC_RXPWDNB_1, + FFC_RXPWDNB_2 => FFC_RXPWDNB_2, + FFC_RXPWDNB_3 => FFC_RXPWDNB_3, + FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, + FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, + FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, + FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, + FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, + FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, + FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, + FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, + FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, + FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, + FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, + FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, + FFC_TRST => FFC_TRST, + FFC_TXPWDNB_0 => FFC_TXPWDNB_0, + FFC_TXPWDNB_1 => FFC_TXPWDNB_1, + FFC_TXPWDNB_2 => FFC_TXPWDNB_2, + FFC_TXPWDNB_3 => FFC_TXPWDNB_3, + SCIADDR0 => SCIADDR0, + SCIADDR1 => SCIADDR1, + SCIADDR2 => SCIADDR2, + SCIADDR3 => SCIADDR3, + SCIADDR4 => SCIADDR4, + SCIADDR5 => SCIADDR5, + SCIENAUX => SCIENAUX, + SCIENCH0 => SCIENCH0, + SCIENCH1 => SCIENCH1, + SCIENCH2 => SCIENCH2, + SCIENCH3 => SCIENCH3, + SCIRD => SCIRD, + SCISELAUX => SCISELAUX, + SCISELCH0 => SCISELCH0, + SCISELCH1 => SCISELCH1, + SCISELCH2 => SCISELCH2, + SCISELCH3 => SCISELCH3, + SCIWDATA0 => SCIWDATA0, + SCIWDATA1 => SCIWDATA1, + SCIWDATA2 => SCIWDATA2, + SCIWDATA3 => SCIWDATA3, + SCIWDATA4 => SCIWDATA4, + SCIWDATA5 => SCIWDATA5, + SCIWDATA6 => SCIWDATA6, + SCIWDATA7 => SCIWDATA7, + SCIWSTN => SCIWSTN, + HDOUTN0 => HDOUTN0, + HDOUTN1 => HDOUTN1, + HDOUTN2 => HDOUTN2, + HDOUTN3 => HDOUTN3, + HDOUTP0 => HDOUTP0, + HDOUTP1 => HDOUTP1, + HDOUTP2 => HDOUTP2, + HDOUTP3 => HDOUTP3, + COUT19 => COUT19, + COUT18 => COUT18, + COUT17 => COUT17, + COUT16 => COUT16, + COUT15 => COUT15, + COUT14 => COUT14, + COUT13 => COUT13, + COUT12 => COUT12, + COUT11 => COUT11, + COUT10 => COUT10, + COUT9 => COUT9, + COUT8 => COUT8, + COUT7 => COUT7, + COUT6 => COUT6, + COUT5 => COUT5, + COUT4 => COUT4, + COUT3 => COUT3, + COUT2 => COUT2, + COUT1 => COUT1, + COUT0 => COUT0, + FF_RX_D_0_0 => FF_RX_D_0_0, + FF_RX_D_0_1 => FF_RX_D_0_1, + FF_RX_D_0_2 => FF_RX_D_0_2, + FF_RX_D_0_3 => FF_RX_D_0_3, + FF_RX_D_0_4 => FF_RX_D_0_4, + FF_RX_D_0_5 => FF_RX_D_0_5, + FF_RX_D_0_6 => FF_RX_D_0_6, + FF_RX_D_0_7 => FF_RX_D_0_7, + FF_RX_D_0_8 => FF_RX_D_0_8, + FF_RX_D_0_9 => FF_RX_D_0_9, + FF_RX_D_0_10 => FF_RX_D_0_10, + FF_RX_D_0_11 => FF_RX_D_0_11, + FF_RX_D_0_12 => FF_RX_D_0_12, + FF_RX_D_0_13 => FF_RX_D_0_13, + FF_RX_D_0_14 => FF_RX_D_0_14, + FF_RX_D_0_15 => FF_RX_D_0_15, + FF_RX_D_0_16 => FF_RX_D_0_16, + FF_RX_D_0_17 => FF_RX_D_0_17, + FF_RX_D_0_18 => FF_RX_D_0_18, + FF_RX_D_0_19 => FF_RX_D_0_19, + FF_RX_D_0_20 => FF_RX_D_0_20, + FF_RX_D_0_21 => FF_RX_D_0_21, + FF_RX_D_0_22 => FF_RX_D_0_22, + FF_RX_D_0_23 => FF_RX_D_0_23, + FF_RX_D_1_0 => FF_RX_D_1_0, + FF_RX_D_1_1 => FF_RX_D_1_1, + FF_RX_D_1_2 => FF_RX_D_1_2, + FF_RX_D_1_3 => FF_RX_D_1_3, + FF_RX_D_1_4 => FF_RX_D_1_4, + FF_RX_D_1_5 => FF_RX_D_1_5, + FF_RX_D_1_6 => FF_RX_D_1_6, + FF_RX_D_1_7 => FF_RX_D_1_7, + FF_RX_D_1_8 => FF_RX_D_1_8, + FF_RX_D_1_9 => FF_RX_D_1_9, + FF_RX_D_1_10 => FF_RX_D_1_10, + FF_RX_D_1_11 => FF_RX_D_1_11, + FF_RX_D_1_12 => FF_RX_D_1_12, + FF_RX_D_1_13 => FF_RX_D_1_13, + FF_RX_D_1_14 => FF_RX_D_1_14, + FF_RX_D_1_15 => FF_RX_D_1_15, + FF_RX_D_1_16 => FF_RX_D_1_16, + FF_RX_D_1_17 => FF_RX_D_1_17, + FF_RX_D_1_18 => FF_RX_D_1_18, + FF_RX_D_1_19 => FF_RX_D_1_19, + FF_RX_D_1_20 => FF_RX_D_1_20, + FF_RX_D_1_21 => FF_RX_D_1_21, + FF_RX_D_1_22 => FF_RX_D_1_22, + FF_RX_D_1_23 => FF_RX_D_1_23, + FF_RX_D_2_0 => FF_RX_D_2_0, + FF_RX_D_2_1 => FF_RX_D_2_1, + FF_RX_D_2_2 => FF_RX_D_2_2, + FF_RX_D_2_3 => FF_RX_D_2_3, + FF_RX_D_2_4 => FF_RX_D_2_4, + FF_RX_D_2_5 => FF_RX_D_2_5, + FF_RX_D_2_6 => FF_RX_D_2_6, + FF_RX_D_2_7 => FF_RX_D_2_7, + FF_RX_D_2_8 => FF_RX_D_2_8, + FF_RX_D_2_9 => FF_RX_D_2_9, + FF_RX_D_2_10 => FF_RX_D_2_10, + FF_RX_D_2_11 => FF_RX_D_2_11, + FF_RX_D_2_12 => FF_RX_D_2_12, + FF_RX_D_2_13 => FF_RX_D_2_13, + FF_RX_D_2_14 => FF_RX_D_2_14, + FF_RX_D_2_15 => FF_RX_D_2_15, + FF_RX_D_2_16 => FF_RX_D_2_16, + FF_RX_D_2_17 => FF_RX_D_2_17, + FF_RX_D_2_18 => FF_RX_D_2_18, + FF_RX_D_2_19 => FF_RX_D_2_19, + FF_RX_D_2_20 => FF_RX_D_2_20, + FF_RX_D_2_21 => FF_RX_D_2_21, + FF_RX_D_2_22 => FF_RX_D_2_22, + FF_RX_D_2_23 => FF_RX_D_2_23, + FF_RX_D_3_0 => FF_RX_D_3_0, + FF_RX_D_3_1 => FF_RX_D_3_1, + FF_RX_D_3_2 => FF_RX_D_3_2, + FF_RX_D_3_3 => FF_RX_D_3_3, + FF_RX_D_3_4 => FF_RX_D_3_4, + FF_RX_D_3_5 => FF_RX_D_3_5, + FF_RX_D_3_6 => FF_RX_D_3_6, + FF_RX_D_3_7 => FF_RX_D_3_7, + FF_RX_D_3_8 => FF_RX_D_3_8, + FF_RX_D_3_9 => FF_RX_D_3_9, + FF_RX_D_3_10 => FF_RX_D_3_10, + FF_RX_D_3_11 => FF_RX_D_3_11, + FF_RX_D_3_12 => FF_RX_D_3_12, + FF_RX_D_3_13 => FF_RX_D_3_13, + FF_RX_D_3_14 => FF_RX_D_3_14, + FF_RX_D_3_15 => FF_RX_D_3_15, + FF_RX_D_3_16 => FF_RX_D_3_16, + FF_RX_D_3_17 => FF_RX_D_3_17, + FF_RX_D_3_18 => FF_RX_D_3_18, + FF_RX_D_3_19 => FF_RX_D_3_19, + FF_RX_D_3_20 => FF_RX_D_3_20, + FF_RX_D_3_21 => FF_RX_D_3_21, + FF_RX_D_3_22 => FF_RX_D_3_22, + FF_RX_D_3_23 => FF_RX_D_3_23, + FF_RX_F_CLK_0 => FF_RX_F_CLK_0, + FF_RX_F_CLK_1 => FF_RX_F_CLK_1, + FF_RX_F_CLK_2 => FF_RX_F_CLK_2, + FF_RX_F_CLK_3 => FF_RX_F_CLK_3, + FF_RX_H_CLK_0 => FF_RX_H_CLK_0, + FF_RX_H_CLK_1 => FF_RX_H_CLK_1, + FF_RX_H_CLK_2 => FF_RX_H_CLK_2, + FF_RX_H_CLK_3 => FF_RX_H_CLK_3, + FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, + FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, + FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, + FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, + FF_TX_F_CLK => FF_TX_F_CLK, + FF_TX_H_CLK => FF_TX_H_CLK, + FF_TX_Q_CLK => FF_TX_Q_CLK, + FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, + FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, + FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, + FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, + FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, + FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, + FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, + FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, + FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, + FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, + FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, + FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, + FFS_PCIE_CON_0 => FFS_PCIE_CON_0, + FFS_PCIE_CON_1 => FFS_PCIE_CON_1, + FFS_PCIE_CON_2 => FFS_PCIE_CON_2, + FFS_PCIE_CON_3 => FFS_PCIE_CON_3, + FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, + FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, + FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, + FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, + FFS_RLOS_LO_0 => FFS_RLOS_LO_0, + FFS_RLOS_LO_1 => FFS_RLOS_LO_1, + FFS_RLOS_LO_2 => FFS_RLOS_LO_2, + FFS_RLOS_LO_3 => FFS_RLOS_LO_3, + FFS_PLOL => FFS_PLOL, + FFS_RLOL_0 => FFS_RLOL_0, + FFS_RLOL_1 => FFS_RLOL_1, + FFS_RLOL_2 => FFS_RLOL_2, + FFS_RLOL_3 => FFS_RLOL_3, + FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, + FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, + FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, + FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, + FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, + FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, + FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, + FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, + OOB_OUT_0 => OOB_OUT_0, + OOB_OUT_1 => OOB_OUT_1, + OOB_OUT_2 => OOB_OUT_2, + OOB_OUT_3 => OOB_OUT_3, + REFCK2CORE => REFCK2CORE, + SCIINT => SCIINT, + SCIRDATA0 => SCIRDATA0, + SCIRDATA1 => SCIRDATA1, + SCIRDATA2 => SCIRDATA2, + SCIRDATA3 => SCIRDATA3, + SCIRDATA4 => SCIRDATA4, + SCIRDATA5 => SCIRDATA5, + SCIRDATA6 => SCIRDATA6, + SCIRDATA7 => SCIRDATA7 + ); + +end PCSC_arch; + +--synopsys translate_on + +--synopsys translate_off +library ECP2; +use ECP2.components.all; +--synopsys translate_on + +library IEEE, STD; +use IEEE.std_logic_1164.all; +use STD.TEXTIO.all; + +entity serdes_gbe_0_200 is + GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_200.txt"); + port ( + core_txrefclk : in std_logic; + core_rxrefclk : in std_logic; + hdinp0, hdinn0 : in std_logic; + hdoutp0, hdoutn0 : out std_logic; + ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; + ff_txdata_ch0 : in std_logic_vector (15 downto 0); + ff_rxdata_ch0 : out std_logic_vector (15 downto 0); + ff_tx_k_cntrl_ch0 : in std_logic_vector (1 downto 0); + ff_rx_k_cntrl_ch0 : out std_logic_vector (1 downto 0); + ff_rxfullclk_ch0 : out std_logic; + ff_rxhalfclk_ch0 : out std_logic; + ff_xmit_ch0 : in std_logic_vector (1 downto 0); + ff_correct_disp_ch0 : in std_logic_vector (1 downto 0); + ff_disp_err_ch0, ff_cv_ch0 : out std_logic_vector (1 downto 0); + ff_rx_even_ch0 : out std_logic_vector (1 downto 0); + ffc_rrst_ch0 : in std_logic; + ffc_lane_tx_rst_ch0 : in std_logic; + ffc_lane_rx_rst_ch0 : in std_logic; + ffc_txpwdnb_ch0 : in std_logic; + ffc_rxpwdnb_ch0 : in std_logic; + ffs_rlos_lo_ch0 : out std_logic; + ffs_ls_sync_status_ch0 : out std_logic; + ffs_cc_underrun_ch0 : out std_logic; + ffs_cc_overrun_ch0 : out std_logic; + ffs_txfbfifo_error_ch0 : out std_logic; + ffs_rxfbfifo_error_ch0 : out std_logic; + ffs_rlol_ch0 : out std_logic; + oob_out_ch0 : out std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + refck2core : out std_logic; + ffs_plol : out std_logic); + +end serdes_gbe_0_200; + +architecture serdes_gbe_0_200_arch of serdes_gbe_0_200 is + +component VLO +port ( + Z : out std_logic); +end component; + +component VHI +port ( + Z : out std_logic); +end component; +component PCSC +--synopsys translate_off +GENERIC( + CONFIG_FILE : String + ); +--synopsys translate_on +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); +end component; + attribute IS_ASB: string; + attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; + attribute CONFIG_FILE: string; + attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSC_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSC_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSC_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSC_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSC_INST : label is "100.0"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSC_INST : label is "100.0"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSC_INST : label is "100.0"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSC_INST : label is "100.0"; + attribute FREQUENCY_PIN_FF_TX_F_CLK: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK of PCSC_INST : label is "100"; + attribute FREQUENCY_PIN_FF_TX_H_CLK: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK of PCSC_INST : label is "100.0"; + attribute black_box_pad_pin: string; + attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; + +signal fpsc_vlo : std_logic := '0'; +signal cin : std_logic_vector (11 downto 0) := "000000000000"; +signal cout : std_logic_vector (19 downto 0); + +begin + +vlo_inst : VLO port map(Z => fpsc_vlo); + +-- pcs_quad instance +PCSC_INST : PCSC +--synopsys translate_off + generic map (CONFIG_FILE => USER_CONFIG_FILE) +--synopsys translate_on +port map ( + FFC_CK_CORE_TX => core_txrefclk, + FFC_CK_CORE_RX => core_rxrefclk, + REFCLKP => fpsc_vlo, + REFCLKN => fpsc_vlo, + HDINP0 => hdinp0, + HDINN0 => hdinn0, + HDOUTP0 => hdoutp0, + HDOUTN0 => hdoutn0, + SCISELCH0 => fpsc_vlo, + SCIENCH0 => fpsc_vlo, + FF_RXI_CLK_0 => ff_rxiclk_ch0, + FF_TXI_CLK_0 => ff_txiclk_ch0, + FF_EBRD_CLK_0 => ff_ebrd_clk_0, + FF_RX_F_CLK_0 => ff_rxfullclk_ch0, + FF_RX_H_CLK_0 => ff_rxhalfclk_ch0, + FF_RX_Q_CLK_0 => open, + FF_TX_D_0_0 => ff_txdata_ch0(0), + FF_TX_D_0_1 => ff_txdata_ch0(1), + FF_TX_D_0_2 => ff_txdata_ch0(2), + FF_TX_D_0_3 => ff_txdata_ch0(3), + FF_TX_D_0_4 => ff_txdata_ch0(4), + FF_TX_D_0_5 => ff_txdata_ch0(5), + FF_TX_D_0_6 => ff_txdata_ch0(6), + FF_TX_D_0_7 => ff_txdata_ch0(7), + FF_TX_D_0_8 => ff_tx_k_cntrl_ch0(0), + FF_TX_D_0_9 => fpsc_vlo, + FF_TX_D_0_10 => ff_xmit_ch0(0), + FF_TX_D_0_11 => ff_correct_disp_ch0(0), + FF_TX_D_0_12 => ff_txdata_ch0(8), + FF_TX_D_0_13 => ff_txdata_ch0(9), + FF_TX_D_0_14 => ff_txdata_ch0(10), + FF_TX_D_0_15 => ff_txdata_ch0(11), + FF_TX_D_0_16 => ff_txdata_ch0(12), + FF_TX_D_0_17 => ff_txdata_ch0(13), + FF_TX_D_0_18 => ff_txdata_ch0(14), + FF_TX_D_0_19 => ff_txdata_ch0(15), + FF_TX_D_0_20 => ff_tx_k_cntrl_ch0(1), + FF_TX_D_0_21 => fpsc_vlo, + FF_TX_D_0_22 => ff_xmit_ch0(1), + FF_TX_D_0_23 => ff_correct_disp_ch0(1), + FF_RX_D_0_0 => ff_rxdata_ch0(0), + FF_RX_D_0_1 => ff_rxdata_ch0(1), + FF_RX_D_0_2 => ff_rxdata_ch0(2), + FF_RX_D_0_3 => ff_rxdata_ch0(3), + FF_RX_D_0_4 => ff_rxdata_ch0(4), + FF_RX_D_0_5 => ff_rxdata_ch0(5), + FF_RX_D_0_6 => ff_rxdata_ch0(6), + FF_RX_D_0_7 => ff_rxdata_ch0(7), + FF_RX_D_0_8 => ff_rx_k_cntrl_ch0(0), + FF_RX_D_0_9 => ff_disp_err_ch0(0), + FF_RX_D_0_10 => ff_cv_ch0(0), + FF_RX_D_0_11 => ff_rx_even_ch0(0), + FF_RX_D_0_12 => ff_rxdata_ch0(8), + FF_RX_D_0_13 => ff_rxdata_ch0(9), + FF_RX_D_0_14 => ff_rxdata_ch0(10), + FF_RX_D_0_15 => ff_rxdata_ch0(11), + FF_RX_D_0_16 => ff_rxdata_ch0(12), + FF_RX_D_0_17 => ff_rxdata_ch0(13), + FF_RX_D_0_18 => ff_rxdata_ch0(14), + FF_RX_D_0_19 => ff_rxdata_ch0(15), + FF_RX_D_0_20 => ff_rx_k_cntrl_ch0(1), + FF_RX_D_0_21 => ff_disp_err_ch0(1), + FF_RX_D_0_22 => ff_cv_ch0(1), + FF_RX_D_0_23 => ff_rx_even_ch0(1), + FFC_RRST_0 => ffc_rrst_ch0, + FFC_SIGNAL_DETECT_0 => fpsc_vlo, + FFC_ENABLE_CGALIGN_0 => fpsc_vlo, + FFC_SB_PFIFO_LP_0 => fpsc_vlo, + FFC_PFIFO_CLR_0 => fpsc_vlo, + FFC_FB_LOOPBACK_0 => fpsc_vlo, + FFC_SB_INV_RX_0 => fpsc_vlo, + FFC_PCIE_CT_0 => fpsc_vlo, + FFC_PCI_DET_EN_0 => fpsc_vlo, + FFS_PCIE_DONE_0 => open, + FFS_PCIE_CON_0 => open, + FFC_EI_EN_0 => fpsc_vlo, + FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0, + FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0, + FFC_TXPWDNB_0 => ffc_txpwdnb_ch0, + FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0, + FFS_RLOS_LO_0 => ffs_rlos_lo_ch0, + FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0, + FFS_CC_UNDERRUN_0 => ffs_cc_underrun_ch0, + FFS_CC_OVERRUN_0 => ffs_cc_overrun_ch0, + FFS_RXFBFIFO_ERROR_0 => ffs_rxfbfifo_error_ch0, + FFS_TXFBFIFO_ERROR_0 => ffs_txfbfifo_error_ch0, + FFS_RLOL_0 => ffs_rlol_ch0, + OOB_OUT_0 => oob_out_ch0, + HDINP1 => fpsc_vlo, + HDINN1 => fpsc_vlo, + HDOUTP1 => open, + HDOUTN1 => open, + SCISELCH1 => fpsc_vlo, + SCIENCH1 => fpsc_vlo, + FF_RXI_CLK_1 => fpsc_vlo, + FF_TXI_CLK_1 => fpsc_vlo, + FF_EBRD_CLK_1 => fpsc_vlo, + FF_RX_F_CLK_1 => open, + FF_RX_H_CLK_1 => open, + FF_RX_Q_CLK_1 => open, + FF_TX_D_1_0 => fpsc_vlo, + FF_TX_D_1_1 => fpsc_vlo, + FF_TX_D_1_2 => fpsc_vlo, + FF_TX_D_1_3 => fpsc_vlo, + FF_TX_D_1_4 => fpsc_vlo, + FF_TX_D_1_5 => fpsc_vlo, + FF_TX_D_1_6 => fpsc_vlo, + FF_TX_D_1_7 => fpsc_vlo, + FF_TX_D_1_8 => fpsc_vlo, + FF_TX_D_1_9 => fpsc_vlo, + FF_TX_D_1_10 => fpsc_vlo, + FF_TX_D_1_11 => fpsc_vlo, + FF_TX_D_1_12 => fpsc_vlo, + FF_TX_D_1_13 => fpsc_vlo, + FF_TX_D_1_14 => fpsc_vlo, + FF_TX_D_1_15 => fpsc_vlo, + FF_TX_D_1_16 => fpsc_vlo, + FF_TX_D_1_17 => fpsc_vlo, + FF_TX_D_1_18 => fpsc_vlo, + FF_TX_D_1_19 => fpsc_vlo, + FF_TX_D_1_20 => fpsc_vlo, + FF_TX_D_1_21 => fpsc_vlo, + FF_TX_D_1_22 => fpsc_vlo, + FF_TX_D_1_23 => fpsc_vlo, + FF_RX_D_1_0 => open, + FF_RX_D_1_1 => open, + FF_RX_D_1_2 => open, + FF_RX_D_1_3 => open, + FF_RX_D_1_4 => open, + FF_RX_D_1_5 => open, + FF_RX_D_1_6 => open, + FF_RX_D_1_7 => open, + FF_RX_D_1_8 => open, + FF_RX_D_1_9 => open, + FF_RX_D_1_10 => open, + FF_RX_D_1_11 => open, + FF_RX_D_1_12 => open, + FF_RX_D_1_13 => open, + FF_RX_D_1_14 => open, + FF_RX_D_1_15 => open, + FF_RX_D_1_16 => open, + FF_RX_D_1_17 => open, + FF_RX_D_1_18 => open, + FF_RX_D_1_19 => open, + FF_RX_D_1_20 => open, + FF_RX_D_1_21 => open, + FF_RX_D_1_22 => open, + FF_RX_D_1_23 => open, + FFC_RRST_1 => fpsc_vlo, + FFC_SIGNAL_DETECT_1 => fpsc_vlo, + FFC_SB_PFIFO_LP_1 => fpsc_vlo, + FFC_SB_INV_RX_1 => fpsc_vlo, + FFC_PFIFO_CLR_1 => fpsc_vlo, + FFC_PCIE_CT_1 => fpsc_vlo, + FFC_PCI_DET_EN_1 => fpsc_vlo, + FFC_FB_LOOPBACK_1 => fpsc_vlo, + FFC_ENABLE_CGALIGN_1 => fpsc_vlo, + FFC_EI_EN_1 => fpsc_vlo, + FFC_LANE_TX_RST_1 => fpsc_vlo, + FFC_LANE_RX_RST_1 => fpsc_vlo, + FFC_TXPWDNB_1 => fpsc_vlo, + FFC_RXPWDNB_1 => fpsc_vlo, + FFS_RLOS_LO_1 => open, + FFS_PCIE_DONE_1 => open, + FFS_PCIE_CON_1 => open, + FFS_LS_SYNC_STATUS_1 => open, + FFS_CC_UNDERRUN_1 => open, + FFS_CC_OVERRUN_1 => open, + FFS_RLOL_1 => open, + FFS_RXFBFIFO_ERROR_1 => open, + FFS_TXFBFIFO_ERROR_1 => open, + OOB_OUT_1 => open, + HDINP2 => fpsc_vlo, + HDINN2 => fpsc_vlo, + HDOUTP2 => open, + HDOUTN2 => open, + SCISELCH2 => fpsc_vlo, + SCIENCH2 => fpsc_vlo, + FF_RXI_CLK_2 => fpsc_vlo, + FF_TXI_CLK_2 => fpsc_vlo, + FF_EBRD_CLK_2 => fpsc_vlo, + FF_RX_F_CLK_2 => open, + FF_RX_H_CLK_2 => open, + FF_RX_Q_CLK_2 => open, + FF_TX_D_2_0 => fpsc_vlo, + FF_TX_D_2_1 => fpsc_vlo, + FF_TX_D_2_2 => fpsc_vlo, + FF_TX_D_2_3 => fpsc_vlo, + FF_TX_D_2_4 => fpsc_vlo, + FF_TX_D_2_5 => fpsc_vlo, + FF_TX_D_2_6 => fpsc_vlo, + FF_TX_D_2_7 => fpsc_vlo, + FF_TX_D_2_8 => fpsc_vlo, + FF_TX_D_2_9 => fpsc_vlo, + FF_TX_D_2_10 => fpsc_vlo, + FF_TX_D_2_11 => fpsc_vlo, + FF_TX_D_2_12 => fpsc_vlo, + FF_TX_D_2_13 => fpsc_vlo, + FF_TX_D_2_14 => fpsc_vlo, + FF_TX_D_2_15 => fpsc_vlo, + FF_TX_D_2_16 => fpsc_vlo, + FF_TX_D_2_17 => fpsc_vlo, + FF_TX_D_2_18 => fpsc_vlo, + FF_TX_D_2_19 => fpsc_vlo, + FF_TX_D_2_20 => fpsc_vlo, + FF_TX_D_2_21 => fpsc_vlo, + FF_TX_D_2_22 => fpsc_vlo, + FF_TX_D_2_23 => fpsc_vlo, + FF_RX_D_2_0 => open, + FF_RX_D_2_1 => open, + FF_RX_D_2_2 => open, + FF_RX_D_2_3 => open, + FF_RX_D_2_4 => open, + FF_RX_D_2_5 => open, + FF_RX_D_2_6 => open, + FF_RX_D_2_7 => open, + FF_RX_D_2_8 => open, + FF_RX_D_2_9 => open, + FF_RX_D_2_10 => open, + FF_RX_D_2_11 => open, + FF_RX_D_2_12 => open, + FF_RX_D_2_13 => open, + FF_RX_D_2_14 => open, + FF_RX_D_2_15 => open, + FF_RX_D_2_16 => open, + FF_RX_D_2_17 => open, + FF_RX_D_2_18 => open, + FF_RX_D_2_19 => open, + FF_RX_D_2_20 => open, + FF_RX_D_2_21 => open, + FF_RX_D_2_22 => open, + FF_RX_D_2_23 => open, + FFC_RRST_2 => fpsc_vlo, + FFC_SIGNAL_DETECT_2 => fpsc_vlo, + FFC_SB_PFIFO_LP_2 => fpsc_vlo, + FFC_SB_INV_RX_2 => fpsc_vlo, + FFC_PFIFO_CLR_2 => fpsc_vlo, + FFC_PCIE_CT_2 => fpsc_vlo, + FFC_PCI_DET_EN_2 => fpsc_vlo, + FFC_FB_LOOPBACK_2 => fpsc_vlo, + FFC_ENABLE_CGALIGN_2 => fpsc_vlo, + FFC_EI_EN_2 => fpsc_vlo, + FFC_LANE_TX_RST_2 => fpsc_vlo, + FFC_LANE_RX_RST_2 => fpsc_vlo, + FFC_TXPWDNB_2 => fpsc_vlo, + FFC_RXPWDNB_2 => fpsc_vlo, + FFS_RLOS_LO_2 => open, + FFS_PCIE_DONE_2 => open, + FFS_PCIE_CON_2 => open, + FFS_LS_SYNC_STATUS_2 => open, + FFS_CC_UNDERRUN_2 => open, + FFS_CC_OVERRUN_2 => open, + FFS_RLOL_2 => open, + FFS_RXFBFIFO_ERROR_2 => open, + FFS_TXFBFIFO_ERROR_2 => open, + OOB_OUT_2 => open, + HDINP3 => fpsc_vlo, + HDINN3 => fpsc_vlo, + HDOUTP3 => open, + HDOUTN3 => open, + SCISELCH3 => fpsc_vlo, + SCIENCH3 => fpsc_vlo, + FF_RXI_CLK_3 => fpsc_vlo, + FF_TXI_CLK_3 => fpsc_vlo, + FF_EBRD_CLK_3 => fpsc_vlo, + FF_RX_F_CLK_3 => open, + FF_RX_H_CLK_3 => open, + FF_RX_Q_CLK_3 => open, + FF_TX_D_3_0 => fpsc_vlo, + FF_TX_D_3_1 => fpsc_vlo, + FF_TX_D_3_2 => fpsc_vlo, + FF_TX_D_3_3 => fpsc_vlo, + FF_TX_D_3_4 => fpsc_vlo, + FF_TX_D_3_5 => fpsc_vlo, + FF_TX_D_3_6 => fpsc_vlo, + FF_TX_D_3_7 => fpsc_vlo, + FF_TX_D_3_8 => fpsc_vlo, + FF_TX_D_3_9 => fpsc_vlo, + FF_TX_D_3_10 => fpsc_vlo, + FF_TX_D_3_11 => fpsc_vlo, + FF_TX_D_3_12 => fpsc_vlo, + FF_TX_D_3_13 => fpsc_vlo, + FF_TX_D_3_14 => fpsc_vlo, + FF_TX_D_3_15 => fpsc_vlo, + FF_TX_D_3_16 => fpsc_vlo, + FF_TX_D_3_17 => fpsc_vlo, + FF_TX_D_3_18 => fpsc_vlo, + FF_TX_D_3_19 => fpsc_vlo, + FF_TX_D_3_20 => fpsc_vlo, + FF_TX_D_3_21 => fpsc_vlo, + FF_TX_D_3_22 => fpsc_vlo, + FF_TX_D_3_23 => fpsc_vlo, + FF_RX_D_3_0 => open, + FF_RX_D_3_1 => open, + FF_RX_D_3_2 => open, + FF_RX_D_3_3 => open, + FF_RX_D_3_4 => open, + FF_RX_D_3_5 => open, + FF_RX_D_3_6 => open, + FF_RX_D_3_7 => open, + FF_RX_D_3_8 => open, + FF_RX_D_3_9 => open, + FF_RX_D_3_10 => open, + FF_RX_D_3_11 => open, + FF_RX_D_3_12 => open, + FF_RX_D_3_13 => open, + FF_RX_D_3_14 => open, + FF_RX_D_3_15 => open, + FF_RX_D_3_16 => open, + FF_RX_D_3_17 => open, + FF_RX_D_3_18 => open, + FF_RX_D_3_19 => open, + FF_RX_D_3_20 => open, + FF_RX_D_3_21 => open, + FF_RX_D_3_22 => open, + FF_RX_D_3_23 => open, + FFC_RRST_3 => fpsc_vlo, + FFC_SIGNAL_DETECT_3 => fpsc_vlo, + FFC_SB_PFIFO_LP_3 => fpsc_vlo, + FFC_SB_INV_RX_3 => fpsc_vlo, + FFC_PFIFO_CLR_3 => fpsc_vlo, + FFC_PCIE_CT_3 => fpsc_vlo, + FFC_PCI_DET_EN_3 => fpsc_vlo, + FFC_FB_LOOPBACK_3 => fpsc_vlo, + FFC_ENABLE_CGALIGN_3 => fpsc_vlo, + FFC_EI_EN_3 => fpsc_vlo, + FFC_LANE_TX_RST_3 => fpsc_vlo, + FFC_LANE_RX_RST_3 => fpsc_vlo, + FFC_TXPWDNB_3 => fpsc_vlo, + FFC_RXPWDNB_3 => fpsc_vlo, + FFS_RLOS_LO_3 => open, + FFS_PCIE_DONE_3 => open, + FFS_PCIE_CON_3 => open, + FFS_LS_SYNC_STATUS_3 => open, + FFS_CC_UNDERRUN_3 => open, + FFS_CC_OVERRUN_3 => open, + FFS_RLOL_3 => open, + FFS_RXFBFIFO_ERROR_3 => open, + FFS_TXFBFIFO_ERROR_3 => open, + OOB_OUT_3 => open, + SCIWDATA0 => fpsc_vlo, + SCIWDATA1 => fpsc_vlo, + SCIWDATA2 => fpsc_vlo, + SCIWDATA3 => fpsc_vlo, + SCIWDATA4 => fpsc_vlo, + SCIWDATA5 => fpsc_vlo, + SCIWDATA6 => fpsc_vlo, + SCIWDATA7 => fpsc_vlo, + SCIADDR0 => fpsc_vlo, + SCIADDR1 => fpsc_vlo, + SCIADDR2 => fpsc_vlo, + SCIADDR3 => fpsc_vlo, + SCIADDR4 => fpsc_vlo, + SCIADDR5 => fpsc_vlo, + SCIRDATA0 => open, + SCIRDATA1 => open, + SCIRDATA2 => open, + SCIRDATA3 => open, + SCIRDATA4 => open, + SCIRDATA5 => open, + SCIRDATA6 => open, + SCIRDATA7 => open, + SCIENAUX => fpsc_vlo, + SCISELAUX => fpsc_vlo, + SCIRD => fpsc_vlo, + SCIWSTN => fpsc_vlo, + CYAWSTN => fpsc_vlo, + SCIINT => open, + FFC_MACRO_RST => ffc_macro_rst, + FFC_QUAD_RST => ffc_quad_rst, + FFC_TRST => ffc_trst, + FF_TX_F_CLK => ff_txfullclk, + FF_TX_H_CLK => ff_txhalfclk, + FF_TX_Q_CLK => open, + REFCK2CORE => refck2core, + CIN0 => cin(0), + CIN1 => cin(1), + CIN2 => cin(2), + CIN3 => cin(3), + CIN4 => cin(4), + CIN5 => cin(5), + CIN6 => cin(6), + CIN7 => cin(7), + CIN8 => cin(8), + CIN9 => cin(9), + CIN10 => cin(10), + CIN11 => cin(11), + COUT0 => cout(0), + COUT1 => cout(1), + COUT2 => cout(2), + COUT3 => cout(3), + COUT4 => cout(4), + COUT5 => cout(5), + COUT6 => cout(6), + COUT7 => cout(7), + COUT8 => cout(8), + COUT9 => cout(9), + COUT10 => cout(10), + COUT11 => cout(11), + COUT12 => cout(12), + COUT13 => cout(13), + COUT14 => cout(14), + COUT15 => cout(15), + COUT16 => cout(16), + COUT17 => cout(17), + COUT18 => cout(18), + COUT19 => cout(19), + FFS_PLOL => ffs_plol); + +--synopsys translate_off +file_read : PROCESS +VARIABLE open_status : file_open_status; +FILE config : text; +BEGIN + file_open (open_status, config, USER_CONFIG_FILE, read_mode); + IF (open_status = name_error) THEN + report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" + severity ERROR; + END IF; + wait; +END PROCESS; +--synopsys translate_on + +end serdes_gbe_0_200_arch ; diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_0_200_ext.lpc b/media_interfaces/ecp2m_sfp/serdes_gbe_0_200_ext.lpc new file mode 100644 index 0000000..cf0293c --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_0_200_ext.lpc @@ -0,0 +1,145 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=8.0 +ModuleName=serdes_gbe_0_200_ext +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=12/21/2009 +Time=10:35:15 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Protocol=Quad +mode=Gigabit Ethernet +Channel0=SINGLE +Channel1=DISABLE +Channel2=DISABLE +Channel3=DISABLE +Rate0=None +Rate1=None +Rate2=None +Rate3=None +TxRefClk=REFCLK +RxRefClk=REFCLK +ClkRate=2 +ClkMult=10X +CalClkRate=200 +DataWidth=16 +FPGAClkRate=100 +TxRefClkCM=REFCLK +RxRefClk0CM=REFCLK +RxRefClk1CM=REFCLK +RxRefClk2CM=REFCLK +RxRefClk3CM=REFCLK +ClkRateH=1.0 +ClkMultH=10XH +CalClkRateH=200.0 +DataWidthH=8 +FPGAClkRateH=100.0 +VCh0=0 +VCh1=0 +VCh2=0 +VCh3=0 +PreCh0=DISABLE +PreCh1=DISABLE +PreCh2=DISABLE +PreCh3=DISABLE +TxCh0=50 +TxCh1=50 +TxCh2=50 +TxCh3=50 +EqCh0=DISABLE +EqCh1=DISABLE +EqCh2=DISABLE +EqCh3=DISABLE +RxTermCh0=50 +RxTermCh1=50 +RxTermCh2=50 +RxTermCh3=50 +RxCoupCh0=DC +RxCoupCh1=AC +RxCoupCh2=AC +RxCoupCh3=AC +Loss=0 +CDRLoss=0 +TxTerm=50 +TxCoup=DC +TxPllLoss=0 +TxInvCh0=NORMAL +TxInvCh1=NORMAL +TxInvCh2=NORMAL +TxInvCh3=NORMAL +RxInvCh0=NORMAL +RxInvCh1=NORMAL +RxInvCh2=NORMAL +RxInvCh3=NORMAL +RxModeCh0=NORMAL +RxModeCh1=NORMAL +RxModeCh2=NORMAL +RxModeCh3=NORMAL +Plus=1100000101 +Minus=0011111010 +Mask=1111111111 +Align=AUTO +CTCCh0=NORMAL +CTCCh1=NORMAL +CTCCh2=NORMAL +CTCCh3=NORMAL +CC_MATCH1=0000000000 +CC_MATCH2=0000000000 +CC_MATCH3=0110111100 +CC_MATCH4=0001010000 +MinIPG=3 +High=9 +Low=7 +CC_MATCH_MODE=MATCH_3_4 +RxDataCh0=FALSE +RxDataCh1=FALSE +RxDataCh2=FALSE +RxDataCh3=FALSE +AlignerCh0=FALSE +AlignerCh1=FALSE +AlignerCh2=FALSE +AlignerCh3=FALSE +DetectCh0=FALSE +DetectCh1=FALSE +DetectCh2=FALSE +DetectCh3=FALSE +ELSMCh0=FALSE +ELSMCh1=FALSE +ELSMCh2=FALSE +ELSMCh3=FALSE +_teidleCh0=FALSE +_teidleCh1=FALSE +_teidleCh2=FALSE +_teidleCh3=FALSE +Ports0=FALSE +rdoPorts0=Serial Loopback +Ports1=TRUE +Ports2=TRUE +Ports3=FALSE +Ports3_1=FALSE +Ports4=FALSE +_rst_gen=DISABLED +_rx_los_port0=Internal +_rx_los_port1=Internal +_rx_los_port2=Internal +_rx_los_port3=Internal diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_0_200_ext.vhd b/media_interfaces/ecp2m_sfp/serdes_gbe_0_200_ext.vhd new file mode 100644 index 0000000..a97e4da --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_0_200_ext.vhd @@ -0,0 +1,2207 @@ + + +--synopsys translate_off + +library pcsc_work; +use pcsc_work.all; +library IEEE; +use IEEE.std_logic_1164.all; + +entity PCSC is +GENERIC( + CONFIG_FILE : String := "serdes_gbe_0_200_ext.txt" + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); + +end PCSC; + +architecture PCSC_arch of PCSC is + +component PCSC_sim +GENERIC( + CONFIG_FILE : String + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); +end component; + +begin + +PCSC_sim_inst : PCSC_sim +generic map ( + CONFIG_FILE => CONFIG_FILE) +port map ( + HDINN0 => HDINN0, + HDINN1 => HDINN1, + HDINN2 => HDINN2, + HDINN3 => HDINN3, + HDINP0 => HDINP0, + HDINP1 => HDINP1, + HDINP2 => HDINP2, + HDINP3 => HDINP3, + REFCLKN => REFCLKN, + REFCLKP => REFCLKP, + CIN11 => CIN11, + CIN10 => CIN10, + CIN9 => CIN9, + CIN8 => CIN8, + CIN7 => CIN7, + CIN6 => CIN6, + CIN5 => CIN5, + CIN4 => CIN4, + CIN3 => CIN3, + CIN2 => CIN2, + CIN1 => CIN1, + CIN0 => CIN0, + CYAWSTN => CYAWSTN, + FF_EBRD_CLK_3 => FF_EBRD_CLK_3, + FF_EBRD_CLK_2 => FF_EBRD_CLK_2, + FF_EBRD_CLK_1 => FF_EBRD_CLK_1, + FF_EBRD_CLK_0 => FF_EBRD_CLK_0, + FF_RXI_CLK_3 => FF_RXI_CLK_3, + FF_RXI_CLK_2 => FF_RXI_CLK_2, + FF_RXI_CLK_1 => FF_RXI_CLK_1, + FF_RXI_CLK_0 => FF_RXI_CLK_0, + + FF_TX_D_0_0 => FF_TX_D_0_0, + FF_TX_D_0_1 => FF_TX_D_0_1, + FF_TX_D_0_2 => FF_TX_D_0_2, + FF_TX_D_0_3 => FF_TX_D_0_3, + FF_TX_D_0_4 => FF_TX_D_0_4, + FF_TX_D_0_5 => FF_TX_D_0_5, + FF_TX_D_0_6 => FF_TX_D_0_6, + FF_TX_D_0_7 => FF_TX_D_0_7, + FF_TX_D_0_8 => FF_TX_D_0_8, + FF_TX_D_0_9 => FF_TX_D_0_9, + FF_TX_D_0_10 => FF_TX_D_0_10, + FF_TX_D_0_11 => FF_TX_D_0_11, + FF_TX_D_0_12 => FF_TX_D_0_12, + FF_TX_D_0_13 => FF_TX_D_0_13, + FF_TX_D_0_14 => FF_TX_D_0_14, + FF_TX_D_0_15 => FF_TX_D_0_15, + FF_TX_D_0_16 => FF_TX_D_0_16, + FF_TX_D_0_17 => FF_TX_D_0_17, + FF_TX_D_0_18 => FF_TX_D_0_18, + FF_TX_D_0_19 => FF_TX_D_0_19, + FF_TX_D_0_20 => FF_TX_D_0_20, + FF_TX_D_0_21 => FF_TX_D_0_21, + FF_TX_D_0_22 => FF_TX_D_0_22, + FF_TX_D_0_23 => FF_TX_D_0_23, + FF_TX_D_1_0 => FF_TX_D_1_0, + FF_TX_D_1_1 => FF_TX_D_1_1, + FF_TX_D_1_2 => FF_TX_D_1_2, + FF_TX_D_1_3 => FF_TX_D_1_3, + FF_TX_D_1_4 => FF_TX_D_1_4, + FF_TX_D_1_5 => FF_TX_D_1_5, + FF_TX_D_1_6 => FF_TX_D_1_6, + FF_TX_D_1_7 => FF_TX_D_1_7, + FF_TX_D_1_8 => FF_TX_D_1_8, + FF_TX_D_1_9 => FF_TX_D_1_9, + FF_TX_D_1_10 => FF_TX_D_1_10, + FF_TX_D_1_11 => FF_TX_D_1_11, + FF_TX_D_1_12 => FF_TX_D_1_12, + FF_TX_D_1_13 => FF_TX_D_1_13, + FF_TX_D_1_14 => FF_TX_D_1_14, + FF_TX_D_1_15 => FF_TX_D_1_15, + FF_TX_D_1_16 => FF_TX_D_1_16, + FF_TX_D_1_17 => FF_TX_D_1_17, + FF_TX_D_1_18 => FF_TX_D_1_18, + FF_TX_D_1_19 => FF_TX_D_1_19, + FF_TX_D_1_20 => FF_TX_D_1_20, + FF_TX_D_1_21 => FF_TX_D_1_21, + FF_TX_D_1_22 => FF_TX_D_1_22, + FF_TX_D_1_23 => FF_TX_D_1_23, + FF_TX_D_2_0 => FF_TX_D_2_0, + FF_TX_D_2_1 => FF_TX_D_2_1, + FF_TX_D_2_2 => FF_TX_D_2_2, + FF_TX_D_2_3 => FF_TX_D_2_3, + FF_TX_D_2_4 => FF_TX_D_2_4, + FF_TX_D_2_5 => FF_TX_D_2_5, + FF_TX_D_2_6 => FF_TX_D_2_6, + FF_TX_D_2_7 => FF_TX_D_2_7, + FF_TX_D_2_8 => FF_TX_D_2_8, + FF_TX_D_2_9 => FF_TX_D_2_9, + FF_TX_D_2_10 => FF_TX_D_2_10, + FF_TX_D_2_11 => FF_TX_D_2_11, + FF_TX_D_2_12 => FF_TX_D_2_12, + FF_TX_D_2_13 => FF_TX_D_2_13, + FF_TX_D_2_14 => FF_TX_D_2_14, + FF_TX_D_2_15 => FF_TX_D_2_15, + FF_TX_D_2_16 => FF_TX_D_2_16, + FF_TX_D_2_17 => FF_TX_D_2_17, + FF_TX_D_2_18 => FF_TX_D_2_18, + FF_TX_D_2_19 => FF_TX_D_2_19, + FF_TX_D_2_20 => FF_TX_D_2_20, + FF_TX_D_2_21 => FF_TX_D_2_21, + FF_TX_D_2_22 => FF_TX_D_2_22, + FF_TX_D_2_23 => FF_TX_D_2_23, + FF_TX_D_3_0 => FF_TX_D_3_0, + FF_TX_D_3_1 => FF_TX_D_3_1, + FF_TX_D_3_2 => FF_TX_D_3_2, + FF_TX_D_3_3 => FF_TX_D_3_3, + FF_TX_D_3_4 => FF_TX_D_3_4, + FF_TX_D_3_5 => FF_TX_D_3_5, + FF_TX_D_3_6 => FF_TX_D_3_6, + FF_TX_D_3_7 => FF_TX_D_3_7, + FF_TX_D_3_8 => FF_TX_D_3_8, + FF_TX_D_3_9 => FF_TX_D_3_9, + FF_TX_D_3_10 => FF_TX_D_3_10, + FF_TX_D_3_11 => FF_TX_D_3_11, + FF_TX_D_3_12 => FF_TX_D_3_12, + FF_TX_D_3_13 => FF_TX_D_3_13, + FF_TX_D_3_14 => FF_TX_D_3_14, + FF_TX_D_3_15 => FF_TX_D_3_15, + FF_TX_D_3_16 => FF_TX_D_3_16, + FF_TX_D_3_17 => FF_TX_D_3_17, + FF_TX_D_3_18 => FF_TX_D_3_18, + FF_TX_D_3_19 => FF_TX_D_3_19, + FF_TX_D_3_20 => FF_TX_D_3_20, + FF_TX_D_3_21 => FF_TX_D_3_21, + FF_TX_D_3_22 => FF_TX_D_3_22, + FF_TX_D_3_23 => FF_TX_D_3_23, + FF_TXI_CLK_0 => FF_TXI_CLK_0, + FF_TXI_CLK_1 => FF_TXI_CLK_1, + FF_TXI_CLK_2 => FF_TXI_CLK_2, + FF_TXI_CLK_3 => FF_TXI_CLK_3, + FFC_CK_CORE_RX => FFC_CK_CORE_RX, + FFC_CK_CORE_TX => FFC_CK_CORE_TX, + FFC_EI_EN_0 => FFC_EI_EN_0, + FFC_EI_EN_1 => FFC_EI_EN_1, + FFC_EI_EN_2 => FFC_EI_EN_2, + FFC_EI_EN_3 => FFC_EI_EN_3, + FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, + FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, + FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, + FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, + FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, + FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, + FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, + FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, + FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, + FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, + FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, + FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, + FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, + FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, + FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, + FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, + FFC_MACRO_RST => FFC_MACRO_RST, + FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, + FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, + FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, + FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, + FFC_PCIE_CT_0 => FFC_PCIE_CT_0, + FFC_PCIE_CT_1 => FFC_PCIE_CT_1, + FFC_PCIE_CT_2 => FFC_PCIE_CT_2, + FFC_PCIE_CT_3 => FFC_PCIE_CT_3, + FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, + FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, + FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, + FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, + FFC_QUAD_RST => FFC_QUAD_RST, + FFC_RRST_0 => FFC_RRST_0, + FFC_RRST_1 => FFC_RRST_1, + FFC_RRST_2 => FFC_RRST_2, + FFC_RRST_3 => FFC_RRST_3, + FFC_RXPWDNB_0 => FFC_RXPWDNB_0, + FFC_RXPWDNB_1 => FFC_RXPWDNB_1, + FFC_RXPWDNB_2 => FFC_RXPWDNB_2, + FFC_RXPWDNB_3 => FFC_RXPWDNB_3, + FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, + FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, + FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, + FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, + FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, + FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, + FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, + FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, + FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, + FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, + FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, + FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, + FFC_TRST => FFC_TRST, + FFC_TXPWDNB_0 => FFC_TXPWDNB_0, + FFC_TXPWDNB_1 => FFC_TXPWDNB_1, + FFC_TXPWDNB_2 => FFC_TXPWDNB_2, + FFC_TXPWDNB_3 => FFC_TXPWDNB_3, + SCIADDR0 => SCIADDR0, + SCIADDR1 => SCIADDR1, + SCIADDR2 => SCIADDR2, + SCIADDR3 => SCIADDR3, + SCIADDR4 => SCIADDR4, + SCIADDR5 => SCIADDR5, + SCIENAUX => SCIENAUX, + SCIENCH0 => SCIENCH0, + SCIENCH1 => SCIENCH1, + SCIENCH2 => SCIENCH2, + SCIENCH3 => SCIENCH3, + SCIRD => SCIRD, + SCISELAUX => SCISELAUX, + SCISELCH0 => SCISELCH0, + SCISELCH1 => SCISELCH1, + SCISELCH2 => SCISELCH2, + SCISELCH3 => SCISELCH3, + SCIWDATA0 => SCIWDATA0, + SCIWDATA1 => SCIWDATA1, + SCIWDATA2 => SCIWDATA2, + SCIWDATA3 => SCIWDATA3, + SCIWDATA4 => SCIWDATA4, + SCIWDATA5 => SCIWDATA5, + SCIWDATA6 => SCIWDATA6, + SCIWDATA7 => SCIWDATA7, + SCIWSTN => SCIWSTN, + HDOUTN0 => HDOUTN0, + HDOUTN1 => HDOUTN1, + HDOUTN2 => HDOUTN2, + HDOUTN3 => HDOUTN3, + HDOUTP0 => HDOUTP0, + HDOUTP1 => HDOUTP1, + HDOUTP2 => HDOUTP2, + HDOUTP3 => HDOUTP3, + COUT19 => COUT19, + COUT18 => COUT18, + COUT17 => COUT17, + COUT16 => COUT16, + COUT15 => COUT15, + COUT14 => COUT14, + COUT13 => COUT13, + COUT12 => COUT12, + COUT11 => COUT11, + COUT10 => COUT10, + COUT9 => COUT9, + COUT8 => COUT8, + COUT7 => COUT7, + COUT6 => COUT6, + COUT5 => COUT5, + COUT4 => COUT4, + COUT3 => COUT3, + COUT2 => COUT2, + COUT1 => COUT1, + COUT0 => COUT0, + FF_RX_D_0_0 => FF_RX_D_0_0, + FF_RX_D_0_1 => FF_RX_D_0_1, + FF_RX_D_0_2 => FF_RX_D_0_2, + FF_RX_D_0_3 => FF_RX_D_0_3, + FF_RX_D_0_4 => FF_RX_D_0_4, + FF_RX_D_0_5 => FF_RX_D_0_5, + FF_RX_D_0_6 => FF_RX_D_0_6, + FF_RX_D_0_7 => FF_RX_D_0_7, + FF_RX_D_0_8 => FF_RX_D_0_8, + FF_RX_D_0_9 => FF_RX_D_0_9, + FF_RX_D_0_10 => FF_RX_D_0_10, + FF_RX_D_0_11 => FF_RX_D_0_11, + FF_RX_D_0_12 => FF_RX_D_0_12, + FF_RX_D_0_13 => FF_RX_D_0_13, + FF_RX_D_0_14 => FF_RX_D_0_14, + FF_RX_D_0_15 => FF_RX_D_0_15, + FF_RX_D_0_16 => FF_RX_D_0_16, + FF_RX_D_0_17 => FF_RX_D_0_17, + FF_RX_D_0_18 => FF_RX_D_0_18, + FF_RX_D_0_19 => FF_RX_D_0_19, + FF_RX_D_0_20 => FF_RX_D_0_20, + FF_RX_D_0_21 => FF_RX_D_0_21, + FF_RX_D_0_22 => FF_RX_D_0_22, + FF_RX_D_0_23 => FF_RX_D_0_23, + FF_RX_D_1_0 => FF_RX_D_1_0, + FF_RX_D_1_1 => FF_RX_D_1_1, + FF_RX_D_1_2 => FF_RX_D_1_2, + FF_RX_D_1_3 => FF_RX_D_1_3, + FF_RX_D_1_4 => FF_RX_D_1_4, + FF_RX_D_1_5 => FF_RX_D_1_5, + FF_RX_D_1_6 => FF_RX_D_1_6, + FF_RX_D_1_7 => FF_RX_D_1_7, + FF_RX_D_1_8 => FF_RX_D_1_8, + FF_RX_D_1_9 => FF_RX_D_1_9, + FF_RX_D_1_10 => FF_RX_D_1_10, + FF_RX_D_1_11 => FF_RX_D_1_11, + FF_RX_D_1_12 => FF_RX_D_1_12, + FF_RX_D_1_13 => FF_RX_D_1_13, + FF_RX_D_1_14 => FF_RX_D_1_14, + FF_RX_D_1_15 => FF_RX_D_1_15, + FF_RX_D_1_16 => FF_RX_D_1_16, + FF_RX_D_1_17 => FF_RX_D_1_17, + FF_RX_D_1_18 => FF_RX_D_1_18, + FF_RX_D_1_19 => FF_RX_D_1_19, + FF_RX_D_1_20 => FF_RX_D_1_20, + FF_RX_D_1_21 => FF_RX_D_1_21, + FF_RX_D_1_22 => FF_RX_D_1_22, + FF_RX_D_1_23 => FF_RX_D_1_23, + FF_RX_D_2_0 => FF_RX_D_2_0, + FF_RX_D_2_1 => FF_RX_D_2_1, + FF_RX_D_2_2 => FF_RX_D_2_2, + FF_RX_D_2_3 => FF_RX_D_2_3, + FF_RX_D_2_4 => FF_RX_D_2_4, + FF_RX_D_2_5 => FF_RX_D_2_5, + FF_RX_D_2_6 => FF_RX_D_2_6, + FF_RX_D_2_7 => FF_RX_D_2_7, + FF_RX_D_2_8 => FF_RX_D_2_8, + FF_RX_D_2_9 => FF_RX_D_2_9, + FF_RX_D_2_10 => FF_RX_D_2_10, + FF_RX_D_2_11 => FF_RX_D_2_11, + FF_RX_D_2_12 => FF_RX_D_2_12, + FF_RX_D_2_13 => FF_RX_D_2_13, + FF_RX_D_2_14 => FF_RX_D_2_14, + FF_RX_D_2_15 => FF_RX_D_2_15, + FF_RX_D_2_16 => FF_RX_D_2_16, + FF_RX_D_2_17 => FF_RX_D_2_17, + FF_RX_D_2_18 => FF_RX_D_2_18, + FF_RX_D_2_19 => FF_RX_D_2_19, + FF_RX_D_2_20 => FF_RX_D_2_20, + FF_RX_D_2_21 => FF_RX_D_2_21, + FF_RX_D_2_22 => FF_RX_D_2_22, + FF_RX_D_2_23 => FF_RX_D_2_23, + FF_RX_D_3_0 => FF_RX_D_3_0, + FF_RX_D_3_1 => FF_RX_D_3_1, + FF_RX_D_3_2 => FF_RX_D_3_2, + FF_RX_D_3_3 => FF_RX_D_3_3, + FF_RX_D_3_4 => FF_RX_D_3_4, + FF_RX_D_3_5 => FF_RX_D_3_5, + FF_RX_D_3_6 => FF_RX_D_3_6, + FF_RX_D_3_7 => FF_RX_D_3_7, + FF_RX_D_3_8 => FF_RX_D_3_8, + FF_RX_D_3_9 => FF_RX_D_3_9, + FF_RX_D_3_10 => FF_RX_D_3_10, + FF_RX_D_3_11 => FF_RX_D_3_11, + FF_RX_D_3_12 => FF_RX_D_3_12, + FF_RX_D_3_13 => FF_RX_D_3_13, + FF_RX_D_3_14 => FF_RX_D_3_14, + FF_RX_D_3_15 => FF_RX_D_3_15, + FF_RX_D_3_16 => FF_RX_D_3_16, + FF_RX_D_3_17 => FF_RX_D_3_17, + FF_RX_D_3_18 => FF_RX_D_3_18, + FF_RX_D_3_19 => FF_RX_D_3_19, + FF_RX_D_3_20 => FF_RX_D_3_20, + FF_RX_D_3_21 => FF_RX_D_3_21, + FF_RX_D_3_22 => FF_RX_D_3_22, + FF_RX_D_3_23 => FF_RX_D_3_23, + FF_RX_F_CLK_0 => FF_RX_F_CLK_0, + FF_RX_F_CLK_1 => FF_RX_F_CLK_1, + FF_RX_F_CLK_2 => FF_RX_F_CLK_2, + FF_RX_F_CLK_3 => FF_RX_F_CLK_3, + FF_RX_H_CLK_0 => FF_RX_H_CLK_0, + FF_RX_H_CLK_1 => FF_RX_H_CLK_1, + FF_RX_H_CLK_2 => FF_RX_H_CLK_2, + FF_RX_H_CLK_3 => FF_RX_H_CLK_3, + FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, + FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, + FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, + FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, + FF_TX_F_CLK => FF_TX_F_CLK, + FF_TX_H_CLK => FF_TX_H_CLK, + FF_TX_Q_CLK => FF_TX_Q_CLK, + FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, + FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, + FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, + FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, + FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, + FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, + FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, + FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, + FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, + FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, + FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, + FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, + FFS_PCIE_CON_0 => FFS_PCIE_CON_0, + FFS_PCIE_CON_1 => FFS_PCIE_CON_1, + FFS_PCIE_CON_2 => FFS_PCIE_CON_2, + FFS_PCIE_CON_3 => FFS_PCIE_CON_3, + FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, + FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, + FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, + FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, + FFS_RLOS_LO_0 => FFS_RLOS_LO_0, + FFS_RLOS_LO_1 => FFS_RLOS_LO_1, + FFS_RLOS_LO_2 => FFS_RLOS_LO_2, + FFS_RLOS_LO_3 => FFS_RLOS_LO_3, + FFS_PLOL => FFS_PLOL, + FFS_RLOL_0 => FFS_RLOL_0, + FFS_RLOL_1 => FFS_RLOL_1, + FFS_RLOL_2 => FFS_RLOL_2, + FFS_RLOL_3 => FFS_RLOL_3, + FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, + FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, + FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, + FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, + FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, + FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, + FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, + FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, + OOB_OUT_0 => OOB_OUT_0, + OOB_OUT_1 => OOB_OUT_1, + OOB_OUT_2 => OOB_OUT_2, + OOB_OUT_3 => OOB_OUT_3, + REFCK2CORE => REFCK2CORE, + SCIINT => SCIINT, + SCIRDATA0 => SCIRDATA0, + SCIRDATA1 => SCIRDATA1, + SCIRDATA2 => SCIRDATA2, + SCIRDATA3 => SCIRDATA3, + SCIRDATA4 => SCIRDATA4, + SCIRDATA5 => SCIRDATA5, + SCIRDATA6 => SCIRDATA6, + SCIRDATA7 => SCIRDATA7 + ); + +end PCSC_arch; + +--synopsys translate_on + +--synopsys translate_off +library ECP2; +use ECP2.components.all; +--synopsys translate_on + +library IEEE, STD; +use IEEE.std_logic_1164.all; +use STD.TEXTIO.all; + +entity serdes_gbe_0_200_ext is + GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_200_ext.txt"); + port ( + refclkp, refclkn : in std_logic; + hdinp0, hdinn0 : in std_logic; + hdoutp0, hdoutn0 : out std_logic; + ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; + ff_txdata_ch0 : in std_logic_vector (15 downto 0); + ff_rxdata_ch0 : out std_logic_vector (15 downto 0); + ff_tx_k_cntrl_ch0 : in std_logic_vector (1 downto 0); + ff_rx_k_cntrl_ch0 : out std_logic_vector (1 downto 0); + ff_rxfullclk_ch0 : out std_logic; + ff_rxhalfclk_ch0 : out std_logic; + ff_xmit_ch0 : in std_logic_vector (1 downto 0); + ff_correct_disp_ch0 : in std_logic_vector (1 downto 0); + ff_disp_err_ch0, ff_cv_ch0 : out std_logic_vector (1 downto 0); + ff_rx_even_ch0 : out std_logic_vector (1 downto 0); + ffc_rrst_ch0 : in std_logic; + ffc_lane_tx_rst_ch0 : in std_logic; + ffc_lane_rx_rst_ch0 : in std_logic; + ffc_txpwdnb_ch0 : in std_logic; + ffc_rxpwdnb_ch0 : in std_logic; + ffs_rlos_lo_ch0 : out std_logic; + ffs_ls_sync_status_ch0 : out std_logic; + ffs_cc_underrun_ch0 : out std_logic; + ffs_cc_overrun_ch0 : out std_logic; + ffs_txfbfifo_error_ch0 : out std_logic; + ffs_rxfbfifo_error_ch0 : out std_logic; + ffs_rlol_ch0 : out std_logic; + oob_out_ch0 : out std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + refck2core : out std_logic; + ffs_plol : out std_logic); + +end serdes_gbe_0_200_ext; + +architecture serdes_gbe_0_200_ext_arch of serdes_gbe_0_200_ext is + +component VLO +port ( + Z : out std_logic); +end component; + +component VHI +port ( + Z : out std_logic); +end component; +component PCSC +--synopsys translate_off +GENERIC( + CONFIG_FILE : String + ); +--synopsys translate_on +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); +end component; + attribute IS_ASB: string; + attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; + attribute CONFIG_FILE: string; + attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSC_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSC_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSC_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSC_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSC_INST : label is "100.0"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSC_INST : label is "100.0"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSC_INST : label is "100.0"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSC_INST : label is "100.0"; + attribute FREQUENCY_PIN_FF_TX_F_CLK: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK of PCSC_INST : label is "100"; + attribute FREQUENCY_PIN_FF_TX_H_CLK: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK of PCSC_INST : label is "100.0"; + attribute black_box_pad_pin: string; + attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; + +signal fpsc_vlo : std_logic := '0'; +signal cin : std_logic_vector (11 downto 0) := "000000000000"; +signal cout : std_logic_vector (19 downto 0); + +begin + +vlo_inst : VLO port map(Z => fpsc_vlo); + +-- pcs_quad instance +PCSC_INST : PCSC +--synopsys translate_off + generic map (CONFIG_FILE => USER_CONFIG_FILE) +--synopsys translate_on +port map ( + FFC_CK_CORE_TX => fpsc_vlo, + FFC_CK_CORE_RX => fpsc_vlo, + REFCLKP => refclkp, + REFCLKN => refclkn, + HDINP0 => hdinp0, + HDINN0 => hdinn0, + HDOUTP0 => hdoutp0, + HDOUTN0 => hdoutn0, + SCISELCH0 => fpsc_vlo, + SCIENCH0 => fpsc_vlo, + FF_RXI_CLK_0 => ff_rxiclk_ch0, + FF_TXI_CLK_0 => ff_txiclk_ch0, + FF_EBRD_CLK_0 => ff_ebrd_clk_0, + FF_RX_F_CLK_0 => ff_rxfullclk_ch0, + FF_RX_H_CLK_0 => ff_rxhalfclk_ch0, + FF_RX_Q_CLK_0 => open, + FF_TX_D_0_0 => ff_txdata_ch0(0), + FF_TX_D_0_1 => ff_txdata_ch0(1), + FF_TX_D_0_2 => ff_txdata_ch0(2), + FF_TX_D_0_3 => ff_txdata_ch0(3), + FF_TX_D_0_4 => ff_txdata_ch0(4), + FF_TX_D_0_5 => ff_txdata_ch0(5), + FF_TX_D_0_6 => ff_txdata_ch0(6), + FF_TX_D_0_7 => ff_txdata_ch0(7), + FF_TX_D_0_8 => ff_tx_k_cntrl_ch0(0), + FF_TX_D_0_9 => fpsc_vlo, + FF_TX_D_0_10 => ff_xmit_ch0(0), + FF_TX_D_0_11 => ff_correct_disp_ch0(0), + FF_TX_D_0_12 => ff_txdata_ch0(8), + FF_TX_D_0_13 => ff_txdata_ch0(9), + FF_TX_D_0_14 => ff_txdata_ch0(10), + FF_TX_D_0_15 => ff_txdata_ch0(11), + FF_TX_D_0_16 => ff_txdata_ch0(12), + FF_TX_D_0_17 => ff_txdata_ch0(13), + FF_TX_D_0_18 => ff_txdata_ch0(14), + FF_TX_D_0_19 => ff_txdata_ch0(15), + FF_TX_D_0_20 => ff_tx_k_cntrl_ch0(1), + FF_TX_D_0_21 => fpsc_vlo, + FF_TX_D_0_22 => ff_xmit_ch0(1), + FF_TX_D_0_23 => ff_correct_disp_ch0(1), + FF_RX_D_0_0 => ff_rxdata_ch0(0), + FF_RX_D_0_1 => ff_rxdata_ch0(1), + FF_RX_D_0_2 => ff_rxdata_ch0(2), + FF_RX_D_0_3 => ff_rxdata_ch0(3), + FF_RX_D_0_4 => ff_rxdata_ch0(4), + FF_RX_D_0_5 => ff_rxdata_ch0(5), + FF_RX_D_0_6 => ff_rxdata_ch0(6), + FF_RX_D_0_7 => ff_rxdata_ch0(7), + FF_RX_D_0_8 => ff_rx_k_cntrl_ch0(0), + FF_RX_D_0_9 => ff_disp_err_ch0(0), + FF_RX_D_0_10 => ff_cv_ch0(0), + FF_RX_D_0_11 => ff_rx_even_ch0(0), + FF_RX_D_0_12 => ff_rxdata_ch0(8), + FF_RX_D_0_13 => ff_rxdata_ch0(9), + FF_RX_D_0_14 => ff_rxdata_ch0(10), + FF_RX_D_0_15 => ff_rxdata_ch0(11), + FF_RX_D_0_16 => ff_rxdata_ch0(12), + FF_RX_D_0_17 => ff_rxdata_ch0(13), + FF_RX_D_0_18 => ff_rxdata_ch0(14), + FF_RX_D_0_19 => ff_rxdata_ch0(15), + FF_RX_D_0_20 => ff_rx_k_cntrl_ch0(1), + FF_RX_D_0_21 => ff_disp_err_ch0(1), + FF_RX_D_0_22 => ff_cv_ch0(1), + FF_RX_D_0_23 => ff_rx_even_ch0(1), + FFC_RRST_0 => ffc_rrst_ch0, + FFC_SIGNAL_DETECT_0 => fpsc_vlo, + FFC_ENABLE_CGALIGN_0 => fpsc_vlo, + FFC_SB_PFIFO_LP_0 => fpsc_vlo, + FFC_PFIFO_CLR_0 => fpsc_vlo, + FFC_FB_LOOPBACK_0 => fpsc_vlo, + FFC_SB_INV_RX_0 => fpsc_vlo, + FFC_PCIE_CT_0 => fpsc_vlo, + FFC_PCI_DET_EN_0 => fpsc_vlo, + FFS_PCIE_DONE_0 => open, + FFS_PCIE_CON_0 => open, + FFC_EI_EN_0 => fpsc_vlo, + FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0, + FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0, + FFC_TXPWDNB_0 => ffc_txpwdnb_ch0, + FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0, + FFS_RLOS_LO_0 => ffs_rlos_lo_ch0, + FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0, + FFS_CC_UNDERRUN_0 => ffs_cc_underrun_ch0, + FFS_CC_OVERRUN_0 => ffs_cc_overrun_ch0, + FFS_RXFBFIFO_ERROR_0 => ffs_rxfbfifo_error_ch0, + FFS_TXFBFIFO_ERROR_0 => ffs_txfbfifo_error_ch0, + FFS_RLOL_0 => ffs_rlol_ch0, + OOB_OUT_0 => oob_out_ch0, + HDINP1 => fpsc_vlo, + HDINN1 => fpsc_vlo, + HDOUTP1 => open, + HDOUTN1 => open, + SCISELCH1 => fpsc_vlo, + SCIENCH1 => fpsc_vlo, + FF_RXI_CLK_1 => fpsc_vlo, + FF_TXI_CLK_1 => fpsc_vlo, + FF_EBRD_CLK_1 => fpsc_vlo, + FF_RX_F_CLK_1 => open, + FF_RX_H_CLK_1 => open, + FF_RX_Q_CLK_1 => open, + FF_TX_D_1_0 => fpsc_vlo, + FF_TX_D_1_1 => fpsc_vlo, + FF_TX_D_1_2 => fpsc_vlo, + FF_TX_D_1_3 => fpsc_vlo, + FF_TX_D_1_4 => fpsc_vlo, + FF_TX_D_1_5 => fpsc_vlo, + FF_TX_D_1_6 => fpsc_vlo, + FF_TX_D_1_7 => fpsc_vlo, + FF_TX_D_1_8 => fpsc_vlo, + FF_TX_D_1_9 => fpsc_vlo, + FF_TX_D_1_10 => fpsc_vlo, + FF_TX_D_1_11 => fpsc_vlo, + FF_TX_D_1_12 => fpsc_vlo, + FF_TX_D_1_13 => fpsc_vlo, + FF_TX_D_1_14 => fpsc_vlo, + FF_TX_D_1_15 => fpsc_vlo, + FF_TX_D_1_16 => fpsc_vlo, + FF_TX_D_1_17 => fpsc_vlo, + FF_TX_D_1_18 => fpsc_vlo, + FF_TX_D_1_19 => fpsc_vlo, + FF_TX_D_1_20 => fpsc_vlo, + FF_TX_D_1_21 => fpsc_vlo, + FF_TX_D_1_22 => fpsc_vlo, + FF_TX_D_1_23 => fpsc_vlo, + FF_RX_D_1_0 => open, + FF_RX_D_1_1 => open, + FF_RX_D_1_2 => open, + FF_RX_D_1_3 => open, + FF_RX_D_1_4 => open, + FF_RX_D_1_5 => open, + FF_RX_D_1_6 => open, + FF_RX_D_1_7 => open, + FF_RX_D_1_8 => open, + FF_RX_D_1_9 => open, + FF_RX_D_1_10 => open, + FF_RX_D_1_11 => open, + FF_RX_D_1_12 => open, + FF_RX_D_1_13 => open, + FF_RX_D_1_14 => open, + FF_RX_D_1_15 => open, + FF_RX_D_1_16 => open, + FF_RX_D_1_17 => open, + FF_RX_D_1_18 => open, + FF_RX_D_1_19 => open, + FF_RX_D_1_20 => open, + FF_RX_D_1_21 => open, + FF_RX_D_1_22 => open, + FF_RX_D_1_23 => open, + FFC_RRST_1 => fpsc_vlo, + FFC_SIGNAL_DETECT_1 => fpsc_vlo, + FFC_SB_PFIFO_LP_1 => fpsc_vlo, + FFC_SB_INV_RX_1 => fpsc_vlo, + FFC_PFIFO_CLR_1 => fpsc_vlo, + FFC_PCIE_CT_1 => fpsc_vlo, + FFC_PCI_DET_EN_1 => fpsc_vlo, + FFC_FB_LOOPBACK_1 => fpsc_vlo, + FFC_ENABLE_CGALIGN_1 => fpsc_vlo, + FFC_EI_EN_1 => fpsc_vlo, + FFC_LANE_TX_RST_1 => fpsc_vlo, + FFC_LANE_RX_RST_1 => fpsc_vlo, + FFC_TXPWDNB_1 => fpsc_vlo, + FFC_RXPWDNB_1 => fpsc_vlo, + FFS_RLOS_LO_1 => open, + FFS_PCIE_DONE_1 => open, + FFS_PCIE_CON_1 => open, + FFS_LS_SYNC_STATUS_1 => open, + FFS_CC_UNDERRUN_1 => open, + FFS_CC_OVERRUN_1 => open, + FFS_RLOL_1 => open, + FFS_RXFBFIFO_ERROR_1 => open, + FFS_TXFBFIFO_ERROR_1 => open, + OOB_OUT_1 => open, + HDINP2 => fpsc_vlo, + HDINN2 => fpsc_vlo, + HDOUTP2 => open, + HDOUTN2 => open, + SCISELCH2 => fpsc_vlo, + SCIENCH2 => fpsc_vlo, + FF_RXI_CLK_2 => fpsc_vlo, + FF_TXI_CLK_2 => fpsc_vlo, + FF_EBRD_CLK_2 => fpsc_vlo, + FF_RX_F_CLK_2 => open, + FF_RX_H_CLK_2 => open, + FF_RX_Q_CLK_2 => open, + FF_TX_D_2_0 => fpsc_vlo, + FF_TX_D_2_1 => fpsc_vlo, + FF_TX_D_2_2 => fpsc_vlo, + FF_TX_D_2_3 => fpsc_vlo, + FF_TX_D_2_4 => fpsc_vlo, + FF_TX_D_2_5 => fpsc_vlo, + FF_TX_D_2_6 => fpsc_vlo, + FF_TX_D_2_7 => fpsc_vlo, + FF_TX_D_2_8 => fpsc_vlo, + FF_TX_D_2_9 => fpsc_vlo, + FF_TX_D_2_10 => fpsc_vlo, + FF_TX_D_2_11 => fpsc_vlo, + FF_TX_D_2_12 => fpsc_vlo, + FF_TX_D_2_13 => fpsc_vlo, + FF_TX_D_2_14 => fpsc_vlo, + FF_TX_D_2_15 => fpsc_vlo, + FF_TX_D_2_16 => fpsc_vlo, + FF_TX_D_2_17 => fpsc_vlo, + FF_TX_D_2_18 => fpsc_vlo, + FF_TX_D_2_19 => fpsc_vlo, + FF_TX_D_2_20 => fpsc_vlo, + FF_TX_D_2_21 => fpsc_vlo, + FF_TX_D_2_22 => fpsc_vlo, + FF_TX_D_2_23 => fpsc_vlo, + FF_RX_D_2_0 => open, + FF_RX_D_2_1 => open, + FF_RX_D_2_2 => open, + FF_RX_D_2_3 => open, + FF_RX_D_2_4 => open, + FF_RX_D_2_5 => open, + FF_RX_D_2_6 => open, + FF_RX_D_2_7 => open, + FF_RX_D_2_8 => open, + FF_RX_D_2_9 => open, + FF_RX_D_2_10 => open, + FF_RX_D_2_11 => open, + FF_RX_D_2_12 => open, + FF_RX_D_2_13 => open, + FF_RX_D_2_14 => open, + FF_RX_D_2_15 => open, + FF_RX_D_2_16 => open, + FF_RX_D_2_17 => open, + FF_RX_D_2_18 => open, + FF_RX_D_2_19 => open, + FF_RX_D_2_20 => open, + FF_RX_D_2_21 => open, + FF_RX_D_2_22 => open, + FF_RX_D_2_23 => open, + FFC_RRST_2 => fpsc_vlo, + FFC_SIGNAL_DETECT_2 => fpsc_vlo, + FFC_SB_PFIFO_LP_2 => fpsc_vlo, + FFC_SB_INV_RX_2 => fpsc_vlo, + FFC_PFIFO_CLR_2 => fpsc_vlo, + FFC_PCIE_CT_2 => fpsc_vlo, + FFC_PCI_DET_EN_2 => fpsc_vlo, + FFC_FB_LOOPBACK_2 => fpsc_vlo, + FFC_ENABLE_CGALIGN_2 => fpsc_vlo, + FFC_EI_EN_2 => fpsc_vlo, + FFC_LANE_TX_RST_2 => fpsc_vlo, + FFC_LANE_RX_RST_2 => fpsc_vlo, + FFC_TXPWDNB_2 => fpsc_vlo, + FFC_RXPWDNB_2 => fpsc_vlo, + FFS_RLOS_LO_2 => open, + FFS_PCIE_DONE_2 => open, + FFS_PCIE_CON_2 => open, + FFS_LS_SYNC_STATUS_2 => open, + FFS_CC_UNDERRUN_2 => open, + FFS_CC_OVERRUN_2 => open, + FFS_RLOL_2 => open, + FFS_RXFBFIFO_ERROR_2 => open, + FFS_TXFBFIFO_ERROR_2 => open, + OOB_OUT_2 => open, + HDINP3 => fpsc_vlo, + HDINN3 => fpsc_vlo, + HDOUTP3 => open, + HDOUTN3 => open, + SCISELCH3 => fpsc_vlo, + SCIENCH3 => fpsc_vlo, + FF_RXI_CLK_3 => fpsc_vlo, + FF_TXI_CLK_3 => fpsc_vlo, + FF_EBRD_CLK_3 => fpsc_vlo, + FF_RX_F_CLK_3 => open, + FF_RX_H_CLK_3 => open, + FF_RX_Q_CLK_3 => open, + FF_TX_D_3_0 => fpsc_vlo, + FF_TX_D_3_1 => fpsc_vlo, + FF_TX_D_3_2 => fpsc_vlo, + FF_TX_D_3_3 => fpsc_vlo, + FF_TX_D_3_4 => fpsc_vlo, + FF_TX_D_3_5 => fpsc_vlo, + FF_TX_D_3_6 => fpsc_vlo, + FF_TX_D_3_7 => fpsc_vlo, + FF_TX_D_3_8 => fpsc_vlo, + FF_TX_D_3_9 => fpsc_vlo, + FF_TX_D_3_10 => fpsc_vlo, + FF_TX_D_3_11 => fpsc_vlo, + FF_TX_D_3_12 => fpsc_vlo, + FF_TX_D_3_13 => fpsc_vlo, + FF_TX_D_3_14 => fpsc_vlo, + FF_TX_D_3_15 => fpsc_vlo, + FF_TX_D_3_16 => fpsc_vlo, + FF_TX_D_3_17 => fpsc_vlo, + FF_TX_D_3_18 => fpsc_vlo, + FF_TX_D_3_19 => fpsc_vlo, + FF_TX_D_3_20 => fpsc_vlo, + FF_TX_D_3_21 => fpsc_vlo, + FF_TX_D_3_22 => fpsc_vlo, + FF_TX_D_3_23 => fpsc_vlo, + FF_RX_D_3_0 => open, + FF_RX_D_3_1 => open, + FF_RX_D_3_2 => open, + FF_RX_D_3_3 => open, + FF_RX_D_3_4 => open, + FF_RX_D_3_5 => open, + FF_RX_D_3_6 => open, + FF_RX_D_3_7 => open, + FF_RX_D_3_8 => open, + FF_RX_D_3_9 => open, + FF_RX_D_3_10 => open, + FF_RX_D_3_11 => open, + FF_RX_D_3_12 => open, + FF_RX_D_3_13 => open, + FF_RX_D_3_14 => open, + FF_RX_D_3_15 => open, + FF_RX_D_3_16 => open, + FF_RX_D_3_17 => open, + FF_RX_D_3_18 => open, + FF_RX_D_3_19 => open, + FF_RX_D_3_20 => open, + FF_RX_D_3_21 => open, + FF_RX_D_3_22 => open, + FF_RX_D_3_23 => open, + FFC_RRST_3 => fpsc_vlo, + FFC_SIGNAL_DETECT_3 => fpsc_vlo, + FFC_SB_PFIFO_LP_3 => fpsc_vlo, + FFC_SB_INV_RX_3 => fpsc_vlo, + FFC_PFIFO_CLR_3 => fpsc_vlo, + FFC_PCIE_CT_3 => fpsc_vlo, + FFC_PCI_DET_EN_3 => fpsc_vlo, + FFC_FB_LOOPBACK_3 => fpsc_vlo, + FFC_ENABLE_CGALIGN_3 => fpsc_vlo, + FFC_EI_EN_3 => fpsc_vlo, + FFC_LANE_TX_RST_3 => fpsc_vlo, + FFC_LANE_RX_RST_3 => fpsc_vlo, + FFC_TXPWDNB_3 => fpsc_vlo, + FFC_RXPWDNB_3 => fpsc_vlo, + FFS_RLOS_LO_3 => open, + FFS_PCIE_DONE_3 => open, + FFS_PCIE_CON_3 => open, + FFS_LS_SYNC_STATUS_3 => open, + FFS_CC_UNDERRUN_3 => open, + FFS_CC_OVERRUN_3 => open, + FFS_RLOL_3 => open, + FFS_RXFBFIFO_ERROR_3 => open, + FFS_TXFBFIFO_ERROR_3 => open, + OOB_OUT_3 => open, + SCIWDATA0 => fpsc_vlo, + SCIWDATA1 => fpsc_vlo, + SCIWDATA2 => fpsc_vlo, + SCIWDATA3 => fpsc_vlo, + SCIWDATA4 => fpsc_vlo, + SCIWDATA5 => fpsc_vlo, + SCIWDATA6 => fpsc_vlo, + SCIWDATA7 => fpsc_vlo, + SCIADDR0 => fpsc_vlo, + SCIADDR1 => fpsc_vlo, + SCIADDR2 => fpsc_vlo, + SCIADDR3 => fpsc_vlo, + SCIADDR4 => fpsc_vlo, + SCIADDR5 => fpsc_vlo, + SCIRDATA0 => open, + SCIRDATA1 => open, + SCIRDATA2 => open, + SCIRDATA3 => open, + SCIRDATA4 => open, + SCIRDATA5 => open, + SCIRDATA6 => open, + SCIRDATA7 => open, + SCIENAUX => fpsc_vlo, + SCISELAUX => fpsc_vlo, + SCIRD => fpsc_vlo, + SCIWSTN => fpsc_vlo, + CYAWSTN => fpsc_vlo, + SCIINT => open, + FFC_MACRO_RST => ffc_macro_rst, + FFC_QUAD_RST => ffc_quad_rst, + FFC_TRST => ffc_trst, + FF_TX_F_CLK => ff_txfullclk, + FF_TX_H_CLK => ff_txhalfclk, + FF_TX_Q_CLK => open, + REFCK2CORE => refck2core, + CIN0 => cin(0), + CIN1 => cin(1), + CIN2 => cin(2), + CIN3 => cin(3), + CIN4 => cin(4), + CIN5 => cin(5), + CIN6 => cin(6), + CIN7 => cin(7), + CIN8 => cin(8), + CIN9 => cin(9), + CIN10 => cin(10), + CIN11 => cin(11), + COUT0 => cout(0), + COUT1 => cout(1), + COUT2 => cout(2), + COUT3 => cout(3), + COUT4 => cout(4), + COUT5 => cout(5), + COUT6 => cout(6), + COUT7 => cout(7), + COUT8 => cout(8), + COUT9 => cout(9), + COUT10 => cout(10), + COUT11 => cout(11), + COUT12 => cout(12), + COUT13 => cout(13), + COUT14 => cout(14), + COUT15 => cout(15), + COUT16 => cout(16), + COUT17 => cout(17), + COUT18 => cout(18), + COUT19 => cout(19), + FFS_PLOL => ffs_plol); + +--synopsys translate_off +file_read : PROCESS +VARIABLE open_status : file_open_status; +FILE config : text; +BEGIN + file_open (open_status, config, USER_CONFIG_FILE, read_mode); + IF (open_status = name_error) THEN + report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" + severity ERROR; + END IF; + wait; +END PROCESS; +--synopsys translate_on + +end serdes_gbe_0_200_ext_arch ; diff --git a/testbenches/tb_trb_net16_ibuf2.vhd b/testbenches/tb_trb_net16_ibuf2.vhd new file mode 100755 index 0000000..ed3ac19 --- /dev/null +++ b/testbenches/tb_trb_net16_ibuf2.vhd @@ -0,0 +1,264 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY testbench IS +END testbench; + +ARCHITECTURE behavior OF testbench IS + + COMPONENT trb_net16_ibuf + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + CLK_EN : IN std_logic; + MED_DATAREADY_IN : IN std_logic; + MED_DATA_IN : IN std_logic_vector(15 downto 0); + MED_PACKET_NUM_IN : IN std_logic_vector(2 downto 0); + MED_ERROR_IN : IN std_logic_vector(2 downto 0); + INT_INIT_READ_IN : IN std_logic; + INT_REPLY_READ_IN : IN std_logic; + MED_READ_OUT : OUT std_logic; + INT_INIT_DATA_OUT : OUT std_logic_vector(15 downto 0); + INT_INIT_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0); + INT_INIT_DATAREADY_OUT : OUT std_logic; + INT_REPLY_DATA_OUT : OUT std_logic_vector(15 downto 0); + INT_REPLY_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0); + INT_REPLY_DATAREADY_OUT : OUT std_logic; + INT_ERROR_OUT : OUT std_logic_vector(2 downto 0); + STAT_BUFFER_COUNTER : OUT std_logic_vector(31 downto 0); + STAT_BUFFER : OUT std_logic_vector(31 downto 0) + ); + END COMPONENT; + + SIGNAL CLK : std_logic; + SIGNAL RESET : std_logic; + SIGNAL CLK_EN : std_logic; + SIGNAL MED_DATAREADY_IN : std_logic; + SIGNAL MED_DATA_IN : std_logic_vector(15 downto 0); + SIGNAL MED_PACKET_NUM_IN : std_logic_vector(2 downto 0); + SIGNAL MED_READ_OUT : std_logic; + SIGNAL MED_ERROR_IN : std_logic_vector(2 downto 0); + SIGNAL INT_INIT_DATA_OUT : std_logic_vector(15 downto 0); + SIGNAL INT_INIT_PACKET_NUM_OUT : std_logic_vector(2 downto 0); + SIGNAL INT_INIT_DATAREADY_OUT : std_logic; + SIGNAL INT_INIT_READ_IN : std_logic; + SIGNAL INT_REPLY_DATA_OUT : std_logic_vector(15 downto 0); + SIGNAL INT_REPLY_PACKET_NUM_OUT : std_logic_vector(2 downto 0); + SIGNAL INT_REPLY_DATAREADY_OUT : std_logic; + SIGNAL INT_REPLY_READ_IN : std_logic; + SIGNAL INT_ERROR_OUT : std_logic_vector(2 downto 0); + SIGNAL STAT_BUFFER_COUNTER : std_logic_vector(31 downto 0); + SIGNAL STAT_BUFFER : std_logic_vector(31 downto 0); + +BEGIN + +-- Please check and add your generic clause manually + uut: trb_net16_ibuf + PORT MAP( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_ERROR_IN => MED_ERROR_IN, + INT_INIT_DATA_OUT => INT_INIT_DATA_OUT, + INT_INIT_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT, + INT_INIT_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, + INT_INIT_READ_IN => INT_INIT_READ_IN, + INT_REPLY_DATA_OUT => INT_REPLY_DATA_OUT, + INT_REPLY_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT, + INT_REPLY_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, + INT_REPLY_READ_IN => INT_REPLY_READ_IN, + INT_ERROR_OUT => INT_ERROR_OUT, + STAT_BUFFER_COUNTER => STAT_BUFFER_COUNTER, + STAT_BUFFER => STAT_BUFFER + ); + +CLOCK_GEN_PROC: process +begin + clk <= '1'; wait for 5.0 ns; + clk <= '0'; wait for 5.0 ns; +end process CLOCK_GEN_PROC; + +THE_TESTBENCH_PROC: process +begin + -- Setup signals + reset <= '0'; + clk_en <= '1'; + med_dataready_in <= '0'; + med_data_in <= x"0000"; + med_packet_num_in <= b"000"; + med_error_in <= b"000"; + int_init_read_in <= '0'; + int_reply_read_in <= '0'; + wait for 33 ns; + + -- Reset the whole stuff + wait until rising_edge(clk); + reset <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + reset <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + -- Tests may start here + + -- First packet + wait until rising_edge(clk); + med_data_in <= x"0002"; + med_packet_num_in <= b"100"; + med_dataready_in <= '1'; + wait until rising_edge(clk); + med_data_in <= x"dead"; + med_packet_num_in <= b"000"; + wait until rising_edge(clk); + med_data_in <= x"beef"; + med_packet_num_in <= b"001"; + wait until rising_edge(clk); + med_data_in <= x"affe"; + med_packet_num_in <= b"010"; + wait until rising_edge(clk); + med_data_in <= x"d00f"; + med_packet_num_in <= b"011"; + wait until rising_edge(clk); + med_dataready_in <= '0'; + + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + int_init_read_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + int_init_read_in <= '0'; + wait until rising_edge(clk); + + + -- Second packet + wait until rising_edge(clk); + med_data_in <= x"0001"; + med_packet_num_in <= b"100"; + med_dataready_in <= '1'; + wait until rising_edge(clk); + med_data_in <= x"dead"; + med_packet_num_in <= b"000"; + wait until rising_edge(clk); + med_data_in <= x"beef"; + med_packet_num_in <= b"001"; + wait until rising_edge(clk); + med_data_in <= x"affe"; + med_packet_num_in <= b"010"; + wait until rising_edge(clk); + med_data_in <= x"d00f"; + med_packet_num_in <= b"011"; + wait until rising_edge(clk); + med_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + + + + -- Third packet + wait until rising_edge(clk); + med_data_in <= x"0001"; + med_packet_num_in <= b"100"; + med_dataready_in <= '1'; + wait until rising_edge(clk); + med_data_in <= x"dead"; + med_packet_num_in <= b"000"; + wait until rising_edge(clk); + med_data_in <= x"beef"; + med_packet_num_in <= b"001"; + wait until rising_edge(clk); + med_data_in <= x"affe"; + med_packet_num_in <= b"010"; + wait until rising_edge(clk); + med_data_in <= x"d00f"; + med_packet_num_in <= b"011"; + wait until rising_edge(clk); + med_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + int_init_read_in <= '1'; + + -- Fourth packet + wait until rising_edge(clk); + med_data_in <= x"0009"; + med_packet_num_in <= b"100"; + med_dataready_in <= '1'; + wait until rising_edge(clk); + med_data_in <= x"dead"; + med_packet_num_in <= b"000"; + wait until rising_edge(clk); + med_data_in <= x"beef"; + med_packet_num_in <= b"001"; + wait until rising_edge(clk); + int_init_read_in <= '0'; + med_data_in <= x"affe"; + med_packet_num_in <= b"010"; + wait until rising_edge(clk); + med_data_in <= x"d00f"; + med_packet_num_in <= b"011"; + wait until rising_edge(clk); + med_dataready_in <= '0'; + wait until rising_edge(clk); + wait until rising_edge(clk); + int_reply_read_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + + -- Fifth packet + wait until rising_edge(clk); + med_data_in <= x"0009"; + med_packet_num_in <= b"100"; + med_dataready_in <= '1'; + wait until rising_edge(clk); + med_data_in <= x"dead"; + med_packet_num_in <= b"000"; + wait until rising_edge(clk); + med_data_in <= x"beef"; + med_packet_num_in <= b"001"; + wait until rising_edge(clk); + med_data_in <= x"affe"; + med_packet_num_in <= b"010"; + wait until rising_edge(clk); + med_data_in <= x"d00f"; + med_packet_num_in <= b"011"; + wait until rising_edge(clk); + med_dataready_in <= '0'; + int_init_read_in <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + wait until rising_edge(clk); + + -- Stay a while... stay forever!!! Muhahaha!!!! + wait; + +end process THE_TESTBENCH_PROC; + + +END; diff --git a/trb_net16_ibuf2.vhd b/trb_net16_ibuf2.vhd new file mode 100644 index 0000000..bb5f480 --- /dev/null +++ b/trb_net16_ibuf2.vhd @@ -0,0 +1,542 @@ +-- for a description see HADES wiki +-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +entity trb_net16_ibuf is + generic ( + DEPTH : integer range 0 to 7 := c_FIFO_BRAM; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + -- Internal direction port + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_READ_IN : in std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_READ_IN : in std_logic; + INT_ERROR_OUT : out std_logic_vector (2 downto 0); + -- Status and control port + STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); + STAT_BUFFER : out std_logic_vector (31 downto 0) + ); +end entity; + +architecture trb_net16_ibuf_arch of trb_net16_ibuf is + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group"; + + signal fifo_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal fifo_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal fifo_packet_num_in : std_logic_vector(1 downto 0); + signal fifo_write, fifo_read : std_logic; + signal fifo_full, fifo_empty : std_logic; + + signal saved_packet_type : std_logic_vector(3 downto 0); + signal current_fifo_packet_type : std_logic_vector(3 downto 0); + signal saved_fifo_packet_type : std_logic_vector(3 downto 0); + signal comb_fifo_data_out : std_logic_vector(15 downto 0); + signal comb_fifo_packet_num_out : std_logic_vector(1 downto 0); + + signal next_read_out, reg_read_out : std_logic; + signal got_ack_init_internal, reg_ack_init_internal : std_logic; + signal got_ack_reply_internal, reg_ack_reply_internal : std_logic; + signal reg_eob_init_out, reg_eob_reply_out : std_logic; + signal tmp_INT_INIT_DATAREADY_OUT: std_logic; + signal tmp_INT_REPLY_DATAREADY_OUT: std_logic; + signal tmp_INT_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal tmp_INT_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); + + type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_UNDEFINED_ERROR); + signal current_error_state, next_error_state : ERROR_STATE; + signal next_rec_buffer_size_out, current_rec_buffer_size_out: std_logic_vector(3 downto 0); + signal fifo_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + + signal CRC_RESET, CRC_enable : std_logic; + signal CRC_match : std_logic; + signal crc_out : std_logic_vector(15 downto 0); + signal crc_active: std_logic; --crc active in this transfer, i.e. no short transfer + signal crc_data_in : std_logic_vector(15 downto 0); + + signal fifo_data_valid : std_logic; + signal stat_sbufs : std_logic_vector(1 downto 0); + signal counter_match : std_logic; + signal init_buffer_number : std_logic_vector(15 downto 0); + signal reply_buffer_number : std_logic_vector(15 downto 0); + + signal reg_med_data_in : std_logic_vector(15 downto 0); + signal reg_med_dataready_in : std_logic; + signal reg_med_packet_num_in : std_logic_vector(2 downto 0); + + + signal is_h0 : std_logic; + + signal fifo_data_waiting : std_logic := '0'; + signal output_reg_empty : std_logic := '0'; + signal output_reg_enable : std_logic := '0'; + signal buf_DATA_OUT : std_logic_vector(15 downto 0); + signal buf_PACKET_NUM_OUT : std_logic_vector(2 downto 0); + signal buf_INIT_DATAREADY_OUT : std_logic := '0'; + signal buf_REPLY_DATAREADY_OUT : std_logic := '0'; + + + signal fifo_reg_empty : std_logic; + signal fifo_output_valid : std_logic; + signal fifo_reg_enable : std_logic; + signal fifo_reg_valid : std_logic; + + + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_sharing : string; + + attribute syn_preserve of fifo_data_in : signal is true; + attribute syn_preserve of fifo_packet_num_in : signal is true; + attribute syn_keep of fifo_data_in : signal is true; + attribute syn_keep of fifo_packet_num_in : signal is true; + attribute syn_sharing of trb_net16_ibuf_arch : architecture is "off"; + attribute syn_keep of reg_med_data_in : signal is true; + attribute syn_keep of reg_med_dataready_in : signal is true; + attribute syn_keep of reg_med_packet_num_in : signal is true; + attribute syn_keep of saved_packet_type : signal is true; + attribute syn_keep of is_h0 : signal is true; + attribute syn_preserve of reg_med_data_in : signal is true; + attribute syn_preserve of reg_med_dataready_in : signal is true; + attribute syn_preserve of reg_med_packet_num_in : signal is true; + attribute syn_preserve of saved_packet_type : signal is true; + attribute syn_preserve of is_h0 : signal is true; + + + +begin + +counter_match <= '1'; + + +------------------------ +--check incoming data for ACK & fifo status check +------------------------ + + is_h0 <= MED_PACKET_NUM_IN(2) and not MED_PACKET_NUM_IN(1) and not MED_PACKET_NUM_IN(0); + --'1' when MED_PACKET_NUM_IN = c_H0 else '0'; + + proc_store_input_packet_type : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_packet_type <= '1' & TYPE_ILLEGAL; + elsif is_h0 = '1' then + saved_packet_type <= MED_DATA_IN(3 downto 0); + end if; + end if; + end process; + + + proc_filter_input_data : process(reg_MED_DATA_IN, reg_MED_DATAREADY_IN, reg_MED_PACKET_NUM_IN, + fifo_full, current_rec_buffer_size_out, + current_error_state, reg_read_out, saved_packet_type) + begin -- process + got_ack_init_internal <= '0'; + got_ack_reply_internal <= '0'; + next_read_out <= not fifo_full; + fifo_write <= '0'; + next_rec_buffer_size_out <= current_rec_buffer_size_out; + next_error_state <= current_error_state; + if reg_MED_DATAREADY_IN = '1' and reg_read_out= '1' then + if saved_packet_type(2 downto 0) = TYPE_ACK and USE_ACKNOWLEDGE = 1 then + if reg_MED_PACKET_NUM_IN = c_H0 and current_error_state /= GOT_OVERFLOW_ERROR then + got_ack_init_internal <= not saved_packet_type(3); + got_ack_reply_internal <= saved_packet_type(3); + end if; + if reg_MED_PACKET_NUM_IN = c_F1 then + next_rec_buffer_size_out <= reg_MED_DATA_IN(3 downto 0); + end if; + elsif not (saved_packet_type(2 downto 0) = TYPE_ILLEGAL) then + fifo_write <= '1'; + if fifo_full = '1' then + next_error_state <= GOT_OVERFLOW_ERROR; + end if; + end if; + end if; + end process; + + MED_READ_OUT <= reg_read_out; + + reg_buffer: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_rec_buffer_size_out <= (others => '0'); + reg_ack_init_internal <= '0'; + reg_ack_reply_internal <= '0'; + reg_read_out <= '0'; + current_error_state <= IDLE; + else + current_rec_buffer_size_out <= next_rec_buffer_size_out; + reg_ack_init_internal <= got_ack_init_internal; + reg_ack_reply_internal <= got_ack_reply_internal; + reg_read_out <= next_read_out; + current_error_state <= next_error_state; + end if; + end if; + end process; + + + +------------------------ +--FIFO Input +------------------------ + + PROC_REG_INPUT : process(CLK) + begin + if rising_edge(CLK) then + reg_med_data_in <= MED_DATA_IN; + reg_med_packet_num_in <= MED_PACKET_NUM_IN; + reg_med_dataready_in <= MED_DATAREADY_IN; + end if; + end process; + + fifo_data_in <= reg_med_data_in; + fifo_packet_num_in <= reg_med_packet_num_in(2) & reg_med_packet_num_in(0); + + +------------------------ +--save the current packet type from fifo output (including init/reply channel) +------------------------ + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_fifo_packet_type <= '1' & TYPE_ILLEGAL; + elsif fifo_long_packet_num_out = c_H0 and fifo_reg_valid = '1' then + saved_fifo_packet_type <= fifo_data_out(3 downto 0); + end if; + end if; + end process; + + current_fifo_packet_type <= fifo_data_out(3 downto 0) when (fifo_long_packet_num_out = c_H0 and fifo_reg_valid = '1') + else saved_fifo_packet_type; + + + +------------------------ +--CRC check +------------------------ + + gen_crc : if USE_CHECKSUM = c_YES generate + THE_CRC : trb_net_CRC + port map( + CLK => CLK, + RESET => CRC_RESET, + CLK_EN => CRC_enable, + DATA_IN => crc_data_in, + CRC_OUT => crc_out, + CRC_match => CRC_match + ); + + process(fifo_data_out, fifo_reg_valid, fifo_long_packet_num_out, current_fifo_packet_type) + begin + crc_data_in <= fifo_data_out; + CRC_enable <= fifo_reg_valid and not fifo_long_packet_num_out(2); + if (current_fifo_packet_type(2 downto 0) = TYPE_TRM or current_fifo_packet_type(2 downto 0) = TYPE_EOB) and fifo_long_packet_num_out /= c_F0 then + CRC_enable <= '0'; + end if; + end process; + + PROC_SAVE_CRC_USED : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or (current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F3) then + CRC_active <= '0'; + elsif (CRC_enable = '1' and current_fifo_packet_type(2 downto 0) /= TYPE_TRM) then + CRC_active <= '1'; + end if; + end if; + end process; + + end generate; + + gen_no_crc : if USE_CHECKSUM = c_NO generate + CRC_match <= '1'; + CRC_active <= '0'; + end generate; + +-------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------- +------------------------ +--the input fifo +------------------------ + THE_FIFO: trb_net16_fifo + generic map ( + DEPTH => DEPTH + ) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + DATA_IN => fifo_data_in, + PACKET_NUM_IN => fifo_packet_num_in, + WRITE_ENABLE_IN => fifo_write, + DATA_OUT => comb_fifo_data_out, + PACKET_NUM_OUT => comb_fifo_packet_num_out, + READ_ENABLE_IN => fifo_read, + FULL_OUT => fifo_full, + EMPTY_OUT => fifo_empty + ); + + +------------------------ +--Register FIFO Output +------------------------ + + --register fifo output + PROC_SYNC_FIFO_OUTPUTS : process(CLK) + begin + if rising_edge(CLK) then + fifo_output_valid <= (fifo_read and not fifo_empty) or (fifo_output_valid and not fifo_reg_enable); + if fifo_reg_valid = '1' and output_reg_enable = '1' then + fifo_reg_valid <= '0'; + end if; + if fifo_reg_enable = '1' and fifo_output_valid = '1' then + fifo_data_out <= comb_fifo_data_out; + fifo_reg_valid <= '1'; + end if; + end if; + end process; + + fifo_read <= (INT_INIT_READ_IN and buf_INIT_DATAREADY_OUT) or (INT_REPLY_READ_IN and buf_REPLY_DATAREADY_OUT) or + (output_reg_empty or fifo_reg_empty or not fifo_output_valid); +-- +-- (INT_INIT_READ_IN or init_output_reg_empty) and (INT_REPLY_READ_IN or reply_output_reg_empty) +-- and not (fifo_valid_read ) +-- (init_output_reg_empty and reply_output_reg_empty and not fifo_valid_read); + + --generate full packet number + proc_make_full_packet_number : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + fifo_long_packet_num_out <= (others => '0'); + elsif fifo_reg_enable = '1' and fifo_output_valid = '1' then + fifo_long_packet_num_out(2) <= comb_fifo_packet_num_out(1); + fifo_long_packet_num_out(0) <= comb_fifo_packet_num_out(0); + if fifo_long_packet_num_out(2) = '0' and fifo_long_packet_num_out(0) = '1' then + fifo_long_packet_num_out(1) <= not fifo_long_packet_num_out(1); + else + fifo_long_packet_num_out(1) <= fifo_long_packet_num_out(1); + end if; + end if; + end if; + end process; + + +------------------------ +--Handle FiFo output +------------------------ + + --copy fifo dout + PROC_GEN_DATA_OUT : process(fifo_data_out, fifo_long_packet_num_out, current_fifo_packet_type, + CRC_match, counter_match, CRC_active) + begin + tmp_INT_DATA_OUT <= fifo_data_out; + tmp_INT_PACKET_NUM_OUT <= fifo_long_packet_num_out; + if USE_CHECKSUM = 1 then + if current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F2 and CRC_active = '1' then + tmp_INT_DATA_OUT(3) <= fifo_data_out(3) or not CRC_match; + tmp_INT_DATA_OUT(4) <= fifo_data_out(4) or not counter_match; + end if; + end if; + end process; + + + fifo_reg_enable <= output_reg_enable or fifo_reg_empty; + + output_reg_enable <= (INT_INIT_READ_IN and buf_INIT_DATAREADY_OUT) or (INT_REPLY_READ_IN and buf_REPLY_DATAREADY_OUT) or output_reg_empty; + + output_reg_empty <= not buf_INIT_DATAREADY_OUT and not buf_REPLY_DATAREADY_OUT; + fifo_reg_empty <= output_reg_enable and not fifo_reg_valid; + + + --set dataready out + PROC_MAKE_DATAREADY : process(fifo_reg_valid, fifo_data_waiting, current_fifo_packet_type, output_reg_enable) + begin + if ((fifo_reg_valid = '1' or fifo_data_waiting = '1') and (current_fifo_packet_type(2 downto 0) /= TYPE_EOB)) then + tmp_INT_INIT_DATAREADY_OUT <= output_reg_enable and not current_fifo_packet_type(3); + tmp_INT_REPLY_DATAREADY_OUT <= output_reg_enable and current_fifo_packet_type(3); + else + tmp_INT_INIT_DATAREADY_OUT <= '0'; + tmp_INT_REPLY_DATAREADY_OUT <= '0'; + end if; + end process; + + proc_reg_waiting_data: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + fifo_data_waiting <= '0'; + elsif ((fifo_reg_valid = '1' or fifo_data_waiting = '1') and (current_fifo_packet_type(2 downto 0) /= TYPE_EOB)) then + fifo_data_waiting <= not output_reg_enable; + end if; + end if; + end process; + + + --reset CRC generator + CRC_RESET <= '1' when current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F3 else RESET; + + --Trigger sending ACK + gen_ack1 : if USE_ACKNOWLEDGE = 1 generate + proc_reg_eob_out: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + reg_eob_init_out <= '0'; + reg_eob_reply_out <= '0'; + elsif fifo_reg_valid = '1' and USE_ACKNOWLEDGE = 1 then + if ( current_fifo_packet_type(2 downto 0) = TYPE_EOB + or current_fifo_packet_type(2 downto 0) = TYPE_TRM) and fifo_long_packet_num_out = c_F3 then + reg_eob_init_out <= not current_fifo_packet_type(3); + reg_eob_reply_out <= current_fifo_packet_type(3); + end if; + else + reg_eob_init_out <= '0'; + reg_eob_reply_out <= '0'; + end if; + end if; + end process; + + --Count received buffers + proc_count_buffers : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + init_buffer_number <= (others => '1'); + reply_buffer_number <= (others => '1'); + elsif CLK_EN = '1' then + if reg_eob_init_out = '1' then + init_buffer_number <= init_buffer_number + 1; + end if; + if reg_eob_reply_out = '1' then + reply_buffer_number <= reply_buffer_number + 1; + end if; + end if; + end if; + end process; + end generate; + + + + + +------------------------ +--Output logic +------------------------ + PROC_output_reg : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + buf_INIT_DATAREADY_OUT <= '0'; + elsif output_reg_enable = '1' then + buf_DATA_OUT <= tmp_INT_DATA_OUT; + buf_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT; + buf_INIT_DATAREADY_OUT <= tmp_INT_INIT_DATAREADY_OUT; + buf_REPLY_DATAREADY_OUT <= tmp_INT_REPLY_DATAREADY_OUT; + end if; + end if; + end process; + + + gen_init_sbuf : if INIT_CAN_RECEIVE_DATA = c_YES generate + INT_INIT_DATA_OUT <= buf_DATA_OUT; + INT_INIT_PACKET_NUM_OUT <= buf_PACKET_NUM_OUT; + INT_INIT_DATAREADY_OUT <= buf_INIT_DATAREADY_OUT; + end generate; + gen_no_init_sbuf : if INIT_CAN_RECEIVE_DATA = c_NO generate + INT_INIT_DATA_OUT <= (others => '0'); + INT_INIT_PACKET_NUM_OUT <= (others => '0'); + INT_INIT_DATAREADY_OUT <= '0'; + end generate; + + gen_reply_sbuf : if REPLY_CAN_RECEIVE_DATA = c_YES generate + INT_REPLY_DATA_OUT <= buf_DATA_OUT; + INT_REPLY_PACKET_NUM_OUT <= buf_PACKET_NUM_OUT; + INT_REPLY_DATAREADY_OUT <= buf_REPLY_DATAREADY_OUT; + end generate; + gen_no_reply_sbuf : if REPLY_CAN_RECEIVE_DATA = c_NO generate + INT_REPLY_DATA_OUT <= (others => '0'); + INT_REPLY_PACKET_NUM_OUT <= (others => '0'); + INT_REPLY_DATAREADY_OUT <= '0'; + end generate; + +-------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------- + +------------------------ +--Debugging Signals +------------------------ + + STAT_BUFFER_COUNTER <= reply_buffer_number & init_buffer_number; + stat_sbufs <= "00"; +-- make STAT_BUFFER + STAT_BUFFER(3 downto 0) <= std_logic_vector(to_unsigned(DEPTH,4)); + STAT_BUFFER(7 downto 4) <= current_rec_buffer_size_out; + + gen_ack2 : if USE_ACKNOWLEDGE = 1 generate + STAT_BUFFER(8) <= reg_eob_init_out; + STAT_BUFFER(9) <= reg_ack_init_internal; + STAT_BUFFER(10) <= reg_eob_reply_out; + STAT_BUFFER(11) <= reg_ack_reply_internal; + end generate; + gen_ack3 : if USE_ACKNOWLEDGE = 0 generate + STAT_BUFFER(11 downto 8) <= (others => '0'); + end generate; + + process(current_error_state) + begin + case current_error_state is + when IDLE => STAT_BUFFER(13 downto 12) <= "00"; + when GOT_OVERFLOW_ERROR => STAT_BUFFER(13 downto 12) <= "01"; + when others => STAT_BUFFER(13 downto 12) <= "11"; + end case; + end process; + + STAT_BUFFER(14) <= fifo_write; + STAT_BUFFER(17 downto 15) <= saved_packet_type(2 downto 0); + STAT_BUFFER(18) <= CRC_match; + STAT_BUFFER(19) <= CRC_enable; + STAT_BUFFER(20) <= CRC_RESET; + STAT_BUFFER(31 downto 21) <= (others => '0'); + + + INT_ERROR_OUT <= MED_ERROR_IN; + +end architecture; + diff --git a/trb_net_sbuf2.vhd b/trb_net_sbuf2.vhd new file mode 100644 index 0000000..0807212 --- /dev/null +++ b/trb_net_sbuf2.vhd @@ -0,0 +1,136 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + +entity trb_net_sbuf2 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + COMB_DATAREADY_IN : in STD_LOGIC; + COMB_next_READ_OUT : out STD_LOGIC; + COMB_READ_IN : in STD_LOGIC; + COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + + SYN_DATAREADY_OUT : out STD_LOGIC; + SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN : in STD_LOGIC; + STAT_BUFFER : out STD_LOGIC + ); +end trb_net_sbuf2; + +architecture trb_net_sbuf_arch of trb_net_sbuf2 is + + component fifo_sbuf is + port ( + Data : in std_logic_vector(18 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(18 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + signal fifo_data_in : std_logic_vector(18 downto 0); + signal fifo_data_out : std_logic_vector(18 downto 0); + signal reg_fifo_data_out : std_logic_vector(18 downto 0); + signal fifo_wr_en : std_logic; + signal fifo_rd_en : std_logic; + signal fifo_empty : std_logic; + signal fifo_full : std_logic; + signal fifo_almost_full : std_logic; + signal fifo_read_before : std_logic; + signal next_last_fifo_read : std_logic; + signal last_fifo_read : std_logic; + + +begin + + +--write to fifo if fifo is not full and data is available + PROC_REG_INPUT : process(CLK) + begin + if rising_edge(CLK) then + fifo_data_in <= COMB_DATA_IN; + fifo_wr_en <= COMB_DATAREADY_IN and COMB_READ_IN and not fifo_full; + end if; + end process; + + + COMB_next_READ_OUT <= not fifo_almost_full; + +--connect to outputs + SYN_DATAREADY_OUT <= fifo_read_before; + SYN_DATA_OUT <= reg_fifo_data_out; + STAT_BUFFER <= fifo_full; + + +--fifo read signal + fifo_rd_en <= SYN_READ_IN or (not next_last_fifo_read and not fifo_read_before); + +--the fifo + THE_BUFFER : fifo_sbuf + port map( + Data => fifo_data_in, + Clock => CLK, + WrEn => fifo_wr_en, + RdEn => fifo_rd_en, + Reset => RESET, + Q => fifo_data_out, + Empty => fifo_empty, + Full => fifo_full, + AlmostFull => fifo_almost_full + ); + + +-- is data on output valid? + PROC_DETECT_VALID_READS : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + fifo_read_before <= '0'; + elsif CLK_EN = '1' then + if next_last_fifo_read = '1' then + fifo_read_before <= '1'; + elsif SYN_READ_IN = '1' then + fifo_read_before <= '0'; + end if; + end if; + end if; + end process; + +-- keep track of fifo read operations + PROC_LAST_FIFO_READ : process(CLK) + begin + if rising_edge(CLK) then + next_last_fifo_read <= fifo_rd_en and not fifo_empty; + last_fifo_read <= next_last_fifo_read and not RESET; + end if; + end process; + + +--register on fifo outputs + PROC_SYNC_FIFO_OUTPUTS : process(CLK) + begin + if rising_edge(CLK) then + if next_last_fifo_read = '1' then + reg_fifo_data_out <= fifo_data_out; + end if; + end if; + end process; + + +end architecture; \ No newline at end of file diff --git a/trb_net_sbuf3.vhd b/trb_net_sbuf3.vhd new file mode 100644 index 0000000..d633f91 --- /dev/null +++ b/trb_net_sbuf3.vhd @@ -0,0 +1,207 @@ + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + +entity trb_net_sbuf3 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT : out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN : in STD_LOGIC; --comb logic IS reading + -- the COMB_next_READ_OUT should be connected via comb. logic to a register + -- to provide COMB_READ_IN (feedback path with 1 cycle delay) + COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + -- Port to synchronous output. + SYN_DATAREADY_OUT : out STD_LOGIC; + SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + SYN_READ_IN : in STD_LOGIC; + -- Status and control port + STAT_BUFFER : out STD_LOGIC + ); +end entity; + +architecture trb_net_sbuf3_arch of trb_net_sbuf3 is + + signal current_b0_buffer : std_logic_vector (DATA_WIDTH-1 downto 0); + signal current_b1_buffer : std_logic_vector (DATA_WIDTH-1 downto 0); + signal current_b2_buffer : std_logic_vector (DATA_WIDTH-1 downto 0); + + signal next_next_READ_OUT, current_next_READ_OUT : std_logic; + signal next_SYN_DATAREADY_OUT, current_SYN_DATAREADY_OUT : std_logic; + + type BUFFER_STATE is (BUFFER_EMPTY, BUFFER_B2_FULL, BUFFER_B1_FULL,BUFFER_B0_FULL); + signal current_buffer_state, next_buffer_state : BUFFER_STATE; + signal current_buffer_state_int : STD_LOGIC_VECTOR (1 downto 0); + + signal current_got_overflow, next_got_overflow : std_logic; + signal combined_COMB_DATAREADY_IN: std_logic; + + + signal move_b1_b2 : std_logic; + signal move_b0_b1 : std_logic; + + signal load_b2 : std_logic; + signal load_b1 : std_logic; + signal load_b0 : std_logic; + + + + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_preserve of current_SYN_DATAREADY_OUT : signal is true; + attribute syn_keep of current_SYN_DATAREADY_OUT : signal is true; + attribute syn_preserve of current_next_READ_OUT : signal is true; + attribute syn_keep of current_next_READ_OUT : signal is true; + attribute syn_hier : string; + attribute syn_hier of trb_net_sbuf3_arch : architecture is "flatten, firm"; + + +begin + + SYN_DATA_OUT <= current_b2_buffer; + SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT; + COMB_next_READ_OUT <= current_next_READ_OUT; + + STAT_BUFFER <= current_got_overflow; + + combined_COMB_DATAREADY_IN <= (COMB_DATAREADY_IN and COMB_READ_IN); + + + + + THE_FSM: process (current_buffer_state, SYN_READ_IN, + current_SYN_DATAREADY_OUT, current_got_overflow, + combined_COMB_DATAREADY_IN) + begin -- process COMB + next_buffer_state <= current_buffer_state; + next_next_READ_OUT <= '1'; + load_b0 <= '0'; + load_b1 <= '0'; + load_b2 <= '0'; + move_b1_b2 <= '0'; + move_b0_b1 <= '0'; + next_SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT; + next_got_overflow <= current_got_overflow; + + case current_buffer_state is + when BUFFER_EMPTY => + current_buffer_state_int <= "00"; + if combined_COMB_DATAREADY_IN = '1' then + next_buffer_state <= BUFFER_B2_FULL; + load_b2 <= '1'; + next_SYN_DATAREADY_OUT <= '1'; + end if; + + when BUFFER_B2_FULL => + current_buffer_state_int <= "01"; + next_SYN_DATAREADY_OUT <= '1'; + if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then + load_b2 <= '1'; + elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then + next_buffer_state <= BUFFER_B1_FULL; + next_next_READ_OUT <= '0'; + load_b1 <= '1'; + elsif combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' then + next_buffer_state <= BUFFER_EMPTY; + next_SYN_DATAREADY_OUT <= '0'; + else + --next_next_READ_OUT <= '0'; + + end if; + + when BUFFER_B1_FULL => + current_buffer_state_int <= "10"; + next_SYN_DATAREADY_OUT <= '1'; + next_next_READ_OUT <= '0'; + if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then + load_b1 <= '1'; + move_b1_b2 <= '1'; + elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then + next_buffer_state <= BUFFER_B0_FULL; + load_b0 <= '1'; + elsif combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' then + next_buffer_state <= BUFFER_B2_FULL; + next_next_READ_OUT <= '1'; + move_b1_b2 <= '1'; + end if; + + when BUFFER_B0_FULL => + current_buffer_state_int <= "11"; + next_SYN_DATAREADY_OUT <= '1'; + next_next_READ_OUT <= '0'; + if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then + next_got_overflow <= '1'; + elsif combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' then + move_b1_b2 <= '1'; + move_b0_b1 <= '1'; + next_buffer_state <= BUFFER_B1_FULL; + elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then + move_b1_b2 <= '1'; + move_b0_b1 <= '1'; + load_b0 <= '1'; + end if; + end case; + end process; + + + + PROC_FSM_REG : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_buffer_state <= BUFFER_EMPTY; + current_got_overflow <= '0'; + current_SYN_DATAREADY_OUT <= '0'; + current_next_READ_OUT <= '0'; + elsif CLK_EN = '1' then + current_buffer_state <= next_buffer_state; + current_got_overflow <= next_got_overflow; + current_SYN_DATAREADY_OUT <= next_SYN_DATAREADY_OUT; + current_next_READ_OUT <= next_next_READ_OUT; + end if; + end if; + end process; + + + PROC_REG_BUFFERS : process(CLK) + begin + if rising_edge(CLK) then + if move_b1_b2 = '1' then + current_b2_buffer <= current_b1_buffer; + end if; + + if move_b0_b1 = '1' then + current_b1_buffer <= current_b0_buffer; + end if; + + if load_b2 = '1' then + current_b2_buffer <= COMB_DATA_IN; + end if; + + if load_b1 = '1' then + current_b1_buffer <= COMB_DATA_IN; + end if; + + if load_b0 = '1' then + current_b0_buffer <= COMB_DATA_IN; + end if; + + end if; + end process; + + + +end architecture; + diff --git a/trb_net_sbuf4.vhd b/trb_net_sbuf4.vhd new file mode 100644 index 0000000..d016bea --- /dev/null +++ b/trb_net_sbuf4.vhd @@ -0,0 +1,210 @@ + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + +entity trb_net_sbuf4 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT : out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN : in STD_LOGIC; --comb logic IS reading + -- the COMB_next_READ_OUT should be connected via comb. logic to a register + -- to provide COMB_READ_IN (feedback path with 1 cycle delay) + COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + -- Port to synchronous output. + SYN_DATAREADY_OUT : out STD_LOGIC; + SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + SYN_READ_IN : in STD_LOGIC; + -- Status and control port + STAT_BUFFER : out STD_LOGIC + ); +end entity; + +architecture trb_net_sbuf4_arch of trb_net_sbuf4 is + + signal current_b0_buffer : std_logic_vector (DATA_WIDTH-1 downto 0); + signal current_b1_buffer : std_logic_vector (DATA_WIDTH-1 downto 0); + signal current_b2_buffer : std_logic_vector (DATA_WIDTH-1 downto 0); + + signal next_next_READ_OUT, current_next_READ_OUT : std_logic; + signal next_SYN_DATAREADY_OUT, current_SYN_DATAREADY_OUT : std_logic; + +-- signal move_b1_buffer, move_b2_buffer, move_b3_buffer: std_logic; + + type BUFFER_STATE is (BUFFER_EMPTY, BUFFER_B2_FULL, BUFFER_B1_FULL,BUFFER_B0_FULL); + signal current_buffer_state, next_buffer_state : BUFFER_STATE; + signal current_buffer_state_int : STD_LOGIC_VECTOR (1 downto 0); + + signal current_got_overflow, next_got_overflow : std_logic; + signal combined_COMB_DATAREADY_IN: std_logic; +-- signal use_current_b1_buffer: std_logic; +-- signal use_current_b0_buffer: std_logic; + + signal move_b1_b2 : std_logic; + signal move_b0_b1 : std_logic; + + signal load_b2 : std_logic; + signal load_b1 : std_logic; + signal load_b0 : std_logic; + + + + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_preserve of current_SYN_DATAREADY_OUT : signal is true; + attribute syn_keep of current_SYN_DATAREADY_OUT : signal is true; + attribute syn_preserve of current_next_READ_OUT : signal is true; + attribute syn_keep of current_next_READ_OUT : signal is true; + attribute syn_hier : string; + attribute syn_hier of trb_net_sbuf4_arch : architecture is "flatten, firm"; + + +begin + + SYN_DATA_OUT <= current_b2_buffer; + SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT; + COMB_next_READ_OUT <= current_next_READ_OUT; + + STAT_BUFFER <= current_got_overflow; + + combined_COMB_DATAREADY_IN <= (COMB_DATAREADY_IN and COMB_READ_IN); + + + + + THE_FSM: process (current_buffer_state, SYN_READ_IN, + current_SYN_DATAREADY_OUT, current_got_overflow, + combined_COMB_DATAREADY_IN) + begin -- process COMB + next_buffer_state <= current_buffer_state; + next_next_READ_OUT <= '1'; + load_b0 <= '0'; + load_b1 <= '0'; + load_b2 <= '0'; + move_b1_b2 <= '0'; + move_b0_b1 <= '0'; + next_SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT; + next_got_overflow <= current_got_overflow; + + case current_buffer_state is + when BUFFER_EMPTY => + current_buffer_state_int <= "00"; + if combined_COMB_DATAREADY_IN = '1' then + next_buffer_state <= BUFFER_B2_FULL; + load_b2 <= '1'; + next_SYN_DATAREADY_OUT <= '1'; + end if; + + when BUFFER_B2_FULL => + current_buffer_state_int <= "01"; + next_SYN_DATAREADY_OUT <= '1'; + if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then + load_b2 <= '1'; + elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then + next_buffer_state <= BUFFER_B1_FULL; + next_next_READ_OUT <= '0'; + load_b1 <= '1'; + elsif combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' then + next_buffer_state <= BUFFER_EMPTY; + next_SYN_DATAREADY_OUT <= '0'; + else + --next_next_READ_OUT <= '0'; + + end if; + + when BUFFER_B1_FULL => + current_buffer_state_int <= "10"; + next_SYN_DATAREADY_OUT <= '1'; + next_next_READ_OUT <= '0'; + if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then + load_b1 <= '1'; + move_b1_b2 <= '1'; + elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then + next_buffer_state <= BUFFER_B0_FULL; + load_b0 <= '1'; + elsif combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' then + next_buffer_state <= BUFFER_B2_FULL; + next_next_READ_OUT <= '1'; + move_b1_b2 <= '1'; + end if; + + when BUFFER_B0_FULL => + current_buffer_state_int <= "11"; + next_SYN_DATAREADY_OUT <= '1'; + next_next_READ_OUT <= '0'; + if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then + next_got_overflow <= '1'; + elsif combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' then + move_b1_b2 <= '1'; + move_b0_b1 <= '1'; + next_buffer_state <= BUFFER_B1_FULL; + elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then + move_b1_b2 <= '1'; + move_b0_b1 <= '1'; + load_b0 <= '1'; + end if; + end case; + end process; + + + + PROC_FSM_REG : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_buffer_state <= BUFFER_EMPTY; + current_got_overflow <= '0'; + current_SYN_DATAREADY_OUT <= '0'; + current_next_READ_OUT <= '0'; + elsif CLK_EN = '1' then + current_buffer_state <= next_buffer_state; + current_got_overflow <= next_got_overflow; + current_SYN_DATAREADY_OUT <= next_SYN_DATAREADY_OUT; + current_next_READ_OUT <= next_next_READ_OUT; + end if; + end if; + end process; + + + PROC_REG_BUFFERS : process(CLK) + begin + if rising_edge(CLK) then + if move_b1_b2 = '1' then + current_b2_buffer <= current_b1_buffer; + end if; + + if move_b0_b1 = '1' then + current_b1_buffer <= current_b0_buffer; + end if; + + if load_b2 = '1' then + current_b2_buffer <= COMB_DATA_IN; + end if; + + if load_b1 = '1' then + current_b1_buffer <= COMB_DATA_IN; + end if; + + if load_b0 = '1' then + current_b0_buffer <= COMB_DATA_IN; + end if; + + end if; + end process; + + + +end architecture; +