From: Jan Michel <j.michel@gsi.de>
Date: Fri, 25 Aug 2017 12:36:38 +0000 (+0200)
Subject: Remove deleted files
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0b104f4ae75fb1f23549a29949da7c23472f54a7;p=logicbox.git

Remove deleted files
---

diff --git a/cores/flash.ipx b/cores/flash.ipx
deleted file mode 100644
index f076aa3..0000000
--- a/cores/flash.ipx
+++ /dev/null
@@ -1,8 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="flash" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 09 29 10:00:22.906" version="1.2" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-		<File name="flash.lpc" type="lpc" modified="2016 09 29 10:00:20.000"/>
-		<File name="flash.vhd" type="top_level_vhdl" modified="2016 09 29 10:00:20.000"/>
-		<File name="flash_tmpl.vhd" type="template_vhdl" modified="2016 09 29 10:00:20.000"/>
-  </Package>
-</DiamondModule>
diff --git a/cores/flash.lpc b/cores/flash.lpc
deleted file mode 100644
index 6413b1b..0000000
--- a/cores/flash.lpc
+++ /dev/null
@@ -1,90 +0,0 @@
-[Device]
-Family=machxo3lf
-PartType=LCMXO3LF-2100E
-PartName=LCMXO3LF-2100E-5UWG49CTR
-SpeedGrade=5
-Package=WLCSP49
-OperatingCondition=COM
-Status=S
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=EFB
-CoreRevision=1.2
-ModuleName=flash
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=09/29/2016
-Time=10:00:20
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-freq=
-i2c1=0
-i2c1config=0
-i2c1_addr=7-Bit Addressing
-i2c1_ce=0
-i2c1_freq=100
-i2c1_sa=10000
-i2c1_we=0
-i2c2=0
-i2c2_addr=7-Bit Addressing
-i2c2_ce=0
-i2c2_freq=100
-i2c2_sa=10000
-i2c2_we=0
-ufm_addr=7-Bit Addressing
-ufm_sa=10000
-pll=0
-pll_cnt=1
-spi=0
-spi_clkinv=0
-spi_cs=1
-spi_en=0
-spi_freq=1
-spi_lsb=0
-spi_mode=Slave
-spi_ib=0
-spi_ph=0
-spi_hs=0
-spi_rxo=0
-spi_rxr=0
-spi_txo=0
-spi_txr=0
-spi_we=0
-static_tc=Static
-tc=0
-tc_clkinv=Positive
-tc_ctr=1
-tc_div=1
-tc_ipcap=0
-tc_mode=CTCM
-tc_ocr=32767
-tc_oflow=1
-tc_o=TOGGLE
-tc_opcomp=0
-tc_osc=0
-tc_sa_oflow=0
-tc_top=65535
-ufm=1
-wb_clk_freq=33.33
-ufm_usage=SHARED_EBR_TAG
-ufm_ebr=629
-ufm_remain=
-mem_size=10
-ufm_start=
-ufm_init=0
-memfile=
-ufm_dt=hex
-wb=1
-
-[Command]
-cmd_line= -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.33 -ufm -ufm_ebr 629 -mem_size 10 -ufm_0 -wb -dev 2100
diff --git a/cores/flashram.ipx b/cores/flashram.ipx
deleted file mode 100644
index cb30b85..0000000
--- a/cores/flashram.ipx
+++ /dev/null
@@ -1,10 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="flashram" module="RAM_DP_TRUE" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 04 25 12:05:46.515" version="7.5" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-		<File name="" type="mem" modified="2016 04 25 12:05:46.000"/>
-		<File name="flashram.lpc" type="lpc" modified="2016 04 25 12:05:43.000"/>
-		<File name="flashram.vhd" type="top_level_vhdl" modified="2016 04 25 12:05:43.000"/>
-		<File name="flashram_tmpl.vhd" type="template_vhdl" modified="2016 04 25 12:05:43.000"/>
-		<File name="tb_flashram_tmpl.vhd" type="testbench_vhdl" modified="2016 04 25 12:05:43.000"/>
-  </Package>
-</DiamondModule>
diff --git a/cores/flashram.lpc b/cores/flashram.lpc
deleted file mode 100644
index d996912..0000000
--- a/cores/flashram.lpc
+++ /dev/null
@@ -1,56 +0,0 @@
-[Device]
-Family=machxo3lf
-PartType=LCMXO3LF-1300C
-PartName=LCMXO3LF-1300C-5BG256C
-SpeedGrade=5
-Package=CABGA256
-OperatingCondition=COM
-Status=S
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=RAM_DP_TRUE
-CoreRevision=7.5
-ModuleName=flashram
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/25/2016
-Time=12:05:43
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-RAddress=16
-RData=8
-WAddress=16
-WData=8
-ROutputEn=0
-RClockEn=0
-WOutputEn=0
-WClockEn=0
-enByte=0
-ByteSize=9
-Optimization=Area
-Reset=Sync
-Reset1=Sync
-Init=0
-MemFile=
-MemFormat=bin
-EnECC=0
-Pipeline=0
-WriteA=Normal
-WriteB=Normal
-init_data=0
-
-[FilesGenerated]
-=mem
-
-[Command]
-cmd_line= -w -n flashram -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo3c00f -type ramdp -device LCMXO3LF-1300C -aaddr_width 4 -widtha 8 -baddr_width 4 -widthb 8 -anum_words 16 -bnum_words 16 -cascade 11 -mem_init0 -writemodeA NORMAL -writemodeB NORMAL