From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Mon, 22 Apr 2013 17:04:34 +0000 (+0200)
Subject: Integrate another trigger recv, but still use MBS VULOM by default
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0b50396a9f381edd49bd0c216eef59fe54ff6e43;p=trb3.git

Integrate another trigger recv, but still use MBS VULOM by default
---

diff --git a/cts/config.vhd b/cts/config.vhd
index 9bb800a..6e708ce 100644
--- a/cts/config.vhd
+++ b/cts/config.vhd
@@ -19,7 +19,11 @@ package config is
     
 --Run wih 125 MHz instead of 100 MHz     
     constant USE_125_MHZ : integer range c_NO to c_YES := c_YES;    
-   
+
+--Which external trigger module (ETM) to use?
+    type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2);
+    constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
+    
 ------------------------------------------------------------------------------
 --End of configuration
 ------------------------------------------------------------------------------
@@ -100,4 +104,4 @@ package body config is
   constant IS_UPLINK_ONLY       : hub_ct  := IS_UPLINK_ONLY_ARR(CFG_MODE); 
   
   
-end package body;
\ No newline at end of file
+end package body;
diff --git a/cts/source/cts_pkg.vhd b/cts/source/cts_pkg.vhd
index 094652f..a410e24 100755
--- a/cts/source/cts_pkg.vhd
+++ b/cts/source/cts_pkg.vhd
@@ -125,6 +125,24 @@ package cts_pkg is
       DEBUG          : out std_logic_vector(31 downto 0)    
       );
    end component;   
+
+   component mainz_a2_recv is
+		 port (
+			 CLK						: in	std_logic;
+			 RESET_IN				: in	std_logic;
+			 SERIAL_IN			: in	std_logic;
+			 EXT_TRG_IN			: in	std_logic;
+			 TRG_ASYNC_OUT	: out std_logic;
+			 TRG_SYNC_OUT		: out std_logic;
+			 TRIGGER_IN			: in	std_logic;
+			 DATA_OUT				: out std_logic_vector(31 downto 0);
+			 WRITE_OUT			: out std_logic;
+			 STATUSBIT_OUT	: out std_logic_vector(31 downto 0);
+			 FINISHED_OUT		: out std_logic;
+			 CONTROL_REG_IN : in	std_logic_vector(31 downto 0);
+			 STATUS_REG_OUT : out std_logic_vector(31 downto 0) := (others => '0');
+			 DEBUG					: out std_logic_vector(31 downto 0));
+	 end component mainz_a2_recv;
    
    component CTS_TRIGGER is
       generic (
diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj
index d3d6a6e..37a1cc8 100644
--- a/cts/trb3_central.prj
+++ b/cts/trb3_central.prj
@@ -62,6 +62,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
 add_file -vhdl -lib work "../base/trb3_components.vhd"
 add_file -vhdl -lib work "../base/code/mbs_vulom_recv.vhd"
+add_file -vhdl -lib work "../base/code/mainz_a2_recv.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd
index 753722e..0a00bd3 100644
--- a/cts/trb3_central.vhd
+++ b/cts/trb3_central.vhd
@@ -407,7 +407,8 @@ architecture trb3_central_arch of trb3_central is
 
 begin
 -- MBS Module
- THE_MBS: entity work.mbs_vulom_recv
+	gen_mbs_vulom_as_etm : if ETM_CHOICE = ETM_CHOICE_MBS_VULOM generate
+	THE_MBS: entity work.mbs_vulom_recv
    port map (
       CLK => clk_100_i,
       RESET_IN => reset_i,
@@ -429,13 +430,38 @@ begin
       
       DEBUG => cts_ext_debug
    );
-
+	end generate;
+
+	gen_mainz_a2_as_etm: if ETM_CHOICE = ETM_CHOICE_MAINZ_A2 generate
+		mainz_a2_recv_1: entity work.mainz_a2_recv
+			port map (
+				CLK						 => clk_100_i,
+				RESET_IN			 => reset_i,
+				SERIAL_IN			 => CLK_EXT(3),
+				EXT_TRG_IN		 => CLK_EXT(4),
+				--TRG_ASYNC_OUT	 => TRG_ASYNC_OUT,
+				TRG_SYNC_OUT	 => cts_ext_trigger,
+				TRIGGER_IN     => cts_rdo_trg_data_valid,
+				DATA_OUT       => cts_rdo_additional_data(31 downto 0),
+				WRITE_OUT      => cts_rdo_additional_write(0),
+				STATUSBIT_OUT  => cts_rdo_trg_status_bits_additional(31 downto 0),
+				FINISHED_OUT   => cts_rdo_additional_finished(0),
+
+				CONTROL_REG_IN => cts_ext_control,
+				STATUS_REG_OUT => cts_ext_status,
+				
+				DEBUG => cts_ext_debug
+				);
+	end generate;
+
+	
+	
    trigger_in_buf_i(1 downto 0) <= CLK_EXT;
    trigger_in_buf_i(3 downto 2) <= TRIGGER_EXT(3 downto 2);
 
  THE_CTS: CTS 
    generic map (
-      EXTERNAL_TRIGGER_ID  => X"60", --, fill in trigger logic enumeration id of external trigger logic
+      EXTERNAL_TRIGGER_ID  => X"60"+ETM_CHOICE_type'pos(ETM_CHOICE), --, fill in trigger logic enumeration id of external trigger logic
       TRIGGER_INPUT_COUNT  => 4,
       TRIGGER_COIN_COUNT   => 4,
       TRIGGER_PULSER_COUNT => 4,