From: hadeshyp <hadeshyp>
Date: Thu, 4 Oct 2012 12:08:29 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0b75e5449b71f686ba8c0457f5217e3bdd1612cb;p=trb3.git

*** empty log message ***
---

diff --git a/base/code/mbs_vulom_recv.vhd b/base/code/mbs_vulom_recv.vhd
index 7d6f7f2..b9e37bb 100644
--- a/base/code/mbs_vulom_recv.vhd
+++ b/base/code/mbs_vulom_recv.vhd
@@ -91,11 +91,11 @@ end process;
   
 first_bits_slow <= first_bits_fast when rising_edge(CLK);
 
-trg_async     <= not MBS_IN or trg_async when first_bits_fast = '1' else '0';
-trg_sync      <= not reg_MBS_IN or trg_sync when rising_edge(CLK) and first_bits_slow ='1' else '0';
+trg_async     <= (not MBS_IN or trg_async) when first_bits_fast = '1' else '0';
+trg_sync      <= (not reg_MBS_IN or trg_sync) and first_bits_slow when rising_edge(CLK);
 
 TRG_ASYNC_OUT <= trg_async;
-TRG_SYNC_OUT  <= trg_sync;
+TRG_SYNC_OUT  <= trg_sync when rising_edge(CLK);
 
 PROC_FSM: process begin
   wait until rising_edge(CLK_200);
@@ -161,4 +161,7 @@ PROC_RDO : process begin
   end case;
 end process;
 
+STATUS_REG_OUT <= error_reg & '0' & std_logic_vector(to_unsigned(bitcnt,6)) & number_reg;
+
+
 end architecture;
\ No newline at end of file