From: Benedikt Gutsche Date: Wed, 10 Jan 2024 14:59:28 +0000 (+0100) Subject: corrected top level file X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0c8fe620507fc14970861ba9c9e48298e3bc4aa1;p=trb5sc.git corrected top level file --- diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd index abac92e..1f7e0ce 100644 --- a/mimosis/trb5sc_mimosis.vhd +++ b/mimosis/trb5sc_mimosis.vhd @@ -28,11 +28,11 @@ entity trb5sc_mimosis is SFP_MOD_0 : in std_logic; --AddOn --- FE_GPIO : inout std_logic_vector(11 downto 0); --- FE_CLK : out std_logic_vector( 2 downto 1); --- FE_DIFF : inout std_logic_vector(63 downto 0); - --INP : inout std_logic_vector(63 downto 0); - --LED_ADDON : out std_logic_vector(5 downto 0); + -- FE_GPIO : inout std_logic_vector(11 downto 0); + -- FE_CLK : out std_logic_vector( 2 downto 1); + -- FE_DIFF : inout std_logic_vector(63 downto 0); + -- INP : inout std_logic_vector(63 downto 0); + -- LED_ADDON : out std_logic_vector(5 downto 0); LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); LED_ADDON_RJ : out std_logic_vector(1 downto 0); @@ -85,27 +85,25 @@ entity trb5sc_mimosis is HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only ); - attribute syn_useioff : boolean; attribute syn_useioff of FLASH_NCS : signal is true; attribute syn_useioff of FLASH_SCLK : signal is true; attribute syn_useioff of FLASH_MOSI : signal is true; attribute syn_useioff of FLASH_MISO : signal is true; - end entity; architecture arch of trb5sc_mimosis is + attribute syn_keep : boolean; attribute syn_preserve : boolean; - signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40 : std_logic; + signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40, clk_80 : std_logic; signal GSR_N : std_logic; signal reset_i : std_logic; signal clear_i : std_logic; signal trigger_in_i : std_logic; - attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -123,8 +121,8 @@ architecture arch of trb5sc_mimosis is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); - signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX; - signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbtcore_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbtcore_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -145,7 +143,6 @@ architecture arch of trb5sc_mimosis is signal inp_i : std_logic_vector( 7 downto 0); signal gbe_status : std_logic_vector(15 downto 0); - signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); signal i2c_reg_2 : std_logic_vector(31 downto 0); signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); @@ -153,6 +150,7 @@ architecture arch of trb5sc_mimosis is signal i2c_go_100, i2c_go : std_logic; signal i2c_reg_5_40 : std_logic_vector(31 downto 0); signal counter : unsigned(23 downto 0); + --signal fwd_dst_mac : std_logic_vector(47 downto 0); --signal fwd_dst_ip : std_logic_vector(31 downto 0); --signal fwd_dst_port : std_logic_vector(15 downto 0); @@ -167,9 +165,7 @@ architecture arch of trb5sc_mimosis is begin - -trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); - + trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); --------------------------------------------------------------------------- -- Clock & Reset Handling @@ -195,17 +191,17 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no ); + THE_160_PLL : entity work.pll_200_160 + port map( + CLKI => clk_full_osc, + CLKOP => clk_160, + CLKOS => clk_320, + CLKOS2=> clk_40, + CLKOS3=> clk_80 + ); -THE_160_PLL : entity work.pll_200_160 - port map( - CLKI => clk_full_osc, - CLKOP => clk_160, - CLKOS => clk_320, - CLKOS2=> clk_40 - ); - -H5(3) <= clk_320; -RJ(0) <= clk_40; + H5(3) <= clk_320; + RJ(0) <= clk_40; --------------------------------------------------------------------------- -- TrbNet Uplink @@ -315,7 +311,6 @@ RJ(0) <= clk_40; --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- - THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( PORT_NUMBER => 5, @@ -335,17 +330,19 @@ RJ(0) <= clk_40; BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => busmimosis_rx, BUS_RX(4) => busi2c_rx, - --BUS_RX(5) => busgbeip_rx, - --BUS_RX(6) => busgbereg_rx, - --BUS_RX(7) => busfwd_rx, + BUS_RX(5) => busgbtcore_rx, + -- BUS_RX(5) => busgbeip_rx, + -- BUS_RX(6) => busgbereg_rx, + -- BUS_RX(7) => busfwd_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busmimosis_tx, BUS_TX(4) => busi2c_tx, - --BUS_TX(5) => busgbeip_tx, - --BUS_TX(6) => busgbereg_tx, - --BUS_TX(7) => busfwd_tx, + BUS_TX(5) => busgbtcore_tx, + -- BUS_TX(5) => busgbeip_tx, + -- BUS_TX(6) => busgbereg_tx, + -- BUS_TX(7) => busfwd_tx, STAT_DEBUG => open ); @@ -403,12 +400,12 @@ RJ(0) <= clk_40; DEBUG_OUT => debug_tools ); ---counter <= counter + '1' when rising_edge(clk_sys); ---HDR_IO <= std_logic_vector(counter(15 downto 0)); ---LED <= std_logic_vector(counter(23 downto 16)); + -- counter <= counter + '1' when rising_edge(clk_sys); + -- HDR_IO <= std_logic_vector(counter(15 downto 0)); + -- LED <= std_logic_vector(counter(23 downto 16)); - --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z'; - --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z'; + -- COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z'; + -- COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z'; FLASH_HOLD <= '1'; FLASH_WP <= '1'; @@ -416,91 +413,92 @@ RJ(0) <= clk_40; --------------------------------------------------------------------------- -- I2C --------------------------------------------------------------------------- -THE_I2C : entity work.i2c_slim2 - port map( - CLOCK => clk_40, - RESET => reset_i, - -- I2C command / setup - I2C_GO_IN => i2c_go, - ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read - WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word - DIRECT_IN => i2c_reg_1(4), -- don't send command - I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) - I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) - I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) - I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command - I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command - STATUS_OUT => i2c_reg_4(23 downto 16), - VALID_OUT => i2c_reg_4(31), - I2C_BUSY_OUT => i2c_reg_4(30), - I2C_DONE_OUT => i2c_reg_4(29), - -- I2C connections - SDA_IN => PIN(4), - SDA_OUT => mimosis_sda_drv, - SCL_IN => PIN(3), - SCL_OUT => mimosis_scl_drv, - -- Debug - BSM_OUT => i2c_reg_4(27 downto 24) -); + THE_I2C : entity work.i2c_slim2 + port map( + CLOCK => clk_40, + RESET => reset_i, + -- I2C command / setup + I2C_GO_IN => i2c_go, + ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read + WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word + DIRECT_IN => i2c_reg_1(4), -- don't send command + I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) + I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) + I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command + I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command + STATUS_OUT => i2c_reg_4(23 downto 16), + VALID_OUT => i2c_reg_4(31), + I2C_BUSY_OUT => i2c_reg_4(30), + I2C_DONE_OUT => i2c_reg_4(29), + -- I2C connections + SDA_IN => PIN(4), + SDA_OUT => mimosis_sda_drv, + SCL_IN => PIN(3), + SCL_OUT => mimosis_scl_drv, + -- Debug + BSM_OUT => i2c_reg_4(27 downto 24) + ); -- I2C signal open collector driver -- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; -- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; -PIN(4) <= MIMOSIS_SDA; -PIN(3) <= MIMOSIS_SCL; -MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z'; -MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z'; - -H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC -PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START -PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET - -PROC_I2C_REGS : process begin - wait until rising_edge(CLK_SYS); - busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '0'; - busi2c_tx.nack <= '0'; - busi2c_tx.data <= (others => '0'); - i2c_go_100 <= '0'; - - if busi2c_rx.write = '1' then - busi2c_tx.ack <= '1'; - if busi2c_rx.addr(3 downto 0) = x"0" then - i2c_reg_0 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"1" then - i2c_reg_1 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"2" then - i2c_reg_2 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"3" then - i2c_go_100 <= busi2c_rx.data(0); - elsif busi2c_rx.addr(3 downto 0) = x"5" then - i2c_reg_5 <= busi2c_rx.data; - else - busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '1'; - end if; - elsif busi2c_rx.read = '1' then - busi2c_tx.ack <= '1'; - if busi2c_rx.addr(3 downto 0) = x"0" then - busi2c_tx.data <= i2c_reg_0; - elsif busi2c_rx.addr(3 downto 0) = x"1" then - busi2c_tx.data <= i2c_reg_1; - elsif busi2c_rx.addr(3 downto 0) = x"2" then - busi2c_tx.data <= i2c_reg_2; - elsif busi2c_rx.addr(3 downto 0) = x"3" then - busi2c_tx.data <= (others => '0'); - elsif busi2c_rx.addr(3 downto 0) = x"4" then - busi2c_tx.data <= i2c_reg_4; - elsif busi2c_rx.addr(3 downto 0) = x"5" then - busi2c_tx.data <= i2c_reg_5; - else - busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '1'; + PIN(4) <= MIMOSIS_SDA; + PIN(3) <= MIMOSIS_SCL; + MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z'; + MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z'; + + H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC + PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START + PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET + PROC_I2C_REGS : process + begin + wait until rising_edge(CLK_SYS); + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '0'; + busi2c_tx.nack <= '0'; + busi2c_tx.data <= (others => '0'); + i2c_go_100 <= '0'; + + if busi2c_rx.write = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + i2c_reg_0 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + i2c_reg_1 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + i2c_reg_2 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + i2c_go_100 <= busi2c_rx.data(0); + elsif busi2c_rx.addr(3 downto 0) = x"5" then + i2c_reg_5 <= busi2c_rx.data; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + end if; + elsif busi2c_rx.read = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + busi2c_tx.data <= i2c_reg_0; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + busi2c_tx.data <= i2c_reg_1; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + busi2c_tx.data <= i2c_reg_2; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + busi2c_tx.data <= (others => '0'); + elsif busi2c_rx.addr(3 downto 0) = x"4" then + busi2c_tx.data <= i2c_reg_4; + elsif busi2c_rx.addr(3 downto 0) = x"5" then + busi2c_tx.data <= i2c_reg_5; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + + end if; end if; - end if; -end process; + end process; THE_I2C_GO_SYNC : pulse_sync port map( @@ -510,21 +508,20 @@ end process; CLK_B_IN => clk_40, RESET_B_IN => reset_i, PULSE_B_OUT => i2c_go - ); - - THE_MIMOSIS_SIGNAL_SYNC : signal_sync - generic map( - WIDTH => 32, - DEPTH => 2 - ) - port map( - RESET => reset_i, - CLK0 => clk_sys, - CLK1 => clk_40, - D_IN => i2c_reg_5, - D_OUT => i2c_reg_5_40 - ); + ); + THE_MIMOSIS_SIGNAL_SYNC : signal_sync + generic map( + WIDTH => 32, + DEPTH => 2 + ) + port map( + RESET => reset_i, + CLK0 => clk_sys, + CLK1 => clk_40, + D_IN => i2c_reg_5, + D_OUT => i2c_reg_5_40 + ); --------------------------------------------------------------------------- @@ -556,97 +553,97 @@ end process; ---- GbE ----------------------------------------------------------------------------- --GBE : entity work.gbe_wrapper - --generic map( - --DO_SIMULATION => 0, - --INCLUDE_DEBUG => 0, - --USE_INTERNAL_TRBNET_DUMMY => 0, - --USE_EXTERNAL_TRBNET_DUMMY => 0, - --RX_PATH_ENABLE => 1, - --FIXED_SIZE_MODE => 1, - --INCREMENTAL_MODE => 1, - --FIXED_SIZE => 100, - --FIXED_DELAY_MODE => 1, - --UP_DOWN_MODE => 0, - --UP_DOWN_LIMIT => 100, - --FIXED_DELAY => 100, - - --NUMBER_OF_GBE_LINKS => 1, - --LINKS_ACTIVE => "0001", - - --LINK_HAS_READOUT => "0000", - --LINK_HAS_SLOWCTRL => "0000", - --LINK_HAS_DHCP => "0001", - --LINK_HAS_ARP => "0001", - --LINK_HAS_PING => "0001", - --LINK_HAS_FWD => "0001" - --) - --port map( - --CLK_SYS_IN => clk_sys, - --CLK_125_IN => CLK_125, - --RESET => reset_i, - --GSR_N => GSR_N, - ---- Trigger - --TRIGGER_IN => '0', - ---- SFP - --SD_PRSNT_N_IN(0) => SFP_MOD_0, - --SD_LOS_IN(0) => SFP_LOS, - --SD_TXDIS_OUT(0) => SFP_TX_DIS, - ---- trigger channel - ---- only for LINK_HAS_READOUT - --CTS_NUMBER_IN => (others => '0'), - --CTS_CODE_IN => (others => '0'), - --CTS_INFORMATION_IN => (others => '0'), - --CTS_READOUT_TYPE_IN => (others => '0'), - --CTS_START_READOUT_IN => '0', - --CTS_DATA_OUT => open, - --CTS_DATAREADY_OUT => open, - --CTS_READOUT_FINISHED_OUT => open, - --CTS_READ_IN => '1', - --CTS_LENGTH_OUT => open, - --CTS_ERROR_PATTERN_OUT => open, - ---- data channel - ---- only for LINK_HAS_READOUT - --FEE_DATA_IN => (others => '0'), - --FEE_DATAREADY_IN => '0', - --FEE_READ_OUT => open, - --FEE_STATUS_BITS_IN => (others => '0'), - --FEE_BUSY_IN => '0', - ---- unique adresses - --MC_UNIQUE_ID_IN => timer.uid, - --MY_TRBNET_ADDRESS_IN => timer.network_address, - --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected - ---- slow control by GbE - --GSC_CLK_IN => open, - --GSC_INIT_DATAREADY_OUT => open, - --GSC_INIT_DATA_OUT => open, - --GSC_INIT_PACKET_NUM_OUT => open, - --GSC_INIT_READ_IN => '1', - --GSC_REPLY_DATAREADY_IN => '0', - --GSC_REPLY_DATA_IN => (others => '0'), - --GSC_REPLY_PACKET_NUM_IN => (others => '0'), - --GSC_REPLY_READ_OUT => open, - --GSC_BUSY_IN => '0', - ---- readout - --BUS_IP_RX => busgbeip_rx, -- registers inside GbE - --BUS_IP_TX => busgbeip_tx, -- registers inside GbE - --BUS_REG_RX => busgbereg_rx, -- registers inside GbE - --BUS_REG_TX => busgbereg_tx, -- registers inside GbE - ---- Forwarder - --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac, - --FWD_DST_IP_IN(31 downto 0) => fwd_dst_ip, - --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port, - --FWD_DATA_IN(7 downto 0) => fwd_data, - --FWD_DATA_VALID_IN(0) => fwd_datavalid, - --FWD_SOP_IN(0) => fwd_sop, - --FWD_EOP_IN(0) => fwd_eop, - --FWD_READY_OUT(0) => fwd_ready, - --FWD_FULL_OUT(0) => fwd_full, - ---- reset - --MAKE_RESET_OUT => open, -- reset by GbE --BUG: needs to be connected - ---- debug and status - --STATUS_OUT => open, - --DEBUG_OUT => open - --); + --generic map( + --DO_SIMULATION => 0, + --INCLUDE_DEBUG => 0, + --USE_INTERNAL_TRBNET_DUMMY => 0, + --USE_EXTERNAL_TRBNET_DUMMY => 0, + --RX_PATH_ENABLE => 1, + --FIXED_SIZE_MODE => 1, + --INCREMENTAL_MODE => 1, + --FIXED_SIZE => 100, + --FIXED_DELAY_MODE => 1, + --UP_DOWN_MODE => 0, + --UP_DOWN_LIMIT => 100, + --FIXED_DELAY => 100, + + --NUMBER_OF_GBE_LINKS => 1, + --LINKS_ACTIVE => "0001", + + --LINK_HAS_READOUT => "0000", + --LINK_HAS_SLOWCTRL => "0000", + --LINK_HAS_DHCP => "0001", + --LINK_HAS_ARP => "0001", + --LINK_HAS_PING => "0001", + --LINK_HAS_FWD => "0001" + --) + --port map( + --CLK_SYS_IN => clk_sys, + --CLK_125_IN => CLK_125, + --RESET => reset_i, + --GSR_N => GSR_N, + ---- Trigger + --TRIGGER_IN => '0', + ---- SFP + --SD_PRSNT_N_IN(0) => SFP_MOD_0, + --SD_LOS_IN(0) => SFP_LOS, + --SD_TXDIS_OUT(0) => SFP_TX_DIS, + ---- trigger channel + ---- only for LINK_HAS_READOUT + --CTS_NUMBER_IN => (others => '0'), + --CTS_CODE_IN => (others => '0'), + --CTS_INFORMATION_IN => (others => '0'), + --CTS_READOUT_TYPE_IN => (others => '0'), + --CTS_START_READOUT_IN => '0', + --CTS_DATA_OUT => open, + --CTS_DATAREADY_OUT => open, + --CTS_READOUT_FINISHED_OUT => open, + --CTS_READ_IN => '1', + --CTS_LENGTH_OUT => open, + --CTS_ERROR_PATTERN_OUT => open, + ---- data channel + ---- only for LINK_HAS_READOUT + --FEE_DATA_IN => (others => '0'), + --FEE_DATAREADY_IN => '0', + --FEE_READ_OUT => open, + --FEE_STATUS_BITS_IN => (others => '0'), + --FEE_BUSY_IN => '0', + ---- unique adresses + --MC_UNIQUE_ID_IN => timer.uid, + --MY_TRBNET_ADDRESS_IN => timer.network_address, + --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected + ---- slow control by GbE + --GSC_CLK_IN => open, + --GSC_INIT_DATAREADY_OUT => open, + --GSC_INIT_DATA_OUT => open, + --GSC_INIT_PACKET_NUM_OUT => open, + --GSC_INIT_READ_IN => '1', + --GSC_REPLY_DATAREADY_IN => '0', + --GSC_REPLY_DATA_IN => (others => '0'), + --GSC_REPLY_PACKET_NUM_IN => (others => '0'), + --GSC_REPLY_READ_OUT => open, + --GSC_BUSY_IN => '0', + ---- readout + --BUS_IP_RX => busgbeip_rx, -- registers inside GbE + --BUS_IP_TX => busgbeip_tx, -- registers inside GbE + --BUS_REG_RX => busgbereg_rx, -- registers inside GbE + --BUS_REG_TX => busgbereg_tx, -- registers inside GbE + ---- Forwarder + --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac, + --FWD_DST_IP_IN(31 downto 0) => fwd_dst_ip, + --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port, + --FWD_DATA_IN(7 downto 0) => fwd_data, + --FWD_DATA_VALID_IN(0) => fwd_datavalid, + --FWD_SOP_IN(0) => fwd_sop, + --FWD_EOP_IN(0) => fwd_eop, + --FWD_READY_OUT(0) => fwd_ready, + --FWD_FULL_OUT(0) => fwd_full, + ---- reset + --MAKE_RESET_OUT => open, -- reset by GbE --BUG: needs to be connected + ---- debug and status + --STATUS_OUT => open, + --DEBUG_OUT => open + --); @@ -660,30 +657,30 @@ end process; --busfwd_tx.unknown <= '0'; --if busfwd_rx.write = '1' then - --busfwd_tx.ack <= '1'; - --case busfwd_rx.addr(7 downto 0) is - --when x"00" => fwd_dst_ip <= busfwd_rx.data; - --when x"01" => fwd_dst_port <= busfwd_rx.data(15 downto 0); - --when x"02" => fwd_dst_mac(31 downto 0) <= busfwd_rx.data; - --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0); - --when x"04" => fwd_length <= busfwd_rx.data(15 downto 0); - --when x"05" => fwd_do_send <= busfwd_rx.data(0); - --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; - --end case; + --busfwd_tx.ack <= '1'; + --case busfwd_rx.addr(7 downto 0) is + --when x"00" => fwd_dst_ip <= busfwd_rx.data; + --when x"01" => fwd_dst_port <= busfwd_rx.data(15 downto 0); + --when x"02" => fwd_dst_mac(31 downto 0) <= busfwd_rx.data; + --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0); + --when x"04" => fwd_length <= busfwd_rx.data(15 downto 0); + --when x"05" => fwd_do_send <= busfwd_rx.data(0); + --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; + --end case; --elsif busfwd_rx.read = '1' then - --busfwd_tx.ack <= '1'; - --case busfwd_rx.addr(7 downto 0) is - --when x"00" => busfwd_tx.data <= fwd_dst_ip; - --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port; - --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0); - --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32); - --when x"04" => busfwd_tx.data <= x"0000" & fwd_length; - --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send; - --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; - --end case; + --busfwd_tx.ack <= '1'; + --case busfwd_rx.addr(7 downto 0) is + --when x"00" => busfwd_tx.data <= fwd_dst_ip; + --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port; + --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0); + --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32); + --when x"04" => busfwd_tx.data <= x"0000" & fwd_length; + --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send; + --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; + --end case; --end if; --if reset_i = '1' then - --fwd_do_send <= '0'; + --fwd_do_send <= '0'; --end if; --end process; @@ -752,8 +749,5 @@ end process; -- readout_tx(0).data_write <= '0'; -- readout_tx(0).busy_release <= '1'; -SFP_ADDON_TX_DIS <= (others => '0'); + SFP_ADDON_TX_DIS <= (others => '0'); end architecture; - - - diff --git a/vldb/trb5sc_mimosis.vhd b/vldb/trb5sc_mimosis.vhd index 2e1123a..5a3bdd0 100644 --- a/vldb/trb5sc_mimosis.vhd +++ b/vldb/trb5sc_mimosis.vhd @@ -28,11 +28,11 @@ entity trb5sc_mimosis is SFP_MOD_0 : in std_logic; --AddOn - --FE_GPIO : inout std_logic_vector(11 downto 0); - --FE_CLK : out std_logic_vector( 2 downto 1); - --FE_DIFF : inout std_logic_vector(63 downto 0); - --INP : inout std_logic_vector(63 downto 0); - --LED_ADDON : out std_logic_vector(5 downto 0); + -- FE_GPIO : inout std_logic_vector(11 downto 0); + -- FE_CLK : out std_logic_vector( 2 downto 1); + -- FE_DIFF : inout std_logic_vector(63 downto 0); + -- INP : inout std_logic_vector(63 downto 0); + -- LED_ADDON : out std_logic_vector(5 downto 0); LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); LED_ADDON_RJ : out std_logic_vector(1 downto 0); @@ -70,11 +70,6 @@ entity trb5sc_mimosis is I2C_SCL : inout std_logic; TMP_ALERT : in std_logic; - --GBTSCA - SCA_RX : in std_logic_vector(1 downto 0); - SCA_TX : out std_logic_vector(1 downto 0); - SCA_CLK : out std_logic_vector(1 downto 0); - --LED LED : out std_logic_vector(8 downto 1); LED_SFP_YELLOW : out std_logic; @@ -98,7 +93,6 @@ entity trb5sc_mimosis is end entity; - architecture arch of trb5sc_mimosis is attribute syn_keep : boolean; @@ -171,10 +165,8 @@ architecture arch of trb5sc_mimosis is begin - trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); - --------------------------------------------------------------------------- -- Clock & Reset Handling --------------------------------------------------------------------------- @@ -198,6 +190,7 @@ begin DEBUG_OUT => debug_clock_reset ); + THE_160_PLL : entity work.pll_200_160 port map( CLKI => clk_full_osc, @@ -210,7 +203,6 @@ begin H5(3) <= clk_320; RJ(0) <= clk_40; - --------------------------------------------------------------------------- -- TrbNet Uplink --------------------------------------------------------------------------- @@ -321,7 +313,7 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 5, + PORT_NUMBER => 6, PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"), PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0), PORT_MASK_ENABLE => 1 @@ -337,8 +329,8 @@ begin BUS_RX(1) => bussci_rx, --SCI Serdes BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => busmimosis_rx, - BUS_RX(4) => busgbtcore_rx, - -- BUS_RX(4) => busi2c_rx, + BUS_RX(4) => busi2c_rx, + BUS_RX(5) => busgbtcore_rx, -- BUS_RX(5) => busgbeip_rx, -- BUS_RX(6) => busgbereg_rx, -- BUS_RX(7) => busfwd_rx, @@ -346,8 +338,8 @@ begin BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busmimosis_tx, - BUS_TX(4) => busgbtcore_tx, - -- BUS_TX(4) => busi2c_tx, + BUS_TX(4) => busi2c_tx, + BUS_TX(5) => busgbtcore_tx, -- BUS_TX(5) => busgbeip_tx, -- BUS_TX(6) => busgbereg_tx, -- BUS_TX(7) => busfwd_tx, @@ -408,16 +400,129 @@ begin DEBUG_OUT => debug_tools ); ---counter <= counter + '1' when rising_edge(clk_sys); ---HDR_IO <= std_logic_vector(counter(15 downto 0)); ---LED <= std_logic_vector(counter(23 downto 16)); + -- counter <= counter + '1' when rising_edge(clk_sys); + -- HDR_IO <= std_logic_vector(counter(15 downto 0)); + -- LED <= std_logic_vector(counter(23 downto 16)); - --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z'; - --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z'; + -- COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z'; + -- COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z'; FLASH_HOLD <= '1'; FLASH_WP <= '1'; +--------------------------------------------------------------------------- +-- I2C +--------------------------------------------------------------------------- + THE_I2C : entity work.i2c_slim2 + port map( + CLOCK => clk_40, + RESET => reset_i, + -- I2C command / setup + I2C_GO_IN => i2c_go, + ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read + WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word + DIRECT_IN => i2c_reg_1(4), -- don't send command + I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) + I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) + I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command + I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command + STATUS_OUT => i2c_reg_4(23 downto 16), + VALID_OUT => i2c_reg_4(31), + I2C_BUSY_OUT => i2c_reg_4(30), + I2C_DONE_OUT => i2c_reg_4(29), + -- I2C connections + SDA_IN => PIN(4), + SDA_OUT => mimosis_sda_drv, + SCL_IN => PIN(3), + SCL_OUT => mimosis_scl_drv, + -- Debug + BSM_OUT => i2c_reg_4(27 downto 24) + ); + +-- I2C signal open collector driver +-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; +-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; + + PIN(4) <= MIMOSIS_SDA; + PIN(3) <= MIMOSIS_SCL; + MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z'; + MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z'; + + H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC + PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START + PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET + + PROC_I2C_REGS : process + begin + wait until rising_edge(CLK_SYS); + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '0'; + busi2c_tx.nack <= '0'; + busi2c_tx.data <= (others => '0'); + i2c_go_100 <= '0'; + + if busi2c_rx.write = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + i2c_reg_0 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + i2c_reg_1 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + i2c_reg_2 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + i2c_go_100 <= busi2c_rx.data(0); + elsif busi2c_rx.addr(3 downto 0) = x"5" then + i2c_reg_5 <= busi2c_rx.data; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + end if; + elsif busi2c_rx.read = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + busi2c_tx.data <= i2c_reg_0; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + busi2c_tx.data <= i2c_reg_1; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + busi2c_tx.data <= i2c_reg_2; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + busi2c_tx.data <= (others => '0'); + elsif busi2c_rx.addr(3 downto 0) = x"4" then + busi2c_tx.data <= i2c_reg_4; + elsif busi2c_rx.addr(3 downto 0) = x"5" then + busi2c_tx.data <= i2c_reg_5; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + + end if; + end if; + end process; + + THE_I2C_GO_SYNC : pulse_sync + port map( + CLK_A_IN => clk_sys, + RESET_A_IN => reset_i, + PULSE_A_IN => i2c_go_100, + CLK_B_IN => clk_40, + RESET_B_IN => reset_i, + PULSE_B_OUT => i2c_go + ); + + THE_MIMOSIS_SIGNAL_SYNC : signal_sync + generic map( + WIDTH => 32, + DEPTH => 2 + ) + port map( + RESET => reset_i, + CLK0 => clk_sys, + CLK1 => clk_40, + D_IN => i2c_reg_5, + D_OUT => i2c_reg_5_40 + ); + --------------------------------------------------------------------------- -- LED @@ -444,6 +549,178 @@ begin LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4)); LED_ADDON_SFP_ORANGE(1) <= '0'; +----------------------------------------------------------------------------- +---- GbE +----------------------------------------------------------------------------- + --GBE : entity work.gbe_wrapper + --generic map( + --DO_SIMULATION => 0, + --INCLUDE_DEBUG => 0, + --USE_INTERNAL_TRBNET_DUMMY => 0, + --USE_EXTERNAL_TRBNET_DUMMY => 0, + --RX_PATH_ENABLE => 1, + --FIXED_SIZE_MODE => 1, + --INCREMENTAL_MODE => 1, + --FIXED_SIZE => 100, + --FIXED_DELAY_MODE => 1, + --UP_DOWN_MODE => 0, + --UP_DOWN_LIMIT => 100, + --FIXED_DELAY => 100, + + --NUMBER_OF_GBE_LINKS => 1, + --LINKS_ACTIVE => "0001", + + --LINK_HAS_READOUT => "0000", + --LINK_HAS_SLOWCTRL => "0000", + --LINK_HAS_DHCP => "0001", + --LINK_HAS_ARP => "0001", + --LINK_HAS_PING => "0001", + --LINK_HAS_FWD => "0001" + --) + --port map( + --CLK_SYS_IN => clk_sys, + --CLK_125_IN => CLK_125, + --RESET => reset_i, + --GSR_N => GSR_N, + ---- Trigger + --TRIGGER_IN => '0', + ---- SFP + --SD_PRSNT_N_IN(0) => SFP_MOD_0, + --SD_LOS_IN(0) => SFP_LOS, + --SD_TXDIS_OUT(0) => SFP_TX_DIS, + ---- trigger channel + ---- only for LINK_HAS_READOUT + --CTS_NUMBER_IN => (others => '0'), + --CTS_CODE_IN => (others => '0'), + --CTS_INFORMATION_IN => (others => '0'), + --CTS_READOUT_TYPE_IN => (others => '0'), + --CTS_START_READOUT_IN => '0', + --CTS_DATA_OUT => open, + --CTS_DATAREADY_OUT => open, + --CTS_READOUT_FINISHED_OUT => open, + --CTS_READ_IN => '1', + --CTS_LENGTH_OUT => open, + --CTS_ERROR_PATTERN_OUT => open, + ---- data channel + ---- only for LINK_HAS_READOUT + --FEE_DATA_IN => (others => '0'), + --FEE_DATAREADY_IN => '0', + --FEE_READ_OUT => open, + --FEE_STATUS_BITS_IN => (others => '0'), + --FEE_BUSY_IN => '0', + ---- unique adresses + --MC_UNIQUE_ID_IN => timer.uid, + --MY_TRBNET_ADDRESS_IN => timer.network_address, + --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected + ---- slow control by GbE + --GSC_CLK_IN => open, + --GSC_INIT_DATAREADY_OUT => open, + --GSC_INIT_DATA_OUT => open, + --GSC_INIT_PACKET_NUM_OUT => open, + --GSC_INIT_READ_IN => '1', + --GSC_REPLY_DATAREADY_IN => '0', + --GSC_REPLY_DATA_IN => (others => '0'), + --GSC_REPLY_PACKET_NUM_IN => (others => '0'), + --GSC_REPLY_READ_OUT => open, + --GSC_BUSY_IN => '0', + ---- readout + --BUS_IP_RX => busgbeip_rx, -- registers inside GbE + --BUS_IP_TX => busgbeip_tx, -- registers inside GbE + --BUS_REG_RX => busgbereg_rx, -- registers inside GbE + --BUS_REG_TX => busgbereg_tx, -- registers inside GbE + ---- Forwarder + --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac, + --FWD_DST_IP_IN(31 downto 0) => fwd_dst_ip, + --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port, + --FWD_DATA_IN(7 downto 0) => fwd_data, + --FWD_DATA_VALID_IN(0) => fwd_datavalid, + --FWD_SOP_IN(0) => fwd_sop, + --FWD_EOP_IN(0) => fwd_eop, + --FWD_READY_OUT(0) => fwd_ready, + --FWD_FULL_OUT(0) => fwd_full, + ---- reset + --MAKE_RESET_OUT => open, -- reset by GbE --BUG: needs to be connected + ---- debug and status + --STATUS_OUT => open, + --DEBUG_OUT => open + --); + + + +----------------------------------------------------------------------------- +---- Test registers +----------------------------------------------------------------------------- +--THE_REGS : process begin + --wait until rising_edge(clk_sys); + --busfwd_tx.ack <= '0'; + --busfwd_tx.nack <= '0'; + --busfwd_tx.unknown <= '0'; + + --if busfwd_rx.write = '1' then + --busfwd_tx.ack <= '1'; + --case busfwd_rx.addr(7 downto 0) is + --when x"00" => fwd_dst_ip <= busfwd_rx.data; + --when x"01" => fwd_dst_port <= busfwd_rx.data(15 downto 0); + --when x"02" => fwd_dst_mac(31 downto 0) <= busfwd_rx.data; + --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0); + --when x"04" => fwd_length <= busfwd_rx.data(15 downto 0); + --when x"05" => fwd_do_send <= busfwd_rx.data(0); + --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; + --end case; + --elsif busfwd_rx.read = '1' then + --busfwd_tx.ack <= '1'; + --case busfwd_rx.addr(7 downto 0) is + --when x"00" => busfwd_tx.data <= fwd_dst_ip; + --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port; + --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0); + --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32); + --when x"04" => busfwd_tx.data <= x"0000" & fwd_length; + --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send; + --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; + --end case; + --end if; + --if reset_i = '1' then + --fwd_do_send <= '0'; + --end if; +--end process; + + +--------------------------------------------------------------------------- +-- Output stage +--------------------------------------------------------------------------- + THE_OUT : entity work.testout + port map( + clkout => open, + refclk => clk_160, + reset => reset_i, + data => out_data, + data_cflag => open, + data_direction => (others => '0'), + data_loadn => (others => '1'), + data_move => (others => '0'), + dout => out_i + ); + + PROC_OUT : process + variable cnt : integer range 0 to 7; + begin + wait until rising_edge(clk_160); + cnt := cnt + 1; + case cnt is + when 0 => out_data <= x"ffff"; + when 1 => out_data <= x"ffff"; + when 2 => out_data <= x"ffff"; + when 3 => out_data <= x"0000"; + when 4 => out_data <= x"5555"; + when 5 => out_data <= x"5555"; + when 6 => out_data <= x"5555"; + when 7 => out_data <= x"5555"; + end case; + end process; + + -- H3(3 downto 0) <= out_i(3 downto 0); + -- H4(3 downto 0) <= out_i(7 downto 4); + --------------------------------------------------------------------------- -- GBT Core