From: hadeshyp Date: Tue, 21 Oct 2008 14:51:10 +0000 (+0000) Subject: added ecp2m media interface & changed all to 80bit packet size. Not fully tested... X-Git-Tag: oldGBE~525 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0ce78170678a3a8a49cee5b4b6dc39bf1b3f93cc;p=trbnet.git added ecp2m media interface & changed all to 80bit packet size. Not fully tested in hardware yet. Jan --- diff --git a/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd b/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd new file mode 100644 index 0000000..2a54312 --- /dev/null +++ b/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd @@ -0,0 +1,1774 @@ +-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58) +-- Module Version: 4.4 +--/local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 1024 -width 18 -depth 1024 -no_enable -pe -1 -pf -1 -e + +-- Sat Oct 18 18:06:48 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity lattice_ecp2m_fifo_16bit_dualport is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic); +end lattice_ecp2m_fifo_16bit_dualport; + +architecture Structure of lattice_ecp2m_fifo_16bit_dualport is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal co5: std_logic; + signal wcount_10: std_logic; + signal co4: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal co5_1: std_logic; + signal rcount_10: std_logic; + signal co4_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_27 : label is "0x6996"; + attribute initval of LUT4_26 : label is "0x6996"; + attribute initval of LUT4_25 : label is "0x6996"; + attribute initval of LUT4_24 : label is "0x6996"; + attribute initval of LUT4_23 : label is "0x6996"; + attribute initval of LUT4_22 : label is "0x6996"; + attribute initval of LUT4_21 : label is "0x6996"; + attribute initval of LUT4_20 : label is "0x6996"; + attribute initval of LUT4_19 : label is "0x6996"; + attribute initval of LUT4_18 : label is "0x6996"; + attribute initval of LUT4_17 : label is "0x6996"; + attribute initval of LUT4_16 : label is "0x6996"; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp2m_fifo_16bit_dualport.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_0 : label is "ENABLED"; + attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "18"; + attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "18"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t22: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t21: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t20: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t19: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t18: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t17: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t16: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t15: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t14: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t13: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t12: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t11: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t10: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t9: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t8: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t7: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t6: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t5: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t4: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t3: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t2: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t1: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t0: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + LUT4_27: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>w_gcount_r210, + DO0=>w_g2b_xor_cluster_0); + + LUT4_26: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_gcount_r26, + DO0=>w_g2b_xor_cluster_1); + + LUT4_25: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_24: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_23: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_22: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); + + LUT4_21: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r4); + + LUT4_20: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_19: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_18: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r21, AD0=>w_gcount_r22, DO0=>wcount_r1); + + LUT4_17: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2); + + LUT4_16: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>r_gcount_w210, + DO0=>r_g2b_xor_cluster_0); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, + DO0=>r_g2b_xor_cluster_1); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r210, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r210, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w210, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w210, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, + ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, + ADB11=>rptr_7, ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), + DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), + DOB11=>Q(11), DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), + DOB15=>Q(15), DOB16=>Q(16), DOB17=>Q(17)); + + FF_111: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_110: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_109: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_106: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_95: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_93: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_92: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_91: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_78: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_58: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_53: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_52: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_51: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_50: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_49: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_48: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_47: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_46: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_45: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_44: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_43: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_42: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_41: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_40: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_39: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_38: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_37: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_36: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_35: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_34: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_33: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_32: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5, + NC0=>iwcount_10, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1, + NC0=>ircount_10, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>w_g2b_xor_cluster_0, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co4_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>r_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co4_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of lattice_ecp2m_fifo_16bit_dualport is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd b/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd new file mode 100644 index 0000000..2796ead --- /dev/null +++ b/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd @@ -0,0 +1,59 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.trb_net_std.all; + +entity trb_net_fifo_16bit_bram_dualport is + generic( + USE_STATUS_FLAGS : integer := c_YES + ); + port ( + read_clock_in: IN std_logic; + write_clock_in: IN std_logic; + read_enable_in: IN std_logic; + write_enable_in: IN std_logic; + fifo_gsr_in: IN std_logic; + write_data_in: IN std_logic_vector(17 downto 0); + read_data_out: OUT std_logic_vector(17 downto 0); + full_out: OUT std_logic; + empty_out: OUT std_logic; + fifostatus_out: OUT std_logic_vector(3 downto 0); + valid_read_out: OUT std_logic; + almost_empty_out:OUT std_logic; + almost_full_out :OUT std_logic + ); +end entity trb_net_fifo_16bit_bram_dualport; + +architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport is + + component lattice_ecp2m_fifo_16bit_dualport + port (Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; Full: out std_logic); + end component; + +BEGIN + FIFO_DP_BRAM : lattice_ecp2m_fifo_16bit_dualport + port map ( + Data => write_data_in, + WrClock => write_clock_in, + RdClock => read_clock_in, + WrEn => write_enable_in, + RdEn => read_enable_in, + Reset => fifo_gsr_in, + RPReset => '0', + Q => read_data_out, + Empty => empty_out, + Full => full_out + ); + +almost_empty_out <= empty_out; +almost_full_out <= full_out; +fifostatus_out <= (others => '0'); +valid_read_out <= '0'; +end architecture trb_net_fifo_16bit_bram_dualport_arch; + diff --git a/trb_net16_api_active.vhd b/oldfiles/trb_net16_api_active.vhd similarity index 100% rename from trb_net16_api_active.vhd rename to oldfiles/trb_net16_api_active.vhd diff --git a/trb_net16_api_passive.vhd b/oldfiles/trb_net16_api_passive.vhd similarity index 100% rename from trb_net16_api_passive.vhd rename to oldfiles/trb_net16_api_passive.vhd diff --git a/trb_net16_endpoint_2_trg_2_api.vhd b/oldfiles/trb_net16_endpoint_2_trg_2_api.vhd similarity index 100% rename from trb_net16_endpoint_2_trg_2_api.vhd rename to oldfiles/trb_net16_endpoint_2_trg_2_api.vhd diff --git a/trb_net_med_8bit_fast.vhd b/oldfiles/trb_net_med_8bit_fast.vhd similarity index 100% rename from trb_net_med_8bit_fast.vhd rename to oldfiles/trb_net_med_8bit_fast.vhd diff --git a/optical_link/flexi_PCS_channel_synch.vhd b/optical_link/flexi_PCS_channel_synch.vhd index 79283be..08ddba6 100644 --- a/optical_link/flexi_PCS_channel_synch.vhd +++ b/optical_link/flexi_PCS_channel_synch.vhd @@ -196,7 +196,7 @@ begin fifo_opt_empty_synch <= fifo_opt_empty; fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; fifo_opt_not_empty <= not fifo_opt_empty; - elsif fifo_opt_empty_synch = '0' and fifo_opt_empty_synch_synch ='0'then + elsif fifo_opt_empty_synch = '0' and fifo_opt_empty_synch_synch ='0' then tx_k_i <= '0'; txd_synch_i <= txd_fifo_out(15 downto 0); fifo_opt_empty_synch <= fifo_opt_empty; diff --git a/testbench/trb_net16_dummy_apl.vhd b/testbench/trb_net16_dummy_apl.vhd index 056a9b5..5afc1a2 100644 --- a/testbench/trb_net16_dummy_apl.vhd +++ b/testbench/trb_net16_dummy_apl.vhd @@ -1,6 +1,6 @@ -- this is a dummy apl, just sending data into an active api ---THIS IS NOT WORKING !!!! +--THIS IS NOT WORKING correctly!!!! LIBRARY IEEE; @@ -27,25 +27,23 @@ entity trb_net16_dummy_apl is RESET : in std_logic; CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and should be transmitted - APL_READ_IN : in std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_OUT: out std_logic; -- - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_OUT: out std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) + APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + APL_SHORT_TRANSFER_OUT: out std_logic; + APL_DTYPE_OUT: out std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); + APL_SEND_OUT: out std_logic; + APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0); -- Receiver port - APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_IN:in std_logic_vector (1 downto 0); - APL_TYP_IN: in std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_IN: in std_logic; -- Data word is valid and might be read out - APL_READ_OUT: out std_logic; -- Read data word + APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN:in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_IN: in std_logic_vector (2 downto 0); + APL_DATAREADY_IN: in std_logic; + APL_READ_OUT: out std_logic; -- APL Control port - APL_RUN_IN: in std_logic; -- Data transfer is running --- APL_MY_ADDRESS_OUT: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_RUN_IN: in std_logic; APL_SEQNR_IN: in std_logic_vector (7 downto 0) ); end entity; @@ -54,12 +52,11 @@ architecture trb_net16_dummy_apl_arch of trb_net16_dummy_apl is type SENDER_STATE is (IDLE, WRITING, WAITING); signal current_state, next_state : SENDER_STATE; - signal next_counter, reg_counter : std_logic_vector(15 downto 0); - signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(15 downto 0); - signal buf_APL_PACKET_NUM_OUT, next_APL_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + signal next_counter, reg_counter : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic; signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic; - signal next_packet_counter, packet_counter : std_logic_vector(1 downto 0); + signal next_packet_counter, packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal address, reghigh, reglow : std_logic_vector(15 downto 0); signal state_bits : std_logic_vector(2 downto 0); begin @@ -67,10 +64,10 @@ begin -- address <= x"0008"; -- reghigh <= x"DEAD"; -- reglow <= x"AFFE"; - address <= x"1001"; --x"0001"; + address <= x"0001"; --x"0001"; reghigh <= x"0022"; reglow <= xor_all(APL_DATA_IN) & "000000000000011"; - APL_DTYPE_OUT <= x"A"; + APL_DTYPE_OUT <= x"8"; APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS; process(current_state) @@ -102,7 +99,6 @@ begin next_APL_SEND_OUT <= buf_APL_SEND_OUT; next_state <= IDLE; next_counter <= reg_counter; - next_APL_PACKET_NUM_OUT <= packet_counter; next_APL_WRITE_OUT <= '0'; next_APL_DATA_OUT <= (others => '0'); next_packet_counter <= packet_counter; @@ -118,7 +114,7 @@ begin next_state <= WRITING; next_APL_DATA_OUT <= address; next_APL_WRITE_OUT <= '1'; - next_packet_counter <= "01"; + next_packet_counter <= c_F0; next_APL_SEND_OUT <= '1'; end if; ------------------------------------------------------------------------- @@ -127,15 +123,19 @@ begin elsif current_state = WRITING then next_APL_SEND_OUT <= '1'; next_state <= WRITING; - if packet_counter = "01" then + if packet_counter = c_F0 then next_APL_WRITE_OUT <= '1'; next_APL_DATA_OUT <= reghigh; - next_packet_counter <= "10"; - elsif packet_counter = "10" then + next_packet_counter <= c_F1; + elsif packet_counter = c_F1 then next_APL_WRITE_OUT <= '1'; next_APL_DATA_OUT <= reglow; - next_packet_counter <= "11"; - elsif packet_counter = "11" then + next_packet_counter <= c_F2; + elsif packet_counter = c_F2 then + next_APL_WRITE_OUT <= '1'; + next_APL_DATA_OUT <= (2 => '1', others => '0'); + next_packet_counter <= c_F3; + elsif packet_counter = c_F3 then next_state <= IDLE; next_counter <= reg_counter +1; end if; @@ -165,9 +165,7 @@ APL_DATAREADY_OUT <= buf_APL_WRITE_OUT; if RESET = '1' then current_state <= IDLE; reg_counter <= (others => '0'); - packet_counter <= "00"; buf_APL_DATA_OUT <= (others => '0'); - buf_APL_PACKET_NUM_OUT <= "00"; buf_APL_WRITE_OUT <= '0'; buf_APL_SEND_OUT <= '0'; elsif CLK_EN = '1' then @@ -175,7 +173,6 @@ APL_DATAREADY_OUT <= buf_APL_WRITE_OUT; current_state <= next_state; packet_counter <= next_packet_counter; buf_APL_DATA_OUT <= next_APL_DATA_OUT; - buf_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT; buf_APL_WRITE_OUT <= next_APL_WRITE_OUT; buf_APL_SEND_OUT <= next_APL_SEND_OUT; end if; diff --git a/testbench/trb_net16_dummy_passive_apl.vhd b/testbench/trb_net16_dummy_passive_apl.vhd index 0e6ef45..0b0cc3c 100644 --- a/testbench/trb_net16_dummy_passive_apl.vhd +++ b/testbench/trb_net16_dummy_passive_apl.vhd @@ -1,6 +1,6 @@ -- this is a dummy apl, just sending data into an active api --- THIS IS NOT WORKING !!!! +-- THIS IS NOT WORKING correctly !!!! LIBRARY IEEE; @@ -26,24 +26,23 @@ entity trb_net16_dummy_passive_apl is RESET : in std_logic; CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and should be transmitted - APL_READ_IN : in std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_OUT: out std_logic; -- - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_OUT: out std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) + APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + APL_SHORT_TRANSFER_OUT: out std_logic; + APL_DTYPE_OUT: out std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); + APL_SEND_OUT: out std_logic; + APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0); -- Receiver port - APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_IN:in std_logic_vector (1 downto 0); - APL_TYP_IN: in std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_IN: in std_logic; -- Data word is valid and might be read out - APL_READ_OUT: out std_logic; -- Read data word + APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN:in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_IN: in std_logic_vector (2 downto 0); + APL_DATAREADY_IN: in std_logic; + APL_READ_OUT: out std_logic; -- APL Control port - APL_RUN_IN: in std_logic; -- Data transfer is running + APL_RUN_IN: in std_logic; APL_SEQNR_IN: in std_logic_vector (7 downto 0); STAT : out std_logic_vector(31 downto 0) ); @@ -54,11 +53,11 @@ architecture trb_net16_dummy_passive_apl_arch of trb_net16_dummy_passive_apl is type SENDER_STATE is (IDLE, WRITING, RUNNING, WAITING, MY_ERROR); signal current_state, next_state : SENDER_STATE; signal next_counter, reg_counter : std_logic_vector(15 downto 0); - signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(15 downto 0); - signal buf_APL_PACKET_NUM_OUT, next_APL_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal buf_APL_PACKET_NUM_OUT, next_APL_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic; signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic; - signal next_packet_counter, packet_counter : std_logic_vector(1 downto 0); + signal next_packet_counter, packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal state_bits : std_logic_vector(2 downto 0); signal current_TYPE_IN, saved_PACKET_TYPE_IN : std_logic_vector(2 downto 0); @@ -97,13 +96,13 @@ begin if rising_edge(CLK) then if RESET = '1' then saved_PACKET_TYPE_IN <= TYPE_ILLEGAL; - elsif APL_PACKET_NUM_IN = "00" then + elsif APL_PACKET_NUM_IN = c_H0 then saved_PACKET_TYPE_IN <= APL_TYP_IN; end if; end if; end process; --create comb. real packet type - current_TYPE_IN <= APL_TYP_IN when (APL_PACKET_NUM_IN = "00" and RESET = '0') + current_TYPE_IN <= APL_TYP_IN when (APL_PACKET_NUM_IN = c_H0 and RESET = '0') else saved_PACKET_TYPE_IN; SENDER_CTRL: process (current_state, APL_READ_IN, reg_counter, APL_RUN_IN, RESET, APL_TYP_IN, @@ -128,24 +127,28 @@ begin next_state <= WRITING; next_APL_DATA_OUT <= (1 => '1', others => '0'); next_APL_WRITE_OUT <= '1'; - next_packet_counter <= "01"; + next_packet_counter <= c_F0; end if; ------------------------------------------------------------------------- -- WRITING ------------------------------------------------------------------------- elsif current_state = WRITING then next_state <= WRITING; - if packet_counter = "01" then + if packet_counter = c_F0 then next_APL_WRITE_OUT <= '1'; next_APL_DATA_OUT <= (0 => '1', others => '0'); - next_packet_counter <= "10"; - elsif packet_counter = "10" then + next_packet_counter <= c_F1; + elsif packet_counter = c_F1 then next_APL_WRITE_OUT <= '1'; next_APL_DATA_OUT <= xor_all(APL_DATA_IN) & reg_counter(14 downto 0); - next_packet_counter <= "11"; - elsif packet_counter <= "11" then + next_packet_counter <= c_F2; + elsif packet_counter = c_F2 then + next_APL_WRITE_OUT <= '1'; + next_APL_DATA_OUT <= xor_all(APL_DATA_IN) & reg_counter(14 downto 0); + next_packet_counter <= c_F3; + elsif packet_counter <=c_F3 then next_state <= IDLE; - next_packet_counter <= "01"; + next_packet_counter <= c_F0; next_counter <= reg_counter +1; end if; ----------------------------------------------------------------------- @@ -165,7 +168,7 @@ begin -- WAITING ----------------------------------------------------------------------- elsif current_state = WAITING then - if (APL_TYP_IN = TYPE_TRM and APL_PACKET_NUM_IN = "11" and APL_DATAREADY_IN = '1') then + if (APL_TYP_IN = TYPE_TRM and APL_PACKET_NUM_IN = c_F3 and APL_DATAREADY_IN = '1') then next_state <= IDLE; next_counter <= (others => '0'); else @@ -188,9 +191,7 @@ APL_SEND_OUT <= buf_APL_SEND_OUT; if RESET = '1' then current_state <= WAITING; reg_counter <= (others => '0'); - packet_counter <= "01"; buf_APL_DATA_OUT <= (others => '0'); - buf_APL_PACKET_NUM_OUT <= "00"; buf_APL_WRITE_OUT <= '0'; buf_APL_SEND_OUT <= '0'; elsif CLK_EN = '1' then @@ -198,7 +199,6 @@ APL_SEND_OUT <= buf_APL_SEND_OUT; current_state <= next_state; packet_counter <= next_packet_counter; buf_APL_DATA_OUT <= next_APL_DATA_OUT; - buf_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT; buf_APL_WRITE_OUT <= next_APL_WRITE_OUT; buf_APL_SEND_OUT <= next_APL_SEND_OUT; end if; diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd index fcd6566..9f5301a 100644 --- a/trb_net16_addresses.vhd +++ b/trb_net16_addresses.vhd @@ -15,15 +15,15 @@ entity trb_net16_addresses is CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - API_DATA_IN : in std_logic_vector(15 downto 0); + API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); API_DATAREADY_IN : in std_logic; API_READ_OUT : out std_logic; RAM_DATA_IN : in std_logic_vector(15 downto 0); RAM_DATA_OUT : out std_logic_vector(15 downto 0); RAM_ADDR_IN : in std_logic_vector(2 downto 0); RAM_WR_IN : in std_logic; - API_DATA_OUT : out std_logic_vector(15 downto 0); - API_PACKET_NUM_OUT: out std_logic_vector(1 downto 0); + API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); API_DATAREADY_OUT : out std_logic; API_READ_IN : in std_logic; ADDRESS_REJECTED : out std_logic; @@ -118,7 +118,7 @@ begin begin next_state <= state; API_DATAREADY_OUT <= '0'; - API_PACKET_NUM_OUT <= "01"; + API_PACKET_NUM_OUT <= c_F0; API_DATA_OUT <= ram_read_dout; ram_read_addr2 <= "000"; next_read_uid_1 <= read_uid_1; @@ -137,7 +137,7 @@ begin when SEND1 => API_SEND_OUT <= '1'; API_DATAREADY_OUT <= '1'; - API_PACKET_NUM_OUT <= "01"; + API_PACKET_NUM_OUT <= c_F0; if read_uid_1 = '1' then ram_read_addr2 <= "001"; elsif read_uid_2 = '1' then @@ -157,7 +157,7 @@ begin when SEND2 => API_SEND_OUT <= '1'; API_DATAREADY_OUT <= '1'; - API_PACKET_NUM_OUT <= "10"; + API_PACKET_NUM_OUT <= c_F1; if read_uid_1 = '1' then ram_read_addr2 <= "010"; else @@ -174,7 +174,7 @@ begin when SEND3 => API_SEND_OUT <= '1'; API_DATAREADY_OUT <= '1'; - API_PACKET_NUM_OUT <= "11"; + API_PACKET_NUM_OUT <= c_F2; if read_uid_1 = '1' then ram_read_addr2 <= "011"; else diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 1fefd43..5a641fc 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -7,7 +7,6 @@ library work; use work.trb_net_std.all; entity trb_net16_api_base is - generic ( API_TYPE : integer range 0 to 1 := c_API_PASSIVE; FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; @@ -17,9 +16,8 @@ entity trb_net16_api_base is USE_VENDOR_CORES : integer range 0 to 1 := c_YES; SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; - APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" - --which bits must be set to accept a broadcast? ); port( @@ -29,27 +27,26 @@ entity trb_net16_api_base is CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_DATAREADY_IN : in std_logic; -- Data word is valid and should be transmitted - APL_READ_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) -- Receiver port - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); APL_SEQNR_OUT : out std_logic_vector (7 downto 0); -- Internal direction port @@ -58,25 +55,22 @@ entity trb_net16_api_base is -- lets define: the "master" path is the path that I send data on. -- master_data_out and slave_data_in are only used in active API for termination INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_IN : in std_logic; INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_OUT : out std_logic; - - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_IN : in std_logic; INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_OUT : out std_logic; @@ -95,36 +89,34 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic ); end component; component trb_net16_fifo is generic ( - DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1) 64Bit packets - USE_VENDOR_CORES : integer := c_YES + USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 ); port ( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic ); end component; @@ -141,11 +133,11 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); -- Port to synchronous output. SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); SYN_READ_IN : in STD_LOGIC; -- Status and control port @@ -155,32 +147,35 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is component trb_net16_term is generic ( - USE_APL_PORT : integer range 0 to 1 := 0; - SECURE_MODE : integer range 0 to 1 := 0 - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these must be available when hold_trm goes low + USE_APL_PORT : integer range 0 to 1 := c_YES; + --even when 0, ERROR_PACKET_IN is used for automatic replys + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE + --if secure_mode is not used, apl must provide error pattern and dtype until + --next trigger comes in. In secure mode these need to be available while relase_trg is high ); port( -- Misc CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) - -- Status and control port + + INT_DATAREADY_OUT : out std_logic; + INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN : in std_logic; + + INT_DATAREADY_IN : in std_logic; + INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out std_logic; + + -- "mini" APL, just to see terminations coming in + APL_DTYPE_OUT : out std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + APL_GOT_TRM : out std_logic; + APL_RELEASE_TRM : in std_logic; + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) ); end component; @@ -197,9 +192,9 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); SYN_READ_IN: in STD_LOGIC; STAT_BUFFER: out STD_LOGIC ); @@ -207,33 +202,41 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is -- signals for the APL to INT fifo: signal fifo_to_int_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_int_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal fifo_to_int_packet_num_in : std_logic_vector(1 downto 0); signal fifo_to_int_write : std_logic; signal fifo_to_int_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_int_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal fifo_to_int_read : std_logic; - signal fifo_to_int_full : std_logic; + signal fifo_to_int_packet_num_out : std_logic_vector(1 downto 0); + signal fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal fifo_to_int_read : std_logic; + signal fifo_to_int_full : std_logic; signal fifo_to_int_empty : std_logic; -- signals for the INT to APL: signal fifo_to_apl_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_apl_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal fifo_to_apl_packet_num_in : std_logic_vector(1 downto 0); signal fifo_to_apl_write : std_logic; signal fifo_to_apl_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_apl_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal fifo_to_apl_read : std_logic; - signal fifo_to_apl_full : std_logic; + signal fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0); + signal fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal fifo_to_apl_read : std_logic; + signal fifo_to_apl_full : std_logic; signal fifo_to_apl_empty : std_logic; - signal saved_fifo_to_apl_packet_type, current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0); + signal saved_fifo_to_apl_packet_type : std_logic_vector(2 downto 0); + signal current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0); + +signal saved_fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); +signal saved_fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); +signal last_fifo_to_apl_read : std_logic; +signal last_fifo_to_int_read : std_logic; - signal state_bits, state_bits_to_int, state_bits_to_apl : std_logic_vector(2 downto 0); + signal state_bits_to_int, state_bits_to_apl : std_logic_vector(2 downto 0); -- signal slave_running, next_slave_running, get_slave_running, release_slave_running : std_logic; signal next_INT_MASTER_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); signal next_INT_MASTER_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); signal next_INT_MASTER_DATAREADY_OUT: std_logic; signal sbuf_free, sbuf_next_READ: std_logic; - signal next_INT_SLAVE_READ_OUT, reg_INT_SLAVE_READ_OUT: std_logic; + signal reg_INT_SLAVE_READ_OUT: std_logic; signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); @@ -242,10 +245,10 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB); signal out_select: OUTPUT_SELECT; signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); - signal combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0); - signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0); - signal registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0); - signal current_combined_header, current_registered_trailer, current_combined_trailer, current_data : std_logic_vector(15 downto 0); + signal combined_header_F0, combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0); + signal combined_trailer_F0, combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0); + signal registered_trailer_F0,registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0); + signal current_combined_header, current_registered_trailer, current_data : std_logic_vector(15 downto 0); signal update_registered_trailer: std_logic; signal master_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); @@ -270,7 +273,7 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is signal master_start, master_end, slave_start, slave_end : std_logic; signal master_running, slave_running : std_logic; - signal buf_INT_MASTER_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + signal buf_INT_MASTER_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_INT_MASTER_DATAREADY_OUT : std_logic; signal next_fifo_was_not_empty, fifo_was_not_empty : std_logic; @@ -348,15 +351,16 @@ begin FULL_OUT => fifo_to_int_full, EMPTY_OUT => fifo_to_int_empty ); - end generate CHECK_BUFFER4; + end generate; STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0); STAT_FIFO_TO_INT(3) <= fifo_to_int_write; - STAT_FIFO_TO_INT(5 downto 4) <= buf_INT_MASTER_PACKET_NUM_OUT; - STAT_FIFO_TO_INT(6) <= buf_INT_MASTER_DATAREADY_OUT; - STAT_FIFO_TO_INT(7) <= INT_MASTER_READ_IN; - STAT_FIFO_TO_INT(10 downto 8) <= fifo_to_int_data_out(2 downto 0); - STAT_FIFO_TO_INT(11) <= fifo_to_int_read; + STAT_FIFO_TO_INT(6 downto 4) <= buf_INT_MASTER_PACKET_NUM_OUT; + STAT_FIFO_TO_INT(7) <= buf_INT_MASTER_DATAREADY_OUT; + STAT_FIFO_TO_INT(8) <= INT_MASTER_READ_IN; + STAT_FIFO_TO_INT(11 downto 9) <= fifo_to_int_data_out(2 downto 0); + STAT_FIFO_TO_INT(12) <= fifo_to_int_read; + STAT_FIFO_TO_INT(13) <= fifo_to_int_read_before; STAT_FIFO_TO_INT(14) <= fifo_to_int_full; STAT_FIFO_TO_INT(15) <= fifo_to_int_empty; STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT; @@ -365,11 +369,8 @@ begin STAT_FIFO_TO_INT(19) <= fifo_to_apl_read; STAT_FIFO_TO_INT(20) <= fifo_to_apl_empty; STAT_FIFO_TO_INT(21) <= fifo_to_apl_write; - STAT_FIFO_TO_INT(12) <= fifo_to_int_read_before; - STAT_FIFO_TO_INT(13) <= '0'; - STAT_FIFO_TO_INT(23 downto 22) <= next_INT_MASTER_PACKET_NUM_OUT; - STAT_FIFO_TO_INT(24) <= next_INT_MASTER_DATAREADY_OUT; - STAT_FIFO_TO_INT(25) <= '0'; + STAT_FIFO_TO_INT(24 downto 22) <= next_INT_MASTER_PACKET_NUM_OUT; + STAT_FIFO_TO_INT(25) <= next_INT_MASTER_DATAREADY_OUT; STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int; STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl; --------------------------------------- @@ -415,16 +416,16 @@ begin STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0); STAT_FIFO_TO_APL(3) <= fifo_to_apl_write; + STAT_FIFO_TO_APL(7 downto 4) <= (others => '0'); STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0); + STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT; STAT_FIFO_TO_APL(11) <= fifo_to_apl_read; + STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN; + STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT; STAT_FIFO_TO_APL(14) <= fifo_to_apl_full; STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty; - STAT_FIFO_TO_APL(7 downto 4) <= (others => '0'); --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0'); STAT_FIFO_TO_APL(31 downto 16) <= (others => '0'); - STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT; - STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN; - STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT; --------------------------------------- -- a sbuf (to_int direction) @@ -527,7 +528,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; end generate; next_APL_DATA_OUT <= fifo_to_apl_data_out; - next_APL_PACKET_NUM_OUT <= fifo_to_apl_packet_num_out; + next_APL_PACKET_NUM_OUT <= fifo_to_apl_long_packet_num_out; next_APL_TYP_OUT <= current_fifo_to_apl_packet_type; APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; APL_DATA_OUT <= reg_APL_DATA_OUT; @@ -542,15 +543,14 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or fifo_to_apl_packet_num_out = "11" then + if RESET = '1' or fifo_to_apl_long_packet_num_out = c_F3 then saved_fifo_to_apl_packet_type <= TYPE_ILLEGAL; - elsif fifo_to_apl_packet_num_out = "00" and CLK_EN = '1' then + elsif fifo_to_apl_long_packet_num_out = c_H0 and CLK_EN = '1' then saved_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0); end if; end if; end process; - --create comb. real packet type - current_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0) when (fifo_to_apl_packet_num_out = "00") + current_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0) when (fifo_to_apl_long_packet_num_out = c_H0) else saved_fifo_to_apl_packet_type; --------------------------------------- @@ -558,12 +558,11 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; --------------------------------------- - process(current_combined_header, current_registered_trailer, current_combined_trailer, current_data, out_select) + process(current_combined_header, current_registered_trailer, current_data, out_select) begin case out_select is when HDR => next_INT_MASTER_DATA_OUT <= current_combined_header; when TRM => next_INT_MASTER_DATA_OUT <= current_registered_trailer; --- when TRM_COMB => next_INT_MASTER_DATA_OUT <= current_combined_trailer; when others => next_INT_MASTER_DATA_OUT <= current_data; end case; end process; @@ -572,28 +571,29 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; process(master_counter, fifo_to_int_data_out, combined_header_F1, registered_trailer_F1, combined_trailer_F1, combined_header_F2, registered_trailer_F2, combined_trailer_F2, - combined_header_F3, registered_trailer_F3, combined_trailer_F3) + combined_header_F3, registered_trailer_F3, combined_trailer_F3, combined_header_F0, + registered_trailer_F0) begin case master_counter is - when "01" => + when c_F0 => + current_combined_header <= combined_header_F0; + current_registered_trailer <= registered_trailer_F0; + current_data <= fifo_to_int_data_out; + when c_F1 => current_combined_header <= combined_header_F1; current_registered_trailer <= registered_trailer_F1; --- current_combined_trailer <= combined_trailer_F1; current_data <= fifo_to_int_data_out; - when "10" => + when c_F2 => current_combined_header <= combined_header_F2; current_registered_trailer <= registered_trailer_F2; --- current_combined_trailer <= combined_trailer_F2; current_data <= fifo_to_int_data_out; - when "11" => + when c_F3 => current_combined_header <= combined_header_F3; current_registered_trailer <= registered_trailer_F3; --- current_combined_trailer <= combined_trailer_F3; current_data <= fifo_to_int_data_out; when others => current_combined_header <= "0000000000000" & TYPE_HDR; current_registered_trailer <= "0000000000000" & TYPE_TRM; --- current_combined_trailer <= "0000000000000" & TYPE_TRM; current_data <= "0000000000000" & TYPE_DAT; end case; end process; @@ -604,9 +604,13 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; begin if rising_edge(CLK) then if RESET = '1' then - master_counter <= (others => '0'); + master_counter <= c_H0; elsif next_INT_MASTER_DATAREADY_OUT = '1' and CLK_EN = '1' then - master_counter <= master_counter + 1; + if master_counter = c_max_word_number then + master_counter <= (others => '0'); + else + master_counter <= master_counter + 1; + end if; end if; end if; end process; @@ -620,7 +624,9 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; if rising_edge(CLK) then if RESET = '1' then fifo_to_apl_read_before <= '0'; + last_fifo_to_apl_read <= '0'; elsif CLK_EN = '1' then + last_fifo_to_apl_read <= fifo_to_apl_read; if fifo_to_apl_read = '1' then fifo_to_apl_read_before <= '1'; elsif sbuf_to_apl_free = '1' or throw_away = '1' then @@ -635,23 +641,59 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; if rising_edge(CLK) then if RESET = '1' then fifo_to_int_read_before <= '0'; + last_fifo_to_int_read <= '0'; elsif CLK_EN = '1' then + last_fifo_to_int_read <= fifo_to_int_read; if fifo_to_int_read = '1' then fifo_to_int_read_before <= '1'; - elsif next_INT_MASTER_DATAREADY_OUT = '1' and master_counter /= "00" then --implies sbuf_free + elsif next_INT_MASTER_DATAREADY_OUT = '1' and master_counter /= c_H0 then --implies sbuf_free fifo_to_int_read_before <= '0'; end if; end if; end if; end process; +--------------------------------------- +--regenerate long packet numbers +--------------------------------------- + fifo_to_int_long_packet_num_out(2) <= fifo_to_int_packet_num_out(1); + fifo_to_int_long_packet_num_out(0) <= fifo_to_int_packet_num_out(0); + fifo_to_int_long_packet_num_out(1) <= not saved_fifo_to_int_long_packet_num_out(1) when last_fifo_to_int_read = '1' and not saved_fifo_to_int_long_packet_num_out(2) = '1' and saved_fifo_to_int_long_packet_num_out(0) = '1' else saved_fifo_to_int_long_packet_num_out(1); + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_fifo_to_int_long_packet_num_out <= (others => '0'); + elsif last_fifo_to_int_read = '1' then + saved_fifo_to_int_long_packet_num_out <= fifo_to_int_long_packet_num_out; + end if; + end if; + end process; + + + fifo_to_apl_long_packet_num_out(2) <= fifo_to_apl_packet_num_out(1); + fifo_to_apl_long_packet_num_out(0) <= fifo_to_apl_packet_num_out(0); + fifo_to_apl_long_packet_num_out(1) <= not saved_fifo_to_apl_long_packet_num_out(1) when last_fifo_to_apl_read = '1' and not saved_fifo_to_apl_long_packet_num_out(2) = '1' and saved_fifo_to_apl_long_packet_num_out(0) = '1' else saved_fifo_to_apl_long_packet_num_out(1); + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_fifo_to_apl_long_packet_num_out <= (others => '0'); + elsif last_fifo_to_apl_read = '1' then + saved_fifo_to_apl_long_packet_num_out <= fifo_to_apl_long_packet_num_out; + end if; + end if; + end process; + --------------------------------------- --state machine for direction to APL --------------------------------------- to_apl : process(fifo_to_apl_full, reg_INT_SLAVE_READ_OUT, INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, - fifo_to_apl_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT, + fifo_to_apl_long_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT, sbuf_to_apl_free, INT_SLAVE_DATA_IN, INT_SLAVE_PACKET_NUM_IN, APL_MY_ADDRESS_IN, reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away,state_to_int, saved_fifo_to_apl_packet_type,master_start) @@ -669,11 +711,11 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; case state_to_apl is when sa_IDLE => if INT_SLAVE_DATAREADY_IN = '1' then - if (INT_SLAVE_DATA_IN(2 downto 0) = TYPE_TRM and INT_SLAVE_PACKET_NUM_IN = "00") then + if (INT_SLAVE_DATA_IN(2 downto 0) = TYPE_TRM and INT_SLAVE_PACKET_NUM_IN = c_H0) then next_state_to_apl <= sa_MY_ADDR; slave_start <= '1'; end if; - if INT_SLAVE_PACKET_NUM_IN = "10" then + if INT_SLAVE_PACKET_NUM_IN = c_F1 then if (INT_SLAVE_DATA_IN = APL_MY_ADDRESS_IN) or (and_all(not(not INT_SLAVE_DATA_IN and (x"FF" & BROADCAST_BITMASK))) = '1') then next_state_to_apl <= sa_MY_ADDR; slave_start <= '1'; @@ -686,19 +728,19 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; when sa_WRONG_ADDR => fifo_to_apl_read <= not fifo_to_apl_empty; throw_away <= '1'; - if saved_fifo_to_apl_packet_type = TYPE_TRM and fifo_to_apl_PACKET_NUM_OUT = "11" then + if saved_fifo_to_apl_packet_type = TYPE_TRM and fifo_to_apl_long_PACKET_NUM_OUT = c_F3 then next_state_to_apl <= sa_INACTIVE; slave_end <= '1'; end if; when sa_MY_ADDR => - if APL_WRITE_4_PACKETS = 0 then - next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and (or_all(fifo_to_apl_packet_num_out)) and sbuf_to_apl_free; - throw_away <= not or_all(fifo_to_apl_packet_num_out); + if APL_WRITE_ALL_WORDS = 0 then + next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and sbuf_to_apl_free and not fifo_to_apl_long_packet_num_out(2); + throw_away <= fifo_to_apl_long_packet_num_out(2); else next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and sbuf_to_apl_free; end if; fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away); - if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and sbuf_to_apl_free = '1' then + if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = c_F3 and sbuf_to_apl_free = '1' then next_state_to_apl <= sa_INACTIVE; slave_end <= '1'; end if; @@ -763,32 +805,32 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; when SEND_HEADER => out_select <= HDR; next_INT_MASTER_DATAREADY_OUT <= sbuf_free; - if master_counter = "11" and sbuf_free = '1' then + if master_counter = c_F3 and sbuf_free = '1' then next_state_to_int <= RUNNING; end if; when RUNNING => - fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(master_counter); - next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or not or_all(master_counter)); + fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2); + next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or master_counter(2)); if APL_SEND_IN = '0' and fifo_was_not_empty = '1' then -- terminate the transfer update_registered_trailer <= '1'; - if fifo_to_int_empty = '1' and master_counter = "11" and sbuf_free = '1' then + if fifo_to_int_empty = '1' and master_counter = c_F3 and sbuf_free = '1' then next_state_to_int <= SEND_TRAILER; -- immediate stop else next_state_to_int <= SHUTDOWN; -- send rest of data / padding end if; end if; when SHUTDOWN => - fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(master_counter); + fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2); next_INT_MASTER_DATAREADY_OUT <= sbuf_free and - ((fifo_to_int_read_before or not or_all(master_counter)) or --write data from fifo - (fifo_to_int_empty and or_all(master_counter))); --fill with padding words - if master_counter = "11" and fifo_to_int_empty = '1' and sbuf_free = '1' then + ((fifo_to_int_read_before or master_counter(2)) or --write data from fifo + (fifo_to_int_empty and not master_counter(2))); --fill with padding words + if master_counter = c_F3 and fifo_to_int_empty = '1' and sbuf_free = '1' then next_state_to_int <= SEND_TRAILER; end if; when SEND_TRAILER => out_select <= TRM; next_INT_MASTER_DATAREADY_OUT <= sbuf_free; - if master_counter = "11" and sbuf_free = '1' then + if master_counter = c_F3 and sbuf_free = '1' then next_state_to_int <= INACTIVE; next_sequence_counter <= sequence_counter +1; master_end <= '1'; @@ -808,14 +850,12 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; state_to_apl <= sa_INACTIVE; state_to_int <= IDLE; end if; - --reg_INT_SLAVE_READ_OUT <= '0'; send_trm_wrong_addr <= '0'; sequence_counter <= (others => '0'); fifo_was_not_empty <= '0'; elsif CLK_EN = '1' then state_to_apl <= next_state_to_apl; state_to_int <= next_state_to_int; - --reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT; send_trm_wrong_addr <= next_send_trm_wrong_addr; sequence_counter <= next_sequence_counter; fifo_was_not_empty <= next_fifo_was_not_empty; @@ -842,7 +882,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; --get target address from active APL gentarget1: if API_TYPE = 1 generate - combined_header_F2 <= APL_TARGET_ADDRESS_IN; + combined_header_F1 <= APL_TARGET_ADDRESS_IN; end generate; --save target address for passive api gentarget0: if API_TYPE = 0 generate @@ -850,19 +890,21 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; begin if rising_edge(CLK) then if RESET = '1' then - combined_header_F2 <= (others => '1'); - elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_packet_num_out = "01" and CLK_EN = '1' then - combined_header_F2 <= fifo_to_apl_data_out; + combined_header_F1 <= (others => '1'); + elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_long_packet_num_out = c_F0 and CLK_EN = '1' then + combined_header_F1 <= fifo_to_apl_data_out; end if; end if; end process; end generate; -- combine the next header - combined_header_F1 <= APL_MY_ADDRESS_IN; + combined_header_F0 <= APL_MY_ADDRESS_IN; + combined_header_F2 <= (others => '0'); combined_header_F3(15 downto 14) <= (others => '0'); -- LAY combined_header_F3(13 downto 12) <= (others => '0'); -- VERS combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR combined_header_F3(3 downto 0) <= APL_DTYPE_IN; + combined_trailer_F0 <= (others => '0'); combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16); combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 1) & endpoint_reached when API_TYPE = c_API_PASSIVE else APL_ERROR_PATTERN_IN(15 downto 0); @@ -873,13 +915,13 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; -- connect Transmitter port fifo_to_int_data_in <= APL_DATA_IN; - fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN; + fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN(2) & APL_PACKET_NUM_IN(0); fifo_to_int_write <= (APL_DATAREADY_IN and not fifo_to_int_full); APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing -- connect receiver fifo_to_apl_data_in <= INT_SLAVE_DATA_IN; - fifo_to_apl_packet_num_in <= INT_SLAVE_PACKET_NUM_IN; + fifo_to_apl_packet_num_in <= INT_SLAVE_PACKET_NUM_IN(2) & INT_SLAVE_PACKET_NUM_IN(0); INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT; RUN_OUT_gen : process(CLK) @@ -929,11 +971,8 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; REG3 : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then - registered_trailer_F1 <= (others => '0'); - registered_trailer_F2 <= (others => '0'); - registered_trailer_F3 <= (others => '0'); - elsif update_registered_trailer = '1' then + if update_registered_trailer = '1' then + registered_trailer_F0 <= combined_trailer_F0; registered_trailer_F1 <= combined_trailer_F1; registered_trailer_F2 <= combined_trailer_F2; registered_trailer_F3 <= combined_trailer_F3; diff --git a/trb_net16_api_streaming.vhd b/trb_net16_api_streaming.vhd index d20ddf2..55f3ed0 100644 --- a/trb_net16_api_streaming.vhd +++ b/trb_net16_api_streaming.vhd @@ -9,20 +9,20 @@ use work.trb_net_std.all; entity trb_net16_api_streaming is generic( - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6; - FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6; - FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; - SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; - APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + SECURE_MODE_TO_APL : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT : integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS: integer range 0 to 1 := c_NO ); port( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - + INT_INIT_DATAREADY_IN : in std_logic; INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); @@ -42,7 +42,7 @@ entity trb_net16_api_streaming is APL_INIT_DATA_IN : out std_logic_vector (c_DATA_WIDTH-1 downto 0); APL_INIT_PACKET_NUM_IN : out std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_INIT_DATAREADY_IN : out std_logic; - + --apl reply sending APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); @@ -59,7 +59,7 @@ entity trb_net16_api_streaming is APL_TYP_OUT : out std_logic_vector (2 downto 0); APL_DATAREADY_OUT : out std_logic; APL_READ_IN : in std_logic; - + -- APL Control port APL_RUN_OUT : out std_logic; APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); @@ -79,14 +79,13 @@ architecture trb_net16_api_streaming_arch of trb_net16_api_streaming is RESET : in std_logic; CLK_EN : in std_logic; DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(1 downto 0); -- Input data WRITE_ENABLE_IN : in std_logic; DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) + EMPTY_OUT : out std_logic ); end component; @@ -100,14 +99,13 @@ architecture trb_net16_api_streaming_arch of trb_net16_api_streaming is RESET : in std_logic; CLK_EN : in std_logic; DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(1 downto 0); -- Input data WRITE_ENABLE_IN : in std_logic; DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) + EMPTY_OUT : out std_logic ); end component; @@ -190,25 +188,32 @@ architecture trb_net16_api_streaming_arch of trb_net16_api_streaming is -- signals for the APL to INT fifo: signal fifo_to_int_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_int_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal fifo_to_int_packet_num_in : std_logic_vector(1 downto 0); signal fifo_to_int_write : std_logic; signal fifo_to_int_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_int_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal fifo_to_int_packet_num_out : std_logic_vector(1 downto 0); + signal fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal fifo_to_int_read : std_logic; signal fifo_to_int_full : std_logic; signal fifo_to_int_empty : std_logic; - + -- signals for the INT to APL: signal fifo_to_apl_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_apl_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal fifo_to_apl_packet_num_in : std_logic_vector(1 downto 0); signal fifo_to_apl_write : std_logic; signal fifo_to_apl_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_apl_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0); + signal fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal fifo_to_apl_read : std_logic; signal fifo_to_apl_full : std_logic; signal fifo_to_apl_empty : std_logic; signal saved_fifo_to_apl_packet_type, current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0); + signal saved_fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal saved_fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal last_fifo_to_apl_read : std_logic; + signal last_fifo_to_int_read : std_logic; + signal state_bits, state_bits_to_int, state_bits_to_apl : std_logic_vector(2 downto 0); -- signal slave_running, next_slave_running, get_slave_running, release_slave_running : std_logic; @@ -221,13 +226,13 @@ architecture trb_net16_api_streaming_arch of trb_net16_api_streaming is signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); signal next_APL_TYP_OUT, reg_APL_TYP_OUT, buf_APL_TYP_OUT: std_logic_vector(2 downto 0); - + type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB); signal out_select: OUTPUT_SELECT; signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); - signal combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0); - signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0); - signal registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0); + signal combined_header_F1, combined_header_F2, combined_header_F3, combined_header_F0 : std_logic_vector(15 downto 0); + signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3, combined_trailer_F0 : std_logic_vector(15 downto 0); + signal registered_trailer_F1, registered_trailer_F2, registered_trailer_F3, registered_trailer_F0 : std_logic_vector(15 downto 0); signal current_combined_header, current_registered_trailer, current_data : std_logic_vector(15 downto 0); signal update_registered_trailer: std_logic; @@ -252,7 +257,7 @@ architecture trb_net16_api_streaming_arch of trb_net16_api_streaming is signal master_start, master_end, slave_start, slave_end : std_logic; signal master_running, slave_running : std_logic; - signal buf_INT_REPLY_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + signal buf_INT_REPLY_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_INT_REPLY_DATAREADY_OUT : std_logic; signal next_fifo_was_not_empty, fifo_was_not_empty : std_logic; @@ -288,11 +293,12 @@ begin STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0); STAT_FIFO_TO_INT(3) <= fifo_to_int_write; - STAT_FIFO_TO_INT(5 downto 4) <= buf_INT_REPLY_PACKET_NUM_OUT; - STAT_FIFO_TO_INT(6) <= buf_INT_REPLY_DATAREADY_OUT; - STAT_FIFO_TO_INT(7) <= INT_REPLY_READ_IN; - STAT_FIFO_TO_INT(10 downto 8) <= fifo_to_int_data_out(2 downto 0); - STAT_FIFO_TO_INT(11) <= fifo_to_int_read; + STAT_FIFO_TO_INT(6 downto 4) <= buf_INT_REPLY_PACKET_NUM_OUT; + STAT_FIFO_TO_INT(7) <= buf_INT_REPLY_DATAREADY_OUT; + STAT_FIFO_TO_INT(8) <= INT_REPLY_READ_IN; + STAT_FIFO_TO_INT(11 downto 9) <= fifo_to_int_data_out(2 downto 0); + STAT_FIFO_TO_INT(12) <= fifo_to_int_read; + STAT_FIFO_TO_INT(13) <= fifo_to_int_read_before; STAT_FIFO_TO_INT(14) <= fifo_to_int_full; STAT_FIFO_TO_INT(15) <= fifo_to_int_empty; STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT; @@ -301,11 +307,8 @@ begin STAT_FIFO_TO_INT(19) <= fifo_to_apl_read; STAT_FIFO_TO_INT(20) <= fifo_to_apl_empty; STAT_FIFO_TO_INT(21) <= fifo_to_apl_write; - STAT_FIFO_TO_INT(12) <= fifo_to_int_read_before; - STAT_FIFO_TO_INT(13) <= '0'; - STAT_FIFO_TO_INT(23 downto 22) <= next_INT_REPLY_PACKET_NUM_OUT; - STAT_FIFO_TO_INT(24) <= next_INT_REPLY_DATAREADY_OUT; - STAT_FIFO_TO_INT(25) <= '0'; + STAT_FIFO_TO_INT(24 downto 22) <= next_INT_REPLY_PACKET_NUM_OUT; + STAT_FIFO_TO_INT(25) <= next_INT_REPLY_DATAREADY_OUT; STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int; STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl; --------------------------------------- @@ -364,7 +367,7 @@ begin SYN_PACKET_NUM_OUT => buf_INT_REPLY_PACKET_NUM_OUT, SYN_READ_IN => INT_REPLY_READ_IN ); - + process(CLK) begin if rising_edge(CLK) then @@ -444,7 +447,7 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; end generate; next_APL_DATA_OUT <= fifo_to_apl_data_out; - next_APL_PACKET_NUM_OUT <= fifo_to_apl_packet_num_out; + next_APL_PACKET_NUM_OUT <= fifo_to_apl_long_packet_num_out; next_APL_TYP_OUT <= current_fifo_to_apl_packet_type; APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; APL_DATA_OUT <= reg_APL_DATA_OUT; @@ -452,6 +455,42 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; APL_TYP_OUT <= reg_APL_TYP_OUT; APL_SEQNR_OUT <= sequence_counter; + + +--------------------------------------- +--regenerate long packet numbers +--------------------------------------- + fifo_to_int_long_packet_num_out(2) <= fifo_to_int_packet_num_out(1); + fifo_to_int_long_packet_num_out(0) <= fifo_to_int_packet_num_out(0); + fifo_to_int_long_packet_num_out(1) <= not saved_fifo_to_int_long_packet_num_out(1) when last_fifo_to_int_read = '1' and not saved_fifo_to_int_long_packet_num_out(2) = '1' and saved_fifo_to_int_long_packet_num_out(0) = '1' else saved_fifo_to_int_long_packet_num_out(1); + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_fifo_to_int_long_packet_num_out <= (others => '0'); + elsif last_fifo_to_int_read = '1' then + saved_fifo_to_int_long_packet_num_out <= fifo_to_int_long_packet_num_out; + end if; + end if; + end process; + + + fifo_to_apl_long_packet_num_out(2) <= fifo_to_apl_packet_num_out(1); + fifo_to_apl_long_packet_num_out(0) <= fifo_to_apl_packet_num_out(0); + fifo_to_apl_long_packet_num_out(1) <= not saved_fifo_to_apl_long_packet_num_out(1) when last_fifo_to_apl_read = '1' and not saved_fifo_to_apl_long_packet_num_out(2) = '1' and saved_fifo_to_apl_long_packet_num_out(0) = '1' else saved_fifo_to_apl_long_packet_num_out(1); + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_fifo_to_apl_long_packet_num_out <= (others => '0'); + elsif last_fifo_to_apl_read = '1' then + saved_fifo_to_apl_long_packet_num_out <= fifo_to_apl_long_packet_num_out; + end if; + end if; + end process; + --------------------------------------- -- save packet type --------------------------------------- @@ -459,15 +498,15 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or fifo_to_apl_packet_num_out = "11" then + if RESET = '1' or fifo_to_apl_long_packet_num_out = c_F3 then saved_fifo_to_apl_packet_type <= TYPE_ILLEGAL; - elsif fifo_to_apl_packet_num_out = "00" then + elsif fifo_to_apl_long_packet_num_out = c_H0 then saved_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0); end if; end if; end process; --create comb. real packet type - current_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0) when (fifo_to_apl_packet_num_out = "00") + current_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0) when (fifo_to_apl_long_packet_num_out = c_H0) else saved_fifo_to_apl_packet_type; --------------------------------------- @@ -487,19 +526,23 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; process(master_counter, fifo_to_int_data_out, combined_header_F1, registered_trailer_F1, - combined_header_F2, registered_trailer_F2, - combined_header_F3, registered_trailer_F3) + combined_header_F2, registered_trailer_F2, registered_trailer_F0, + combined_header_F3, registered_trailer_F3, combined_header_F0) begin case master_counter is - when "01" => + when c_F0 => + current_combined_header <= combined_header_F0; + current_registered_trailer <= registered_trailer_F0; + current_data <= fifo_to_int_data_out; + when c_F1 => current_combined_header <= combined_header_F1; current_registered_trailer <= registered_trailer_F1; current_data <= fifo_to_int_data_out; - when "10" => + when c_F2 => current_combined_header <= combined_header_F2; current_registered_trailer <= registered_trailer_F2; current_data <= fifo_to_int_data_out; - when "11" => + when c_F3 => current_combined_header <= combined_header_F3; current_registered_trailer <= registered_trailer_F3; current_data <= fifo_to_int_data_out; @@ -516,9 +559,13 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; begin if rising_edge(CLK) then if RESET = '1' then - master_counter <= (others => '0'); + master_counter <= c_H0; elsif next_INT_REPLY_DATAREADY_OUT = '1' then - master_counter <= master_counter + 1; + if master_counter = c_max_word_number then + master_counter <= (others => '0'); + else + master_counter <= master_counter + 1; + end if; end if; end if; end process; @@ -533,6 +580,7 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; if RESET = '1' then fifo_to_apl_read_before <= '0'; else + last_fifo_to_apl_read <= fifo_to_apl_read; if fifo_to_apl_read = '1' then fifo_to_apl_read_before <= '1'; elsif sbuf_to_apl_free = '1' or throw_away = '1' then @@ -548,6 +596,7 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; if RESET = '1' then fifo_to_int_read_before <= '0'; else + last_fifo_to_int_read <= fifo_to_int_read; if fifo_to_int_read = '1' then fifo_to_int_read_before <= '1'; elsif next_INT_REPLY_DATAREADY_OUT = '1' and master_counter /= "00" then --implies sbuf_free @@ -560,10 +609,10 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; --------------------------------------- ---state machine for direction to APL +--state machine for direction to APL --------------------------------------- to_apl : process(fifo_to_apl_full, reg_INT_REPLY_READ_OUT, INT_REPLY_DATAREADY_IN, fifo_to_apl_empty, - fifo_to_apl_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT, + fifo_to_apl_long_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT, sbuf_to_apl_free, INT_REPLY_DATA_IN, INT_REPLY_PACKET_NUM_IN, reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away,state_to_int ) begin @@ -579,14 +628,14 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; case state_to_apl is when sa_IDLE => slave_start <= fifo_to_apl_write; - if APL_WRITE_4_PACKETS = 0 then - next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and (or_all(fifo_to_apl_packet_num_out)) and sbuf_to_apl_free; - throw_away <= not or_all(fifo_to_apl_packet_num_out); + if APL_WRITE_ALL_WORDS = 0 then + next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and not fifo_to_apl_long_packet_num_out(2) and sbuf_to_apl_free; + throw_away <= fifo_to_apl_long_packet_num_out(2); else next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and sbuf_to_apl_free; end if; fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away); - if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and sbuf_to_apl_free = '1' then + if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = c_F3 and sbuf_to_apl_free = '1' then next_state_to_apl <= sa_INACTIVE; slave_end <= '1'; end if; @@ -637,26 +686,26 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; when SEND_HEADER => out_select <= HDR; next_INT_REPLY_DATAREADY_OUT <= sbuf_free; - if master_counter = "11" and sbuf_free = '1' then + if master_counter = c_F3 and sbuf_free = '1' then next_state_to_int <= RUNNING; end if; when RUNNING => - fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(master_counter); - next_INT_REPLY_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or not or_all(master_counter)); + fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2); + next_INT_REPLY_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or master_counter(2)); if APL_SEND_IN = '0' and fifo_was_not_empty = '1' then -- terminate the transfer update_registered_trailer <= '1'; - if fifo_to_int_empty = '1' and master_counter = "11" and sbuf_free = '1' then + if fifo_to_int_empty = '1' and master_counter = c_F3 and sbuf_free = '1' then next_state_to_int <= SEND_TRAILER; -- immediate stop else next_state_to_int <= SHUTDOWN; -- send rest of data / padding end if; end if; when SHUTDOWN => - fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(master_counter); + fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2); next_INT_REPLY_DATAREADY_OUT <= sbuf_free and - ((fifo_to_int_read_before or not or_all(master_counter)) or --write data from fifo - (fifo_to_int_empty and or_all(master_counter))); --fill with padding words - if master_counter = "11" and fifo_to_int_empty = '1' and sbuf_free = '1' then + ((fifo_to_int_read_before or master_counter(2)) or --write data from fifo + (fifo_to_int_empty and not master_counter(2))); --fill with padding words + if master_counter = c_F3 and fifo_to_int_empty = '1' and sbuf_free = '1' then next_state_to_int <= SEND_TRAILER; end if; when SEND_TRAILER => @@ -677,13 +726,11 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; if RESET = '1' then state_to_apl <= sa_IDLE; state_to_int <= INACTIVE; - --reg_INT_SLAVE_READ_OUT <= '0'; sequence_counter <= (others => '0'); fifo_was_not_empty <= '0'; else state_to_apl <= next_state_to_apl; state_to_int <= next_state_to_int; - --reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT; sequence_counter <= next_sequence_counter; fifo_was_not_empty <= next_fifo_was_not_empty; end if; @@ -693,26 +740,28 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; --------------------------------------- --- +-- --------------------------------------- --save target address for passive api reg_hdr_f1: process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then - combined_header_F2 <= (others => '1'); - elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_packet_num_out = "01" then - combined_header_F2 <= fifo_to_apl_data_out; + if current_fifo_to_apl_packet_type = TYPE_HDR then + if fifo_to_apl_long_packet_num_out = c_F1 then + combined_header_F1 <= fifo_to_apl_data_out; + end if; end if; end if; end process; -- combine the next header - combined_header_F1 <= APL_MY_ADDRESS_IN; + combined_header_F0 <= APL_MY_ADDRESS_IN; + combined_header_F2 <= (others => '0'); combined_header_F3(15 downto 14) <= (others => '0'); -- LAY combined_header_F3(13 downto 12) <= (others => '0'); -- VERS combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR combined_header_F3(3 downto 0) <= APL_DTYPE_IN; + combined_trailer_F0 <= (others => '0'); combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16); combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 0); combined_trailer_F3(15 downto 14) <= (others => '0'); -- res. @@ -722,13 +771,13 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; -- connect Transmitter port fifo_to_int_data_in <= APL_DATA_IN; - fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN; + fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN(2) & APL_PACKET_NUM_IN(0); fifo_to_int_write <= (APL_DATAREADY_IN and not fifo_to_int_full); APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing -- connect receiver fifo_to_apl_data_in <= INT_REPLY_DATA_IN; - fifo_to_apl_packet_num_in <= INT_REPLY_PACKET_NUM_IN; + fifo_to_apl_packet_num_in <= INT_REPLY_PACKET_NUM_IN(2) & INT_REPLY_PACKET_NUM_IN(0); INT_REPLY_READ_OUT <= reg_INT_REPLY_READ_OUT; RUN_OUT_gen : process(CLK) @@ -770,11 +819,8 @@ INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; REG3 : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then - registered_trailer_F1 <= (others => '0'); - registered_trailer_F2 <= (others => '0'); - registered_trailer_F3 <= (others => '0'); - elsif update_registered_trailer = '1' then + if update_registered_trailer = '1' then + registered_trailer_F0 <= combined_trailer_F0; registered_trailer_F1 <= combined_trailer_F1; registered_trailer_F2 <= combined_trailer_F2; registered_trailer_F3 <= combined_trailer_F3; diff --git a/trb_net16_dummy_fifo.vhd b/trb_net16_dummy_fifo.vhd index c917472..97ec11d 100644 --- a/trb_net16_dummy_fifo.vhd +++ b/trb_net16_dummy_fifo.vhd @@ -13,15 +13,14 @@ entity trb_net16_dummy_fifo is CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic ); end entity; @@ -30,9 +29,9 @@ architecture arch_trb_net16_dummy_fifo of trb_net16_dummy_fifo is component trb_net_dummy_fifo is generic ( - WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH); + WIDTH : integer := c_DATA_WIDTH + 2); port ( - CLK : in std_logic; + CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data @@ -40,19 +39,18 @@ architecture arch_trb_net16_dummy_fifo of trb_net16_dummy_fifo is DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) + EMPTY_OUT : out std_logic ); end component; - signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH -1 downto 0); + signal din, dout : std_logic_vector(c_DATA_WIDTH + 2 -1 downto 0); begin din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; - din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; + din(c_DATA_WIDTH + 2 -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); - + PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 2 - 1 downto c_DATA_WIDTH); + fifo : trb_net_dummy_fifo port map( CLK => CLK, @@ -63,8 +61,7 @@ begin DATA_OUT => dout, READ_ENABLE_IN => READ_ENABLE_IN, FULL_OUT => FULL_OUT, - EMPTY_OUT => EMPTY_OUT, - DEPTH_OUT => DEPTH_OUT + EMPTY_OUT => EMPTY_OUT ); end architecture; diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd index 212e3cf..a20e08a 100644 --- a/trb_net16_endpoint_0_trg_1_api.vhd +++ b/trb_net16_endpoint_0_trg_1_api.vhd @@ -46,37 +46,36 @@ entity trb_net16_endpoint_0_trg_1_api is MED_ERROR_IN : in std_logic_vector (2 downto 0); MED_STAT_OP : in std_logic_vector (15 downto 0); MED_CTRL_OP : out std_logic_vector (15 downto 0); - + -- APL Transmitter port - APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted - APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in std_logic; -- - APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) + APL_DATAREADY_IN: in std_logic; + APL_READ_OUT: out std_logic; + APL_SHORT_TRANSFER_IN: in std_logic; + APL_DTYPE_IN: in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); + APL_SEND_IN: in std_logic; + APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Receiver port - APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out - APL_READ_IN: in std_logic; -- Read data word - + APL_TYP_OUT: out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT: out std_logic; + APL_READ_IN: in std_logic; + -- APL Control port - APL_RUN_OUT: out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_RUN_OUT: out std_logic; + APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - STAT_api_control_signals: out std_logic_vector(31 downto 0); + + -- Status and control port + STAT_GEN: out std_logic_vector (31 downto 0); + STAT_LOCKED: out std_logic_vector (31 downto 0); + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); + STAT_api_control_signals: out std_logic_vector(31 downto 0); STAT_MPLEX: out std_logic_vector(31 downto 0); CTRL_GEN: in std_logic_vector (31 downto 0); CTRL_LOCKED: in std_logic_vector (31 downto 0); @@ -90,204 +89,200 @@ end entity; architecture trb_net16_endpoint_0_trg_1_api_arch of trb_net16_endpoint_0_trg_1_api is -component trb_net16_iobuf is - - generic ( - IBUF_DEPTH : integer range 0 to 6 := std_FIFO_DEPTH; - IBUF_SECURE_MODE : integer range 0 to 1 := std_IBUF_SECURE_MODE; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; - - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; - - - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_ERROR_IN: in std_logic_vector (2 downto 0); - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN: in std_logic; - - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT: out std_logic; - - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN: in std_logic; - - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT: out std_logic; - - -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); - STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0); - CTRL_GEN: in std_logic_vector (31 downto 0); - STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0) - ); -end component; - -component trb_net16_api_base is - generic ( - API_TYPE : integer range 0 to 1 := c_API_ACTIVE; - FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; - FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; - FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; - SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; - APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted - APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in std_logic; -- - APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out - APL_READ_IN: in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT: out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - - -- Internal direction port - -- This is just a clone from trb_net_iobuf - - INT_MASTER_DATAREADY_OUT: out std_logic; - INT_MASTER_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_IN: in std_logic; - - INT_MASTER_DATAREADY_IN: in std_logic; - INT_MASTER_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_OUT: out std_logic; - - - INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the SLAVE path) - INT_SLAVE_DATAREADY_OUT: out std_logic; - INT_SLAVE_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_IN: in std_logic; - - INT_SLAVE_DATAREADY_IN: in std_logic; - INT_SLAVE_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_OUT: out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -end component; - - - -component trb_net16_io_multiplexer is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); - MED_READ_OUT: out STD_LOGIC; - - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); - MED_READ_IN: in STD_LOGIC; + component trb_net16_iobuf is + generic ( + IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); + + -- Internal direction port + + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN: in std_logic; + + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT: out std_logic; + + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN: in std_logic; + + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + + -- Status and control port + STAT_GEN: out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0); + CTRL_GEN: in std_logic_vector (31 downto 0); + STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0) + ); + end component; - -- Internal direction port - INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + component trb_net16_api_base is + generic ( + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" + ); - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + + -- APL Control port + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + -- master_data_out and slave_data_in are only used in active API for termination + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_IN : in std_logic; + + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; - -- Status and control port - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT: out STD_LOGIC_VECTOR (31 downto 0) - ); -end component; + component trb_net16_io_multiplexer is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; + + -- Internal direction port + INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + + INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + + -- Status and control port + CTRL : in STD_LOGIC_VECTOR (31 downto 0); + STAT : out STD_LOGIC_VECTOR (31 downto 0) + ); + end component; - component trb_net16_term_buf is + component trb_net16_term_buf is port( -- Misc CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic ); end component; @@ -352,14 +347,14 @@ begin m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT; m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2) <= MED_INIT_DATA_OUT; m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH) <= MED_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT; + m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH) <= MED_REPLY_PACKET_NUM_OUT; MED_INIT_READ_IN <= m_READ_IN(i*2); MED_REPLY_READ_IN <= m_READ_IN(i*2+1); MED_IO_DATAREADY_IN <= m_DATAREADY_IN(i); MED_IO_DATA_IN <= m_DATA_IN(c_DATA_WIDTH-1 downto 0); - MED_IO_PACKET_NUM_IN <= m_PACKET_NUM_IN(1 downto 0); + MED_IO_PACKET_NUM_IN <= m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0); m_READ_OUT(i) <= MED_IO_READ_OUT; end generate; genelse: if i /= DAT_CHANNEL generate @@ -370,11 +365,11 @@ begin CLK_EN => CLK_EN, MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto (i*2)*c_NUM_WIDTH), MED_INIT_READ_IN => m_READ_IN(i*2), MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2), + MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), MED_REPLY_READ_IN => m_READ_IN(i*2+1), MED_DATAREADY_IN => m_DATAREADY_IN(i), @@ -431,7 +426,6 @@ begin INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA, INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM, INT_MASTER_READ_OUT => buf_to_apl_INIT_READ, - INT_SLAVE_HEADER_IN => '0', INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA, INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM, @@ -489,7 +483,6 @@ begin INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA, INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM, INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ, - INT_SLAVE_HEADER_IN => '0', INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA, INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM, @@ -546,7 +539,7 @@ IOBUF: trb_net16_iobuf MED_INIT_DATA_OUT => MED_INIT_DATA_OUT, MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT, MED_INIT_READ_IN => MED_INIT_READ_IN, - + MED_DATAREADY_IN => MED_IO_DATAREADY_IN, MED_DATA_IN => MED_IO_DATA_IN, MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, @@ -612,6 +605,6 @@ IOBUF: trb_net16_iobuf INT_READ_OUT => m_READ_IN, CTRL => MPLEX_CTRL ); - + end architecture; - + diff --git a/trb_net16_fifo.vhd b/trb_net16_fifo.vhd deleted file mode 100644 index eec7e4e..0000000 --- a/trb_net16_fifo.vhd +++ /dev/null @@ -1,36 +0,0 @@ --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo - --- The only difference of fifo16 to the original fifo is the division --- into a data and a num port - no change in logic, just for easier use. --- The depth is given in 64Bit-packets! - -library ieee; -use ieee.std_logic_1164.all; -USE ieee.std_logic_signed.ALL; -USE ieee.std_logic_arith.ALL; - -library work; -use work.trb_net_std.all; - -entity trb_net16_fifo is - generic ( - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - DEPTH : integer := 3 -- Depth of the FIFO, 2^(n+1) 64Bit packets - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); -end entity; - - diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index b23741b..13708ef 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -6,22 +6,22 @@ library work; use work.trb_net_std.all; use work.trb_net16_hub_func.all; - entity trb_net16_hub_base is generic ( --hub control - HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 3;--c_SLOW_CTRL_CHANNEL; + HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 0;--c_SLOW_CTRL_CHANNEL; HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES); USE_CHECKSUM : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES); + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0'); - COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; --media interfaces - MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 4; + MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 2; MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; -- settings for apis API_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; @@ -29,6 +29,11 @@ entity trb_net16_hub_base is API_TYPE : hub_api_config_t := (0,0,0,0,0,0,0,0); API_FIFO_TO_INT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1); API_FIFO_TO_APL_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1); + SECURE_MODE_TO_APL : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT : integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS : hub_api_config_t := (0,0,0,0,0,0,0,0); + BROADCAST_BITMASK : hub_api_broadcast_t := (x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF"); + --trigger reading interfaces TRG_NUMBER : integer range 0 to c_MAX_TRG_PER_HUB := 0; TRG_SECURE_MODE : integer range 0 to 1 := c_NO; @@ -36,8 +41,8 @@ entity trb_net16_hub_base is ); port ( CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; --Media interfacces MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); @@ -117,20 +122,19 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal buf_to_hub_INIT_DATAREADY : std_logic_vector (total_point_num-1 downto 0); signal buf_to_hub_INIT_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); - signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); + signal buf_to_hub_INIT_PACKET_NUM: std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal buf_to_hub_INIT_READ : std_logic_vector (total_point_num-1 downto 0); signal hub_to_buf_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0); signal hub_to_buf_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); - signal hub_to_buf_REPLY_PACKET_NUM :std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); + signal hub_to_buf_REPLY_PACKET_NUM : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal hub_to_buf_REPLY_READ : std_logic_vector (total_point_num-1 downto 0); - signal hub_to_buf_REPLY_SEND_HEADER : std_logic_vector(total_point_num-1 downto 0); signal buf_to_hub_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0); signal buf_to_hub_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); - signal buf_to_hub_REPLY_PACKET_NUM :std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); + signal buf_to_hub_REPLY_PACKET_NUM : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal buf_to_hub_REPLY_READ : std_logic_vector (total_point_num-1 downto 0); - signal buf_to_hub_REPLY_SEND_HEADER : std_logic_vector(total_point_num-1 downto 0); + signal buf_to_hub_REPLY_SEND_HEADER : std_logic_vector (total_point_num-1 downto 0); signal HUB_INIT_DATAREADY_OUT : std_logic_vector (total_point_num-1 downto 0); signal HUB_INIT_DATA_OUT : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); @@ -150,17 +154,17 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal HUB_REPLY_READ_OUT : std_logic_vector (total_point_num-1 downto 0); signal HUB_REPLY_SEND_HEADER_OUT : std_logic_vector (total_point_num-1 downto 0); - signal buf_HUB_STAT_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); - signal buf_STAT_POINTS_locked : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0); - signal buf_HUB_STAT_GEN : std_logic_vector (31 downto 0); - signal buf_STAT_DEBUG : std_logic_vector (31 downto 0); - signal buf_CTRL_DEBUG : std_logic_vector (31 downto 0); + signal buf_HUB_STAT_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); + signal buf_STAT_POINTS_locked : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0); + signal buf_HUB_STAT_GEN : std_logic_vector (31 downto 0); + signal buf_STAT_DEBUG : std_logic_vector (31 downto 0); + signal buf_CTRL_DEBUG : std_logic_vector (31 downto 0); signal HC_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); signal HC_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); - signal HC_DATAREADY_IN : std_logic; - signal HC_READ_OUT : std_logic; + signal HC_DATAREADY_IN : std_logic; + signal HC_READ_OUT : std_logic; signal HC_SHORT_TRANSFER_IN : std_logic; signal HC_DTYPE_IN : std_logic_vector (3 downto 0); signal HC_ERROR_PATTERN_IN : std_logic_vector (31 downto 0); @@ -175,8 +179,8 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal HC_SEQNR_OUT : std_logic_vector (7 downto 0); signal HC_STAT_REGS : std_logic_vector (2**3*32-1 downto 0); signal HC_CTRL_REGS : std_logic_vector (2**3*32-1 downto 0); - signal HC_COMMON_STAT_REGS : std_logic_vector(std_COMSTATREG*32-1 downto 0); - signal HC_COMMON_CTRL_REGS : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal HC_COMMON_STAT_REGS : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal HC_COMMON_CTRL_REGS : std_logic_vector(std_COMCTRLREG*32-1 downto 0); signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0); @@ -200,38 +204,38 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal TEMP_OUT : std_logic_vector(11 downto 0); component trb_net16_hub_logic is - generic ( - --media interfaces - POINT_NUMBER : integer range 2 to c_MAX_POINTS_PER_HUB := 2 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - STAT : out std_logic_vector (15 downto 0); - STAT_POINTS_locked : out std_logic_vector (31 downto 0); - STAT_ERRORBITS : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (15 downto 0); - CTRL_activepoints : in std_logic_vector (31 downto 0) - ); -end component; + generic ( + --media interfaces + POINT_NUMBER : integer range 2 to c_MAX_POINTS_PER_HUB := 2 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + STAT : out std_logic_vector (15 downto 0); + STAT_POINTS_locked : out std_logic_vector (31 downto 0); + STAT_ERRORBITS : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (15 downto 0); + CTRL_activepoints : in std_logic_vector (31 downto 0) + ); + end component; component trb_net16_io_multiplexer is port( @@ -239,32 +243,27 @@ end component; CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); - MED_READ_OUT: out STD_LOGIC; - - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); - MED_READ_IN: in STD_LOGIC; - + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; -- Internal direction port - INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - + INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); -- Status and control port - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT: out STD_LOGIC_VECTOR (31 downto 0) + CTRL : in STD_LOGIC_VECTOR (31 downto 0); + STAT : out STD_LOGIC_VECTOR (31 downto 0) ); end component; @@ -286,101 +285,105 @@ end component; RESET : in std_logic; CLK_EN : in std_logic; -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; -- Media is reading - - MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; -- Media is reading - - MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; -- buffer reads a word from media - MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); -- Internal direction port - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN: in std_logic; - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT: out std_logic; - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN: in std_logic; - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT: out std_logic; + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN : in std_logic; + INT_INIT_DATAREADY_IN : in std_logic; + INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT : out std_logic; + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN : in std_logic; + INT_REPLY_DATAREADY_IN : in std_logic; + INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT : out std_logic; -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); - STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0); - CTRL_GEN: in std_logic_vector (31 downto 0); - STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0) + STAT_GEN : out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0); + STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0) ); end component; component trb_net16_api_base is generic ( - API_TYPE : integer range 0 to 1 := c_API_ACTIVE; - FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; - FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; USE_VENDOR_CORES : integer range 0 to 1 := c_YES; SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; - SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" ); + port( -- Misc CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; + -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_DATAREADY_IN : in std_logic; -- Data word is valid and should be transmitted - APL_READ_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) -- Receiver port - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); APL_SEQNR_OUT : out std_logic_vector (7 downto 0); -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + -- master_data_out and slave_data_in are only used in active API for termination INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_IN : in std_logic; INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_OUT : out std_logic; - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_IN : in std_logic; INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_OUT : out std_logic; -- Status and control port STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); @@ -401,31 +404,26 @@ end component; CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr + INT_DATAREADY_OUT : out std_logic; + INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN : in std_logic; + INT_DATAREADY_IN : in std_logic; + INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out std_logic; + -- "mini" APL, just to see terminations coming in + APL_DTYPE_OUT : out std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + APL_GOT_TRM : out std_logic; + APL_RELEASE_TRM : in std_logic; + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) ); end component; component trb_net16_regIO is generic ( - REGISTER_WIDTH : integer range 32 to 32 := 32; - ADDRESS_WIDTH : integer range 8 to 16 := 16; NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers --standard values for output registers @@ -477,19 +475,19 @@ end component; MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); --Common Register in / out - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0); - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); --Custom Register in / out - REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); - REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + REGISTERS_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); + REGISTERS_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); --Internal Data Port - DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); + DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); DAT_READ_ENABLE_OUT : out std_logic; DAT_WRITE_ENABLE_OUT: out std_logic; - DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0); + DAT_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); --Data input can only be used as reaction on read or write access. write operation should return data --if successful - DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0); + DAT_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); DAT_DATAREADY_IN : in std_logic; DAT_NO_MORE_DATA_IN : in std_logic; --finish transmission, when reading from a fifo and it got empty @@ -500,7 +498,6 @@ end component; EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0); STAT : out std_logic_vector(31 downto 0) ); - end component; component trb_net16_term_buf is @@ -509,21 +506,18 @@ end component; CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; - - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; - - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic ); end component; @@ -617,8 +611,14 @@ begin IOBUF: trb_net16_iobuf generic map ( IBUF_DEPTH => calc_depth(i,MII_IBUF_DEPTH, API_FIFO_TO_APL_DEPTH, MII_NUMBER, API_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH), - USE_CHECKSUM => USE_CHECKSUM(k), - IBUF_SECURE_MODE => IBUF_SECURE_MODE + USE_CHECKSUM => USE_CHECKSUM(k), + IBUF_SECURE_MODE => IBUF_SECURE_MODE, + SBUF_VERSION => std_SBUF_VERSION, + OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH, + USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(k), + USE_VENDOR_CORES => USE_VENDOR_CORES, + INIT_CAN_SEND_DATA => c_YES, + REPLY_CAN_SEND_DATA => c_YES ) port map ( -- Misc @@ -630,12 +630,10 @@ begin MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), MED_INIT_READ_IN => m_READ_IN(i*2), - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), MED_REPLY_READ_IN => m_READ_IN(i*2+1), - MED_DATAREADY_IN => m_DATAREADY_IN(i), MED_DATA_IN => m_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), MED_PACKET_NUM_IN => m_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), @@ -643,27 +641,22 @@ begin MED_ERROR_IN => m_ERROR_IN((j+1)*3-1 downto j*3), -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), INT_INIT_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_INIT_READ_IN => buf_to_hub_INIT_READ(i), - INT_INIT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), INT_INIT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_INIT_READ_OUT => hub_to_buf_INIT_READ(i), - INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), INT_REPLY_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_REPLY_READ_IN => buf_to_hub_REPLY_READ(i), - INT_REPLY_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i), INT_REPLY_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_REPLY_READ_OUT => hub_to_buf_REPLY_READ(i), - -- Status and control port STAT_GEN => IOBUF_STAT_GEN((i+1)*32-1 downto i*32), STAT_IBUF_BUFFER => IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32), @@ -742,7 +735,6 @@ begin INT_MASTER_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_MASTER_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_OUT => hub_to_buf_REPLY_READ(i), - INT_SLAVE_HEADER_IN => hub_to_buf_REPLY_SEND_HEADER(i), INT_SLAVE_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), INT_SLAVE_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_SLAVE_PACKET_NUM_OUT => buf_to_hub_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), @@ -769,7 +761,14 @@ begin generic map( API_TYPE => API_TYPE(aploffset), FIFO_TO_INT_DEPTH => API_FIFO_TO_INT_DEPTH(aploffset), - FIFO_TO_APL_DEPTH => API_FIFO_TO_APL_DEPTH(aploffset) + FIFO_TO_APL_DEPTH => API_FIFO_TO_APL_DEPTH(aploffset), + FORCE_REPLY => cfg_FORCE_REPLY(API_CHANNELS(aploffset)), + SBUF_VERSION => std_SBUF_VERSION, + USE_VENDOR_CORES => USE_VENDOR_CORES, + SECURE_MODE_TO_APL => SECURE_MODE_TO_APL, + SECURE_MODE_TO_INT => SECURE_MODE_TO_INT, + APL_WRITE_ALL_WORDS => APL_WRITE_ALL_WORDS(aploffset), + BROADCAST_BITMASK => BROADCAST_BITMASK(aploffset) ) port map( -- Misc @@ -805,7 +804,6 @@ begin INT_MASTER_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_MASTER_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_OUT => hub_to_buf_REPLY_READ(i), - INT_SLAVE_HEADER_IN => hub_to_buf_REPLY_SEND_HEADER(i), INT_SLAVE_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), INT_SLAVE_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_SLAVE_PACKET_NUM_OUT => buf_to_hub_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), @@ -826,7 +824,14 @@ begin generic map( API_TYPE => API_TYPE(aploffset), FIFO_TO_INT_DEPTH => API_FIFO_TO_INT_DEPTH(aploffset), - FIFO_TO_APL_DEPTH => API_FIFO_TO_APL_DEPTH(aploffset) + FIFO_TO_APL_DEPTH => API_FIFO_TO_APL_DEPTH(aploffset), + FORCE_REPLY => cfg_FORCE_REPLY(API_CHANNELS(aploffset)), + SBUF_VERSION => std_SBUF_VERSION, + USE_VENDOR_CORES => USE_VENDOR_CORES, + SECURE_MODE_TO_APL => SECURE_MODE_TO_APL, + SECURE_MODE_TO_INT => SECURE_MODE_TO_INT, + APL_WRITE_ALL_WORDS => APL_WRITE_ALL_WORDS(aploffset), + BROADCAST_BITMASK => BROADCAST_BITMASK(aploffset) ) port map( -- Misc @@ -862,7 +867,6 @@ begin INT_MASTER_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_MASTER_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_OUT => hub_to_buf_INIT_READ(i), - INT_SLAVE_HEADER_IN => '0', INT_SLAVE_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), INT_SLAVE_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_SLAVE_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), @@ -1151,8 +1155,6 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); hub_control : trb_net16_regIO generic map( - REGISTER_WIDTH => 32, - ADDRESS_WIDTH => 16, NUM_STAT_REGS => 3, NUM_CTRL_REGS => 3, INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index cfe8cad..081641f 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -9,14 +9,15 @@ package trb_net16_hub_func is type hub_iobuf_config_t is array(0 to 63) of integer; --2**(c_MUX_WIDTH-1)*c_MAX_MII_PER_HUB-1 type hub_api_config_t is array(0 to 7) of integer; + type hub_api_broadcast_t is array(0 to 7) of std_logic_vector(7 downto 0); type hub_channel_config_t is array(0 to 2**(3-1)-1) of integer; - --hub constraints (only needed for generic configuration) + --hub constraints (only needed for generic configuration) constant c_MAX_MII_PER_HUB : integer := 16; constant c_MAX_API_PER_HUB : integer := 8; constant c_MAX_TRG_PER_HUB : integer := 8; constant c_MAX_POINTS_PER_HUB : integer := 18; - + constant std_HUB_IBUF_DEPTH : hub_iobuf_config_t :=( 6,6,6,6, --MII 0 6,6,6,6, 6,6,6,6, @@ -32,8 +33,8 @@ package trb_net16_hub_func is 6,6,6,6, 6,6,6,6, 6,6,6,6, - 6,6,6,6); --MII 15 - + 6,6,6,6); --MII 15 + function calc_point_number (MII_NUMBER : integer; CHANNEL : integer; HUB_CTRL_CHANNEL : integer; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index c430173..d867683 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -51,22 +51,22 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is ); port( -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; -- port to combinatorial logic - COMB_DATAREADY_IN: in std_logic; --comb logic provides data word - COMB_next_READ_OUT: out std_logic; --sbuf can read in NEXT cycle - COMB_READ_IN: in std_logic; --comb logic IS reading - COMB_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in std_logic_vector(c_NUM_WIDTH-1 downto 0); + COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN : in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); -- Port to synchronous output. - SYN_DATAREADY_OUT: out std_logic; - SYN_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); - SYN_READ_IN: in std_logic; + SYN_DATAREADY_OUT : out STD_LOGIC; + SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + SYN_READ_IN : in STD_LOGIC; -- Status and control port - STAT_BUFFER: out std_logic + STAT_BUFFER : out STD_LOGIC ); end component; component trb_net_priority_arbiter is @@ -119,15 +119,15 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); signal next_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); signal current_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reading_trmF1, reading_trmF2 : std_logic_vector(POINT_NUMBER-1 downto 0); - signal REPLY_combined_trm_F1, REPLY_combined_trm_F2 : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal reading_trmF0, reading_trmF1, reading_trmF2 : std_logic_vector(POINT_NUMBER-1 downto 0); + signal REPLY_combined_trm_F0,REPLY_combined_trm_F1, REPLY_combined_trm_F2 : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal REPLY_MUX_real_reading : std_logic; signal real_activepoints : std_logic_vector(POINT_NUMBER-1 downto 0); - + signal REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0); signal next_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0); signal current_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0); - signal last_header_addr : std_logic_vector(1 downto 0); + signal last_header_addr : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal last_header_data : std_logic_vector(POINT_NUMBER*c_DATA_WIDTH-1 downto 0); signal reading_last_hdr,next_reading_last_hdr : std_logic_vector(POINT_NUMBER-1 downto 0); @@ -146,7 +146,7 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is type state_type is (SENDING_DATA, SENDING_REPLY_TRM); signal current_state, next_state : state_type; - signal packet_counter : std_logic_vector(1 downto 0); + signal packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal data_counter : std_logic_vector(7 downto 0); signal SEQ_NR : std_logic_vector(7 downto 0); signal comb_REPLY_POOL_DATAREADY : std_logic; @@ -157,7 +157,6 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal reply_point_lock, next_point_lock : std_logic; - signal tmp_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); signal comb_REPLY_muxed_DATAREADY : std_logic; signal comb_REPLY_muxed_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); @@ -233,7 +232,7 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; --choosing reply point - INIT_ARBITER: trb_net_priority_arbiter + INIT_ARBITER: trb_net_priority_arbiter generic map (WIDTH => POINT_NUMBER) port map ( CLK => CLK, @@ -302,7 +301,7 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_has_read_from_pool(i) and real_activepoints(i) and not locking_point(i); INIT_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= INIT_POOL_DATA; INIT_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= INIT_POOL_PACKET_NUM; - end generate; + end generate; --locked signals @@ -313,9 +312,9 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; get_locked <= INIT_muxed_DATAREADY; next_locked <= (get_locked or locked) and not release_locked; next_locking_point <= (INIT_DATAREADY_IN) when (locked = '0' and REPLY_POOL_DATAREADY = '0') else locking_point; - --buf_INIT_READ_OUT and + --buf_INIT_READ_OUT and - get_init_locked <= '1' when saved_INIT_TYPE = TYPE_TRM and INIT_muxed_PACKET_NUM = "11" else '0'; + get_init_locked <= '1' when saved_INIT_TYPE = TYPE_TRM and INIT_muxed_PACKET_NUM = c_F3 else '0'; release_init_locked <= release_locked; next_init_locked <= (get_init_locked or init_locked) and not release_init_locked; @@ -354,27 +353,27 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; save_INIT_TYPE : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or (INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = "11") then + if RESET = '1' or (INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = c_F3) then saved_INIT_TYPE <= TYPE_ILLEGAL; - elsif INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = "00" then + elsif INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = c_H0 then saved_INIT_TYPE <= INIT_muxed_DATA(2 downto 0); end if; end if; end process; - current_INIT_TYPE <= INIT_muxed_DATA(2 downto 0) when INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = "00" + current_INIT_TYPE <= INIT_muxed_DATA(2 downto 0) when INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = c_H0 else saved_INIT_TYPE; save_REPLY_TYPE : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or (REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "11") then + if RESET = '1' or (REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_F3) then saved_REPLY_TYPE <= TYPE_ILLEGAL; - elsif REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "00" then + elsif REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_H0 then saved_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0); end if; end if; end process; - current_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0) when REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "00" + current_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0) when REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_H0 else saved_REPLY_TYPE; save_SEQ_NR : process(CLK) @@ -382,7 +381,7 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; if rising_edge(CLK) then if RESET = '1' then SEQ_NR <= (others => '0'); - elsif INIT_POOL_PACKET_NUM = "11" and current_INIT_TYPE = TYPE_HDR then + elsif INIT_POOL_PACKET_NUM = c_F3 and current_INIT_TYPE = TYPE_HDR then SEQ_NR <= INIT_POOL_DATA(11 downto 4); end if; end if; @@ -394,10 +393,10 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; process(REPLY_reading_hdr, REPLY_PACKET_NUM_IN, REPLY_DATA_IN) begin next_REPLY_reading_hdr(i) <= REPLY_reading_hdr(i); - if REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = "11" then + if REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_F3 then next_REPLY_reading_hdr(i) <= '0'; elsif REPLY_DATA_IN(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH) = TYPE_HDR - and REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = "00" then + and REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then next_REPLY_reading_hdr(i) <= '1'; end if; end process; @@ -418,16 +417,16 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; gen_saving_hdr : for i in 0 to POINT_NUMBER-1 generate last_HDR_RAM : trb_net_ram_dp generic map( - depth => 2, + depth => 3, width => 16 ) port map( CLK => CLK, - wr1 => REPLY_reading_hdr(i), + wr1 => current_REPLY_reading_hdr(i), a1 => REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), din1 => REPLY_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), dout1 => open, - a2 => last_header_addr(1 downto 0), + a2 => last_header_addr, dout2 => last_header_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) ); end generate; @@ -441,10 +440,10 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; process(REPLY_reading_trm, REPLY_PACKET_NUM_IN, REPLY_DATA_IN) begin next_REPLY_reading_trm(i) <= REPLY_reading_trm(i); - if REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = "11" then + if REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_F3 then next_REPLY_reading_trm(i) <= '0'; elsif REPLY_DATA_IN(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH) = TYPE_TRM - and REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = "00" then + and REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then next_REPLY_reading_trm(i) <= '1'; end if; end process; @@ -464,28 +463,33 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; gen_reading_trmFn : for i in 0 to POINT_NUMBER-1 generate + reading_trmF0(i) <= not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) + and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2) and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i); reading_trmF1(i) <= not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i); - reading_trmF2(i) <= REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i); end generate; gen_combining_trm : for j in 0 to c_DATA_WIDTH-1 generate process(CLK) - variable tmpF1, tmpF2 : std_logic; + variable tmpF1, tmpF2, tmpF0 : std_logic; begin if rising_edge(CLK) then if RESET = '1' or locked = '0' then + REPLY_combined_trm_F0(j) <= '0'; REPLY_combined_trm_F1(j) <= '0'; REPLY_combined_trm_F2(j) <= '0'; else + tmpF0 := '0'; tmpF1 := '0'; tmpF2 := '0'; for i in 0 to POINT_NUMBER-1 loop + tmpF0 := tmpF0 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF0(i)); tmpF1 := tmpF1 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF1(i)); tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF2(i)); end loop; + REPLY_combined_trm_F0(j) <= REPLY_combined_trm_F0(j) or tmpF0; REPLY_combined_trm_F1(j) <= REPLY_combined_trm_F1(j) or tmpF1; REPLY_combined_trm_F2(j) <= REPLY_combined_trm_F2(j) or tmpF2; end if; @@ -542,20 +546,24 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; begin if rising_edge(CLK) then if RESET = '1' or locked = '0' then - packet_counter <= (others => '0'); + packet_counter <= c_H0; elsif comb_REPLY_POOL_DATAREADY = '1' then - packet_counter <= packet_counter + 1; + if packet_counter = c_max_word_number then + packet_counter <= (others => '0'); + else + packet_counter <= packet_counter + 1; + end if; end if; end if; end process; --counts data packets only gen_data_counter : process(CLK) - begin + begin if rising_edge(CLK) then if RESET = '1' or reply_point_lock = '0' then data_counter <= (others => '0'); - elsif comb_REPLY_POOL_PACKET_NUM="00" and comb_REPLY_POOL_DATAREADY = '1' + elsif comb_REPLY_POOL_PACKET_NUM = c_H0 and comb_REPLY_POOL_DATAREADY = '1' and comb_REPLY_POOL_DATA(2 downto 0) = TYPE_DAT then data_counter <= data_counter + 1; end if; @@ -563,25 +571,25 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; end process; --counter for idle time --- gen_idle_count : process(CLK) --- begin --- if rising_edge(CLK) then --- if RESET = '1' or packet_counter="00" then --- idle_counter <= (others => '0'); --- idle_time_exceeded <= '0'; --- elsif or_all(REPLY_MUX_reading and REPLY_DATAREADY_IN) = '0' and idle_time_exceeded = '0' then --- idle_counter <= idle_counter + 1; --- if idle_counter = c_MAX_IDLE_TIME_PER_PACKET then --- idle_time_exceeded <= '1'; --- end if; --- end if; --- end if; --- end process; + gen_idle_count : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or packet_counter = c_H0 then + idle_counter <= (others => '0'); + idle_time_exceeded <= '0'; + elsif or_all(REPLY_MUX_reading and REPLY_DATAREADY_IN) = '0' and idle_time_exceeded = '0' then + idle_counter <= idle_counter + 1; + if idle_counter = c_MAX_IDLE_TIME_PER_PACKET then + idle_time_exceeded <= '1'; + end if; + end if; + end if; + end process; --REPLY mux select input ----------------------------------- - REPLY_ARBITER: trb_net_priority_arbiter +---------------------------------- + REPLY_ARBITER: trb_net_priority_arbiter generic map ( WIDTH => POINT_NUMBER ) @@ -614,7 +622,7 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; next_reading_last_hdr <= (others => '0'); next_resending_header <= '0'; --release lock if TRM is read - if comb_REPLY_muxed_PACKET_NUM = "00" and or_all(REPLY_MUX_reading and REPLY_DATAREADY_IN) = '1' then + if comb_REPLY_muxed_PACKET_NUM = c_H0 and or_all(REPLY_MUX_reading and REPLY_DATAREADY_IN) = '1' then if comb_REPLY_muxed_DATA(2 downto 0) = TYPE_TRM then next_point_lock <= '0'; else @@ -631,7 +639,7 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; next_resending_header <= '1'; next_reading_last_hdr <= reply_arbiter_result; REPLY_MUX_reading <= (others => '0'); - if resending_header = '1' and comb_REPLY_muxed_PACKET_NUM = "11" and comb_REPLY_muxed_DATAREADY = '1' then + if resending_header = '1' and comb_REPLY_muxed_PACKET_NUM = c_F3 and comb_REPLY_muxed_DATAREADY = '1' then next_resending_header <= '0'; next_reading_last_hdr <= (others => '0'); end if; @@ -659,7 +667,7 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; --REPLY mux ----------------------------------- +---------------------------------- gen_reply_mux1 : for i in 0 to c_DATA_WIDTH-1 generate data_mux : process(REPLY_DATA_IN, REPLY_MUX_reading,last_header_data, reading_last_hdr) variable tmp_data : std_logic; @@ -690,8 +698,8 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; --REPLY POOL state machine ----------------------------------- - reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, +---------------------------------- + reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, REPLY_combined_trm_F0, send_reply_trm, SEQ_NR, REPLY_combined_trm_F1, REPLY_combined_trm_F2, comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, init_locked, comb_REPLY_muxed_PACKET_NUM, waiting_for_init_finish) @@ -720,11 +728,13 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; next_waiting_for_init_finish <= '0'; end if; case packet_counter is - when "01" => + when c_F0 => + comb_REPLY_POOL_DATA <= REPLY_combined_trm_F0; + when c_F1 => comb_REPLY_POOL_DATA <= REPLY_combined_trm_F1; - when "10" => + when c_F2 => comb_REPLY_POOL_DATA <= REPLY_combined_trm_F2; - when "11" => + when c_F3 => comb_REPLY_POOL_DATA <= "0000" & SEQ_NR & "0000"; if REPLY_POOL_next_read = '1' and (init_locked = '1') then release_locked <= '1'; --release only when init has finished too diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index e7b6afe..2f24bb4 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -3,7 +3,7 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; +USE IEEE.numeric_std.ALL; USE IEEE.std_logic_UNSIGNED.ALL; library work; @@ -58,22 +58,21 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is end component; component trb_net16_fifo is generic ( - DEPTH : integer := 4; - USE_VENDOR_CORES : integer := c_YES - ); + USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 -- Depth of the FIFO + ); port ( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); WRITE_ENABLE_IN : in std_logic; DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic ); end component; @@ -106,11 +105,10 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal fifo_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal fifo_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal fifo_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal fifo_packet_num_in : std_logic_vector(1 downto 0); + signal fifo_packet_num_out : std_logic_vector(1 downto 0); signal fifo_write, fifo_read : std_logic; signal fifo_full, fifo_empty : std_logic; - signal fifo_depth : std_logic_vector(7 downto 0); signal current_packet_type : std_logic_vector(3 downto 0); signal saved_packet_type : std_logic_vector(3 downto 0); @@ -133,7 +131,8 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_UNDEFINED_ERROR); signal current_error_state, next_error_state : ERROR_STATE; signal next_rec_buffer_size_out, current_rec_buffer_size_out: std_logic_vector(3 downto 0); - + signal fifo_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal saved_fifo_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal CRC_RESET, CRC_enable : std_logic; signal CRC_match : std_logic; @@ -160,12 +159,27 @@ begin PACKET_NUM_OUT => fifo_packet_num_out, READ_ENABLE_IN => fifo_read, FULL_OUT => fifo_full, - EMPTY_OUT => fifo_empty, - DEPTH_OUT => fifo_depth + EMPTY_OUT => fifo_empty ); fifo_data_in <= MED_DATA_IN; - fifo_packet_num_in <= MED_PACKET_NUM_IN; + fifo_packet_num_in <= MED_PACKET_NUM_IN(2) & MED_PACKET_NUM_IN(0); + +--regenerate long packet numbers + fifo_long_packet_num_out(2) <= fifo_packet_num_out(1); + fifo_long_packet_num_out(0) <= fifo_packet_num_out(0); + fifo_long_packet_num_out(1) <= not saved_fifo_long_packet_num_out(1) when last_fifo_read = '1' and not saved_fifo_long_packet_num_out(2) = '1' and saved_fifo_long_packet_num_out(0) = '1' else saved_fifo_long_packet_num_out(1); + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_fifo_long_packet_num_out <= (others => '0'); + elsif last_fifo_read = '1' then + saved_fifo_long_packet_num_out <= fifo_long_packet_num_out; + end if; + end if; + end process; ------------------------ --save the current packet type (including init/reply channel) @@ -175,7 +189,7 @@ begin if rising_edge(CLK) then if RESET = '1' then saved_packet_type <= '1' & TYPE_ILLEGAL; - elsif MED_PACKET_NUM_IN = "00" then + elsif MED_PACKET_NUM_IN = c_H0 then saved_packet_type <= MED_DATA_IN(3 downto 0); end if; end if; @@ -184,17 +198,17 @@ begin process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or fifo_packet_num_out = "11" then + if RESET = '1' then saved_fifo_packet_type <= '1' & TYPE_ILLEGAL; - elsif fifo_packet_num_out = "00" then + elsif fifo_long_packet_num_out = c_H0 then saved_fifo_packet_type <= fifo_data_out(3 downto 0); end if; end if; end process; --create comb. real packet type - current_packet_type <= MED_DATA_IN(3 downto 0) when (MED_PACKET_NUM_IN = "00") + current_packet_type <= MED_DATA_IN(3 downto 0) when (MED_PACKET_NUM_IN = c_H0) else saved_packet_type; - current_fifo_packet_type <= fifo_data_out(3 downto 0) when (fifo_packet_num_out = "00") + current_fifo_packet_type <= fifo_data_out(3 downto 0) when (fifo_long_packet_num_out = c_H0) else saved_fifo_packet_type; gen_crc : if USE_CHECKSUM = 1 generate @@ -207,13 +221,13 @@ begin CRC_OUT => open, CRC_match => CRC_match ); - process(last_fifo_read, fifo_packet_num_out, current_fifo_packet_type) + process(last_fifo_read, fifo_long_packet_num_out, current_fifo_packet_type) begin - CRC_enable <= last_fifo_read and or_all(fifo_packet_num_out); + CRC_enable <= last_fifo_read and not fifo_long_packet_num_out(2); if current_fifo_packet_type = TYPE_TRM or (current_fifo_packet_type = TYPE_EOB) then CRC_enable <= '0'; end if; - if current_fifo_packet_type = TYPE_EOB and fifo_packet_num_out = "11" then + if current_fifo_packet_type = TYPE_EOB and fifo_long_packet_num_out = c_F3 then CRC_enable <= '1'; end if; end process; @@ -239,11 +253,11 @@ begin next_error_state <= current_error_state; if MED_DATAREADY_IN = '1' and reg_read_out= '1' then if current_packet_type(2 downto 0) = TYPE_ACK and USE_ACKNOWLEDGE = 1 then - if MED_PACKET_NUM_IN = "00" and current_error_state /= GOT_OVERFLOW_ERROR then + if MED_PACKET_NUM_IN = c_H0 and current_error_state /= GOT_OVERFLOW_ERROR then got_ack_init_internal <= not current_packet_type(3); got_ack_reply_internal <= current_packet_type(3); end if; - if MED_PACKET_NUM_IN = "10" then + if MED_PACKET_NUM_IN = c_F1 then next_rec_buffer_size_out <= MED_DATA_IN(3 downto 0); end if; elsif not (current_packet_type(2 downto 0) = TYPE_ILLEGAL) then @@ -337,12 +351,12 @@ begin end generate; - process(fifo_data_out, fifo_packet_num_out, sbuf_init_free, RESET, + process(fifo_data_out, fifo_long_packet_num_out, sbuf_init_free, RESET, fifo_empty, sbuf_reply_free, last_fifo_read, current_fifo_packet_type, fifo_read_before, INT_INIT_READ_IN, INT_REPLY_READ_IN, CRC_match) begin tmp_INT_DATA_OUT <= fifo_data_out; - tmp_INT_PACKET_NUM_OUT <= fifo_packet_num_out; + tmp_INT_PACKET_NUM_OUT <= fifo_long_packet_num_out; tmp_INT_INIT_DATAREADY_OUT <= '0'; tmp_INT_REPLY_DATAREADY_OUT <= '0'; got_eob_init_out <= '0'; @@ -350,7 +364,7 @@ begin throw_away <= '0'; CRC_RESET <= RESET; if USE_CHECKSUM = 1 then - if current_fifo_packet_type = TYPE_TRM and fifo_packet_num_out = "10" then + if current_fifo_packet_type = TYPE_TRM and fifo_long_packet_num_out = c_F2 then tmp_INT_DATA_OUT(3) <= fifo_data_out(3) or not CRC_match; CRC_RESET <= '1'; end if; @@ -376,7 +390,7 @@ begin end if; if USE_ACKNOWLEDGE = 1 then if ( current_fifo_packet_type(2 downto 0) = TYPE_EOB - or current_fifo_packet_type(2 downto 0) = TYPE_TRM) and fifo_packet_num_out = "11" then + or current_fifo_packet_type(2 downto 0) = TYPE_TRM) and fifo_long_packet_num_out = c_F3 then got_eob_init_out <= not current_fifo_packet_type(3); got_eob_reply_out <= current_fifo_packet_type(3); end if; @@ -431,7 +445,7 @@ begin -- make STAT_BUFFER - STAT_BUFFER(3 downto 0) <= (fifo_depth(3 downto 0)); + STAT_BUFFER(3 downto 0) <= std_logic_vector(to_unsigned(DEPTH,4)); STAT_BUFFER(7 downto 4) <= current_rec_buffer_size_out; gen_ack2 : if USE_ACKNOWLEDGE = 1 generate diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index b24a109..952ed7b 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -15,30 +15,30 @@ entity trb_net16_io_multiplexer is CLK_EN : in std_logic; -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); - MED_READ_OUT: out STD_LOGIC; + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); - MED_READ_IN: in STD_LOGIC; + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; -- Internal direction port - INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); -- Status and control port - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT: out STD_LOGIC_VECTOR (31 downto 0) + CTRL : in STD_LOGIC_VECTOR (31 downto 0); + STAT : out STD_LOGIC_VECTOR (31 downto 0) ); end trb_net16_io_multiplexer; @@ -58,14 +58,14 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is RESET : in std_logic; CLK_EN : in std_logic; -- port to combinatorial logic - COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + COMB_DATAREADY_IN : in STD_LOGIC; + COMB_next_READ_OUT: out STD_LOGIC; + COMB_READ_IN : in STD_LOGIC; + COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); -- Port to synchronous output. SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); SYN_READ_IN : in STD_LOGIC; -- Status and control port @@ -75,17 +75,17 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is component trb_net_priority_arbiter is generic ( - WIDTH : integer := 2**c_MUX_WIDTH + WIDTH : integer := 8 ); port( -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - ENABLE : in std_logic; - CTRL: in STD_LOGIC_VECTOR (31 downto 0) + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INPUT_IN : in std_logic_vector (WIDTH-1 downto 0); + RESULT_OUT: out std_logic_vector (WIDTH-1 downto 0); + ENABLE : in std_logic; + CTRL : in std_logic_vector (31 downto 0) ); end component; @@ -95,14 +95,14 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); --signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); signal mux_read, mux_enable, mux_next_READ: STD_LOGIC; - signal current_mux_buffer: STD_LOGIC_VECTOR (c_DATA_WIDTH+2-1 downto 0); + signal current_mux_buffer: STD_LOGIC_VECTOR (c_DATA_WIDTH+c_NUM_WIDTH-1 downto 0); signal endpoint_locked, next_endpoint_locked: std_logic; signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); - signal current_mux_packet_number : std_logic_vector (1 downto 0); + signal current_mux_packet_number : std_logic_vector (c_NUM_WIDTH-1 downto 0); signal last_mux_enable : std_logic; signal arbiter_CLK_EN : std_logic; - signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR ((c_DATA_WIDTH)-1 downto 0); - signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (1 downto 0); + signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); -- signal demux_comb_dataready_in : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); begin ------------------------------------------------------------------------------- @@ -135,9 +135,8 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is end process; end generate; - INT_DATA_OUT <= buf_INT_DATA_OUT; - INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; - + INT_DATA_OUT <= buf_INT_DATA_OUT; + INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; --current_demux_READ <= INT_READ_IN; demux_next_READ <= (others => '1'); @@ -149,16 +148,14 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is begin next_demux_dr <= demux_dr_tmp; --(others => '0'); current_demux_READ <= (others => '0'); - -- generate the READ_OUT next_MED_READ_OUT <= '1'; --and_all(demux_next_READ or INT_READ_IN); -- - -- (follow instruction on sbuf) current_demux_READ <= (others => '0'); if current_MED_READ_OUT = '1' then current_demux_READ <= (others => '1'); end if; if current_MED_READ_OUT = '1' and MED_DATAREADY_IN = '1' then - if MED_PACKET_NUM_IN = "00" then --demux_dr_tmp only valid on packet 0, use saved demux_dr otherwise + if MED_PACKET_NUM_IN = "100" then --demux_dr_tmp only valid on packet 0, use saved demux_dr otherwise next_demux_dr <= next_demux_dr_tmp; --enable DR on the sbufs else next_demux_dr <= demux_dr_tmp; @@ -189,7 +186,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is if rising_edge(CLK) then if RESET = '1' then demux_dr_tmp <= (others => '0'); - elsif current_MED_READ_OUT = '1' and MED_DATAREADY_IN = '1' and MED_PACKET_NUM_IN = "00" then + elsif current_MED_READ_OUT = '1' and MED_DATAREADY_IN = '1' and MED_PACKET_NUM_IN = "100" then demux_dr_tmp <= next_demux_dr_tmp; end if; end if; @@ -231,9 +228,9 @@ ARBITER: trb_net_priority_arbiter process(current_mux_buffer, mux_read, endpoint_locked, current_mux_packet_number) begin next_endpoint_locked <= endpoint_locked; - if current_mux_packet_number = "11" and mux_read = '1' then + if current_mux_packet_number = "011" and mux_read = '1' then next_endpoint_locked <= '0'; - elsif current_mux_packet_number = "00" and mux_read = '1' then + elsif current_mux_packet_number = "100" and mux_read = '1' then next_endpoint_locked <= '1'; end if; end process; @@ -271,8 +268,8 @@ ARBITER: trb_net_priority_arbiter -- else final_INT_READ_OUT; STAT(15 downto 0) <= (others => '0'); - STAT(17 downto 16) <= current_mux_buffer(c_DATA_WIDTH+1 downto c_DATA_WIDTH) xor current_mux_packet_number; - STAT(31 downto 18) <= (others => '0'); + STAT(18 downto 16) <= current_mux_buffer(c_DATA_WIDTH+c_NUM_WIDTH-1 downto c_DATA_WIDTH) xor current_mux_packet_number; + STAT(31 downto 19) <= (others => '0'); process(CLK) @@ -293,9 +290,13 @@ ARBITER: trb_net_priority_arbiter begin if rising_edge(CLK) then if RESET = '1' then - current_mux_packet_number <= "00"; + current_mux_packet_number <= c_H0; elsif mux_read = '1' then - current_mux_packet_number <= current_mux_packet_number + 1; + if current_mux_packet_number = c_max_word_number then + current_mux_packet_number <= (others => '0'); + else + current_mux_packet_number <= current_mux_packet_number + 1; + end if; end if; end if; end process; @@ -313,7 +314,7 @@ ARBITER: trb_net_priority_arbiter COMB_next_READ_OUT => mux_next_READ, COMB_READ_IN => '1', COMB_DATA_IN => current_mux_buffer(c_DATA_WIDTH-1 downto 0), - COMB_PACKET_NUM_IN => current_mux_buffer(c_DATA_WIDTH+1 downto c_DATA_WIDTH), + COMB_PACKET_NUM_IN => current_mux_buffer(c_DATA_WIDTH+c_NUM_WIDTH-1 downto c_DATA_WIDTH), SYN_DATAREADY_OUT => MED_DATAREADY_OUT, SYN_DATA_OUT => MED_DATA_OUT, SYN_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, @@ -322,7 +323,7 @@ ARBITER: trb_net_priority_arbiter process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN) - variable var_mux_buffer : STD_LOGIC_VECTOR (c_DATA_WIDTH+2-1 downto 0); + variable var_mux_buffer : STD_LOGIC_VECTOR (c_DATA_WIDTH+c_NUM_WIDTH-1 downto 0); variable j : integer range 0 to c_MUX_WIDTH-1 := 0; variable k : integer range 0 to 2**c_MUX_WIDTH-1 := 0; begin @@ -341,7 +342,7 @@ ARBITER: trb_net_priority_arbiter else var_mux_buffer(j) := var_mux_buffer(j) or (INT_PACKET_NUM_IN(c_NUM_WIDTH*i+j-c_DATA_WIDTH) and current_INT_READ_OUT(i)); end if; - if current_INT_READ_OUT(i) = '1' and INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i) = "00" then + if current_INT_READ_OUT(i) = '1' and INT_PACKET_NUM_IN(c_NUM_WIDTH*(i+1)-1 downto c_NUM_WIDTH*i) = "100" then k := i; else k := k; diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index 7d3c3c9..9c553c3 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -25,52 +25,49 @@ entity trb_net16_iobuf is RESET : in std_logic; CLK_EN : in std_logic; -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; - - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; - - - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_ERROR_IN: in std_logic_vector (2 downto 0); - - + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); -- Internal direction port - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN: in std_logic; + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN : in std_logic; - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT: out std_logic; + INT_INIT_DATAREADY_IN : in std_logic; + INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT : out std_logic; - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN: in std_logic; + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN : in std_logic; - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT: out std_logic; + INT_REPLY_DATAREADY_IN : in std_logic; + INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT : out std_logic; -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); - STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0); - CTRL_GEN: in std_logic_vector (31 downto 0); - STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0) + STAT_GEN : out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0); + STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0) ); end entity; diff --git a/trb_net16_med_16_SDR_OS.vhd b/trb_net16_med_16_SDR_OS.vhd index a3e2273..2cf8393 100644 --- a/trb_net16_med_16_SDR_OS.vhd +++ b/trb_net16_med_16_SDR_OS.vhd @@ -126,7 +126,7 @@ architecture trb_net16_med_16_SDR_OS_arch of trb_net16_med_16_SDR_OS is signal buf_INT_DATAREADY_OUT : std_logic; - signal rx_packet_counter : std_logic_vector(1 downto 0); + signal rx_packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal wait_for_startup : std_logic; signal wait_for_startup_slow : std_logic; signal rx_CLK_counter : std_logic_vector(4 downto 0); @@ -202,7 +202,11 @@ begin else buf_INT_DATA_IN <= INT_DATA_IN; tx_datavalid <= INT_DATAREADY_IN and buf_INT_READ_OUT; - tx_first_packet <= not or_all(INT_PACKET_NUM_IN); + if INT_PACKET_NUM_IN = c_H0 then + tx_first_packet <= '1'; + else + tx_first_packet <= '0'; + end if; tx_reset <= buf_tx_reset; buf_tx_reset <= next_tx_reset; tx_parity <= xor_all(INT_DATA_IN); @@ -318,9 +322,13 @@ process(CLK) begin if rising_edge(CLK) then if RESET = '1' or med_reset = '1' then - rx_packet_counter <= "00"; + rx_packet_counter <= "100"; elsif buf_INT_DATAREADY_OUT = '1' then - rx_packet_counter <= rx_packet_counter + 1; + if rx_packet_counter = c_max_word_number then + rx_packet_counter <= (others => '0'); + else + rx_packet_counter <= rx_packet_counter + 1; + end if; end if; end if; end process; @@ -366,7 +374,7 @@ process(CLK) INT_ERROR_OUT <= ERROR_NC; elsif (buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(16) = '0') then --Parity error INT_ERROR_OUT <= ERROR_ENCOD; - elsif (rx_packet_counter /= "00" and buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(17) = '1') then + elsif (rx_packet_counter /= "100" and buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(17) = '1') then INT_ERROR_OUT <= ERROR_FATAL; --Counter error else INT_ERROR_OUT <= ERROR_OK; diff --git a/trb_net16_med_ecp_sfp.vhd b/trb_net16_med_ecp_sfp.vhd new file mode 100644 index 0000000..4d8f387 --- /dev/null +++ b/trb_net16_med_ecp_sfp.vhd @@ -0,0 +1,399 @@ +--Media interface for Lattice ECP2M using PCS at 2GHz + +--Still missing: link reset features, clock switching after lock + + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + +entity trb_net16_med_ecp_sfp is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_ERROR_OUT : out std_logic_vector(2 downto 0); + + REFCLK2CORE : out std_logic; + --SFP Connection + SD_RXD_P : in std_logic; + SD_RXD_N : in std_logic; + SD_TXD_P : out std_logic; + SD_TXD_N : out std_logic; + SD_REFCLK_P : in std_logic; + SD_REFCLK_N : in std_logic; + -- Status and control port + STAT_OP: out std_logic_vector (15 downto 0); + CTRL_OP: in std_logic_vector (15 downto 0); + + STAT_DEBUG: out std_logic_vector (63 downto 0); + CTRL_DEBUG: in std_logic_vector (63 downto 0) + + ); +end entity; + +architecture med_ecp_sfp of trb_net16_med_ecp_sfp is + + component serdes + port( + core_txrefclk, core_rxrefclk : IN std_logic; --CLK +-- refclkp, refclkn : in std_logic; + hdinp2 : IN std_logic; --RX Data input + hdinn2 : IN std_logic; --RX Data input + ff_rxiclk_ch2 : IN std_logic; --CLK ff_txhalfclk + ff_txiclk_ch2 : IN std_logic; --CLK ff_txhalfclk + ff_ebrd_clk_2 : IN std_logic; --CLK ff_txfullclk + ff_txdata_ch2 : IN std_logic_vector(15 downto 0); --internal tx data + ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0); --control character flag 00 + ff_force_disp_ch2 : IN std_logic_vector(1 downto 0); --activate disparity value 00 + ff_disp_sel_ch2 : IN std_logic_vector(1 downto 0); --disparity value in 00 + ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0); --disparity check 00 + ffc_rrst_ch2 : IN std_logic; --RESET + ffc_signal_detect_ch2 : IN std_logic; --enable signal detect + ffc_enable_cgalign_ch2 : IN std_logic; --enable comma aligner 0 + ffc_lane_tx_rst_ch2 : IN std_logic; --RESET + ffc_lane_rx_rst_ch2 : IN std_logic; -- reset PCS (word alignment) + ffc_txpwdnb_ch2 : IN std_logic; --power down active low + ffc_rxpwdnb_ch2 : IN std_logic; --power down active low + ffc_macro_rst : IN std_logic; --RESET + ffc_quad_rst : IN std_logic; --RESET + ffc_trst : IN std_logic; --RESET + hdoutp2 : OUT std_logic; --TX Data output + hdoutn2 : OUT std_logic; --TX Data output + ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0); --internal rx data + ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0); --control character flag + ff_rxfullclk_ch2 : OUT std_logic; --RX recovered CLK + ff_rxhalfclk_ch2 : OUT std_logic; --+ --RX half recovered CLK + ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0); --disparity error flag + ff_cv_ch2 : OUT std_logic_vector(1 downto 0); --code violation flag + ffs_rlos_lo_ch2 : OUT std_logic; --NOT signal loss + ffs_ls_sync_status_ch2 : OUT std_logic; --+ --link state machine status + ffs_cc_underrun_ch2 : OUT std_logic; --Clock compensator FIFO error + ffs_cc_overrun_ch2 : OUT std_logic; --Clock compensator FIFO error + ffs_txfbfifo_error_ch2 : OUT std_logic; --TX FIFO error + ffs_rxfbfifo_error_ch2 : OUT std_logic; --RX FIFO error + ffs_rlol_ch2 : OUT std_logic; --Clock Recovery error + oob_out_ch2 : OUT std_logic; --internal output same as real serdes output + ff_txfullclk : OUT std_logic; --TX CLK + ff_txhalfclk : OUT std_logic; --TX CLK/2 <- interface CLK from MED to Serdes + refck2core : OUT std_logic; --+ --Reference CLK + ffs_plol : OUT std_logic --TX PLL error (not locked) + ); + end component; + + component trb_net_fifo_16bit_bram_dualport is + generic( + USE_STATUS_FLAGS : integer := c_YES + ); + port ( + read_clock_in: in std_logic; + write_clock_in: in std_logic; + read_enable_in: in std_logic; + write_enable_in: in std_logic; + fifo_gsr_in: in std_logic; + write_data_in: in std_logic_vector(17 downto 0); + read_data_out: out std_logic_vector(17 downto 0); + full_out: out std_logic; + empty_out: out std_logic; + fifostatus_out: out std_logic_vector(3 downto 0); + valid_read_out: out std_logic; + almost_empty_out:out std_logic; + almost_full_out :out std_logic + ); + end component; + + + signal REFCLK : std_logic; + signal refck2core : std_logic; + --reset signals + signal ffc_quad_rst : std_logic; + signal ffc_lane_tx_rst_ch2 : std_logic; + signal ffc_lane_rx_rst_ch2 : std_logic; + --serdes connections + signal tx_data : std_logic_vector(15 downto 0); + signal tx_k : std_logic_vector(1 downto 0); + signal rx_data : std_logic_vector(15 downto 0); + signal rx_k : std_logic_vector(1 downto 0); + signal link_ok : std_logic_vector(0 downto 0); + signal link_error : std_logic_vector(9 downto 0); + signal ff_rxhalfclk : std_logic; + signal ff_txhalfclk : std_logic; + --rx fifo signals + signal fifo_rx_rd_en : std_logic; + signal fifo_rx_wr_en : std_logic; + signal fifo_rx_reset : std_logic; + signal fifo_rx_din : std_logic_vector(17 downto 0); + signal fifo_rx_dout : std_logic_vector(17 downto 0); + signal fifo_rx_full : std_logic; + signal fifo_rx_empty : std_logic; + --tx fifo signals + signal fifo_tx_rd_en : std_logic; + signal fifo_tx_wr_en : std_logic; + signal fifo_tx_reset : std_logic; + signal fifo_tx_din : std_logic_vector(17 downto 0); + signal fifo_tx_dout : std_logic_vector(17 downto 0); + signal fifo_tx_full : std_logic; + signal fifo_tx_empty : std_logic; + --rx path + signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal reset_interface : std_logic; + signal buf_MED_DATAREADY_OUT : std_logic; + signal swap_bytes : std_logic; + signal last_rx : std_logic_vector(8 downto 0); + --tx path + signal last_fifo_tx_empty : std_logic; + --link status + type med_state_t is (start, waitplolandrlol, waitrxallow, waittxallow, working); + signal state : med_state_t; + signal state_bits : std_logic_vector(2 downto 0); + signal counter : std_logic_vector(28 downto 0); + signal tx_allow : std_logic; + signal rx_allow : std_logic; + + +begin + REFCLK2CORE <= refck2core; + +--Instantiation of serdes module +--------------------- + + s : serdes + PORT map( + core_txrefclk => CLK, --CLK + core_rxrefclk => CLK, + hdinp2 => SD_RXD_P, --RX Data input + hdinn2 => SD_RXD_N, --RX Data input + ff_rxiclk_ch2 => ff_rxhalfclk, --CLK ff_txhalfclk + ff_txiclk_ch2 => ff_txhalfclk, --CLK ff_txhalfclk + ff_ebrd_clk_2 => ff_rxhalfclk, --CLK ff_txfullclk + ff_txdata_ch2 => tx_data, --internal tx data + ff_tx_k_cntrl_ch2 => tx_k, --control character flag 00 + ff_force_disp_ch2 => "00", --activate disparity value 00 + ff_disp_sel_ch2 => "00", --disparity value in 00 + ff_correct_disp_ch2 => "00", --disparity check 00 + ffc_rrst_ch2 => '0', --RESET + ffc_signal_detect_ch2 => '1', --enable signal detect + ffc_enable_cgalign_ch2 => '1', --enable comma aligner 0 + ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2, + ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2, + ffc_txpwdnb_ch2 => '1', --power down active low + ffc_rxpwdnb_ch2 => '1', --power down active low + ffc_macro_rst => '0', --RESET + ffc_quad_rst => ffc_quad_rst, --RESET + ffc_trst => '0', --RESET + hdoutp2 => SD_TXD_P, --TX Data output + hdoutn2 => SD_TXD_N, --TX Data output + ff_rxdata_ch2 => rx_data, --internal rx data + ff_rx_k_cntrl_ch2 => rx_k, --control character flag + ff_rxfullclk_ch2 => open, --RX recovered CLK + ff_rxhalfclk_ch2 => ff_rxhalfclk, --RX half recovered CLK + ff_disp_err_ch2 => open, --disparity error flag + ff_cv_ch2 => link_error(7 downto 6), --code violation flag + ffs_rlos_lo_ch2 => link_error(8), --signal loss + ffs_ls_sync_status_ch2 => link_ok(0), --link state machine status + ffs_cc_underrun_ch2 => link_error(0), --Clock compensator FIFO error + ffs_cc_overrun_ch2 => link_error(1), --Clock compensator FIFO error + ffs_txfbfifo_error_ch2 => link_error(2), --TX FIFO error + ffs_rxfbfifo_error_ch2 => link_error(3), --RX FIFO error + ffs_rlol_ch2 => link_error(4), --Clock Recovery error + oob_out_ch2 => open, --internal output same as real serdes output + ff_txfullclk => open, --TX CLK + ff_txhalfclk => ff_txhalfclk, --TX CLK/2 <- interface CLK from MED to Serdes + refck2core => refck2core, --Reference CLK + ffs_plol => link_error(5) --TX PLL error (not locked) + ); + + +--RX Fifo & Data output +--------------------- + FIFO_SFP_TO_INT: trb_net_fifo_16bit_bram_dualport + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( + read_clock_in => CLK, + write_clock_in => ff_rxhalfclk, + read_enable_in => fifo_rx_rd_en, + write_enable_in => fifo_rx_wr_en, + fifo_gsr_in => fifo_rx_reset, + write_data_in => fifo_rx_din, + read_data_out => fifo_rx_dout, + full_out => fifo_rx_full, + empty_out => fifo_rx_empty + ); + + fifo_rx_reset <= reset or not rx_allow; + fifo_rx_rd_en <= '1'; + + process(ff_rxhalfclk) + begin + if rising_edge(ff_rxhalfclk) then + if swap_bytes = '0' then + fifo_rx_din <= rx_k & rx_data; + fifo_rx_wr_en <= not or_all(rx_k) and rx_allow; + else + last_rx <= rx_k(1) & rx_data(15 downto 8); + fifo_rx_din <= rx_k(1) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0); + fifo_rx_wr_en <= not last_rx(8) and not rx_k(1) and rx_allow; + end if; + end if; + end process; + + MED_DATA_OUT <= fifo_rx_dout(15 downto 0); + buf_MED_DATAREADY_OUT <= not fifo_rx_dout(17) and not fifo_rx_dout(16); + MED_PACKET_NUM_OUT <= rx_counter; + MED_READ_OUT <= tx_allow; + MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; + +--rx packet counter +--------------------- + rx_counter_p : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or reset_interface = '1' then + rx_counter <= c_H0; + else + if buf_MED_DATAREADY_OUT = '1' then + if rx_counter = c_max_word_number then + rx_counter <= (others => '0'); + else + rx_counter <= rx_counter + 1; + end if; + end if; + end if; + end if; + end process; + + +--TX Fifo & Data output to Serdes +--------------------- + FIFO_INT_TO_SFP: trb_net_fifo_16bit_bram_dualport + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( + read_clock_in => ff_txhalfclk, + write_clock_in => CLK, + read_enable_in => fifo_tx_rd_en, + write_enable_in => fifo_tx_wr_en, + fifo_gsr_in => fifo_tx_reset, + write_data_in => fifo_tx_din, + read_data_out => fifo_tx_dout, + full_out => fifo_tx_full, + empty_out => fifo_tx_empty + ); + fifo_tx_reset <= reset or not tx_allow; + fifo_tx_din <= MED_PACKET_NUM_IN(2) & MED_PACKET_NUM_IN(0) & MED_DATA_IN; + fifo_tx_wr_en <= MED_DATAREADY_IN and tx_allow; + fifo_tx_rd_en <= '1'; + + make_serdes_input : process(ff_txhalfclk) + begin + if rising_edge(ff_txhalfclk) then + last_fifo_tx_empty <= fifo_tx_empty; + if last_fifo_tx_empty = '1' then + tx_data <= x"c5bc"; + tx_k <= "01"; + else + tx_data <= fifo_tx_dout(15 downto 0); + tx_k <= "00"; + end if; + end if; + end process; + + +--link start-up state machine +---------------------- + + medium_states : process(ff_rxhalfclk) --correct clock? + begin + if rising_edge(ff_rxhalfclk) then + if RESET = '0' then + counter <= counter + 1; + swap_bytes <= '0'; + end if; + swap_bytes <= swap_bytes; + case state is + when start => + if counter(7 downto 0) = x"FF" then + counter <= (others => '0'); + state <= waitplolandrlol; + end if; + MED_ERROR_OUT <= ERROR_NC; + rx_allow <= '0'; + tx_allow <= '0'; + when waitplolandrlol => + counter <= (others => '0'); + if (link_error(5) = '0' and link_error(4) = '0') THEN + state <= waitrxallow; + end if; + MED_ERROR_OUT <= ERROR_NC; + when waitrxallow => --care for byte alignment! + if counter(28) = '1' then + counter <= (others => '0'); + rx_allow <= '1'; + state <= waittxallow; + end if; + MED_ERROR_OUT <= ERROR_WAIT; + when waittxallow => + if rx_k = "10" then + swap_bytes <= '1'; + elsif rx_k = "01" then + swap_bytes <= '0'; + end if; + if counter(28) = '1' then + tx_allow <= '1'; + state <= working; + end if; + MED_ERROR_OUT <= ERROR_WAIT; + when working => + MED_ERROR_OUT <= ERROR_OK; + end case; + if (link_error(6) = '1' or link_error(7) = '1') and ffc_lane_rx_rst_ch2 = '0' then + rx_allow <= '0'; + tx_allow <= '0'; + state <= waitrxallow; + MED_ERROR_OUT <= ERROR_WAIT; + end if; + end if; + end process; + + ffc_quad_rst <= '1' when state = start else RESET; + ffc_lane_tx_rst_ch2 <= '1' when state = start or state = waitplolandrlol else '0'; + ffc_lane_rx_rst_ch2 <= '1' when state = start or state = waitplolandrlol else '0'; + + + process(state) + begin + case state is + when start => state_bits <= "000"; + when waitplolandrlol => state_bits <= "001"; + when waitrxallow => state_bits <= "010"; + when waittxallow => state_bits <= "011"; + when working => state_bits <= "100"; + when others => state_bits <= "111"; + end case; + end process; + + STAT_DEBUG(2 downto 0) <= state_bits; + STAT_DEBUG(9 downto 3) <= (others => '0'); + STAT_DEBUG(19 downto 10) <= link_error; + STAT_DEBUG(20) <= link_ok(0); + STAT_DEBUG(38 downto 21) <= fifo_rx_din; + STAT_DEBUG(39) <= swap_bytes; + STAT_DEBUG(63 downto 40) <= (others => '0'); + +end architecture; \ No newline at end of file diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index 13c474d..19c5d3b 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -28,12 +28,12 @@ entity trb_net16_med_tlk is SFP_TX_DIS : out std_logic; MED_DATAREADY_IN : in std_logic; MED_READ_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (15 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_DATAREADY_OUT : out std_logic; MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (15 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_ERROR_OUT : out std_logic_vector (2 downto 0); STAT : out std_logic_vector (63 downto 0); STAT_MONITOR : out std_logic_vector ( 100 downto 0); @@ -80,12 +80,12 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal fifo_almost_empty_m, fifo_almost_empty_a : std_logic; signal fifo_valid_read_m, fifo_valid_read_a : std_logic; signal fifo_underflow_a, fifo_underflow_m : std_logic; - + signal fifo_reset : std_logic; signal fifo_status_a : std_logic_vector(3 downto 0); signal fifo_status_m : std_logic_vector(3 downto 0); signal last_fifo_rd_en_a, last_fifo_rd_en_m : std_logic; - signal buf_MED_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_MED_READ_OUT : std_logic; signal buf_MED_DATAREADY_OUT : std_logic; signal rx_allow : std_logic; @@ -113,7 +113,7 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal state_bits : std_logic_vector(2 downto 0); signal counter_reset : std_logic; - signal resync_counter : std_logic_vector(1 downto 0); + signal resync_counter : std_logic_vector(2 downto 0); signal buf_STAT_OP : std_logic_vector(15 downto 0); signal send_resync : std_logic; begin @@ -202,9 +202,9 @@ begin STAT(59) <= TLK_CLK_neg; STAT(60) <= fifo_wr_en_m; STAT(61) <= reset_packet_num; - STAT(63 downto 62) <= resync_counter; + STAT(63 downto 62) <= resync_counter(1 downto 0); --STAT(63 downto 57) <= (others => '0'); - + STAT_MONITOR(17 downto 0) <= fifo_din_a; @@ -221,9 +221,13 @@ begin begin if rising_edge(CLK) then if internal_reset = '1' or reset_packet_num = '1' then - buf_MED_PACKET_NUM_OUT <= "00"; + buf_MED_PACKET_NUM_OUT <= c_H0; elsif buf_MED_DATAREADY_OUT = '1' then - buf_MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT + 1; + if buf_MED_PACKET_NUM_OUT = c_max_word_number then + buf_MED_PACKET_NUM_OUT <= (others => '0'); + else + buf_MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT + 1; + end if; end if; end if; end process; @@ -239,10 +243,10 @@ begin if fifo_dout_a(7 downto 0) = x"7F" then resync_counter <= resync_counter + 1; else - resync_counter <= "00"; + resync_counter <= "000"; end if; end if; - if resync_counter = "11" then + if resync_counter = "100" then buf_STAT_OP(15) <= '1'; reset_packet_num <= '1'; end if; @@ -254,13 +258,13 @@ begin ------------- U_DCM_Transmitter: DCM - generic map( + generic map( CLKIN_PERIOD => 10.00, -- 30.30ns STARTUP_WAIT => FALSE, PHASE_SHIFT => 0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", CLKOUT_PHASE_SHIFT => "FIXED" - ) + ) port map ( CLKIN => TLK_CLK, CLKFB => FB_CLK, @@ -272,8 +276,8 @@ U_DCM_Transmitter: DCM CLK0 => CLK_FB_Out, -- for feedback CLK90=> CLK_Out, LOCKED => open - ); --- + ); +-- U0_BUFG: BUFG port map (I => CLK_FB_Out, O => TLK_CLK_neg); U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); @@ -327,7 +331,7 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); --Medium states ------------- - medium_states : process(current_state, tx_allow, rx_allow, internal_reset, + medium_states : process(current_state, tx_allow, rx_allow, internal_reset, reg_RX_ER, reg_RX_DV, buf_MED_ERROR_OUT, counter) begin next_state <= current_state; diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 6654c7f..97aad46 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -76,8 +76,8 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is ); end component; - signal current_output_data_buffer : STD_LOGIC_VECTOR (15 downto 0); - signal current_output_num_buffer : STD_LOGIC_VECTOR (1 downto 0); + signal current_output_data_buffer : STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + signal current_output_num_buffer : STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); signal current_ACK_word, current_EOB_word, current_DATA_word, current_NOP_word : STD_LOGIC_VECTOR (15 downto 0); signal comb_dataready, comb_next_read, comb_read ,sbuf_free: STD_LOGIC; @@ -97,7 +97,7 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal SEND_ACK_IN : STD_LOGIC; signal GOT_ACK_IN : STD_LOGIC; - signal transfer_counter : std_logic_vector(1 downto 0); + signal transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal saved_packet_type : std_logic_vector(2 downto 0); signal reg_SEND_ACK_IN_2,next_SEND_ACK_IN_2 : std_logic; @@ -112,7 +112,7 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal CRC : std_logic_vector(15 downto 0); begin -- gen_sbuf : if SECURE_MODE = 1 generate - SBUF: trb_net16_sbuf + SBUF:trb_net16_sbuf generic map ( VERSION => SBUF_VERSION ) @@ -190,14 +190,16 @@ begin current_ACK_word <= (others => '0'); current_EOB_word <= (others => '0'); current_DATA_word <= INT_DATA_IN; - if transfer_counter = "10" then + if transfer_counter = c_F1 then current_ACK_word(3 downto 0) <= SEND_BUFFER_SIZE_IN; + end if; + if transfer_counter = c_F2 then current_EOB_word(DATA_COUNT_WIDTH-1 downto 0) <= CURRENT_DATA_COUNT; end if; - if transfer_counter = "11" then + if transfer_counter = c_F3 then current_EOB_word <= CRC; end if; - if transfer_counter = "00" then + if transfer_counter = c_H0 then current_NOP_word(2 downto 0) <= TYPE_ILLEGAL; current_ACK_word(2 downto 0) <= TYPE_ACK; current_EOB_word(2 downto 0) <= TYPE_EOB; @@ -208,9 +210,13 @@ begin begin if rising_edge(CLK) then if RESET = '1' then - transfer_counter <= (others => '0'); + transfer_counter <= c_max_word_number; elsif comb_dataready = '1' then - transfer_counter <= transfer_counter + 1; + if transfer_counter = c_max_word_number then + transfer_counter <= (others => '0'); + else + transfer_counter <= transfer_counter + 1; + end if; end if; end if; end process; @@ -220,7 +226,7 @@ begin if rising_edge(CLK) then if RESET = '1' then saved_packet_type <= TYPE_ILLEGAL; - elsif transfer_counter = "00" and comb_dataready = '1' then + elsif transfer_counter = c_H0 and comb_dataready = '1' then saved_packet_type <= current_output_data_buffer(2 downto 0); end if; end if; @@ -272,10 +278,10 @@ begin --can only happen if idle or sending_data current_output_data_buffer <= current_DATA_word; comb_dataready <= '1'; - if transfer_counter = "10" then + if transfer_counter = c_F3_next then increase_DATA_COUNT <= '1'; --transfer_counter(1) and not transfer_counter(0); end if; - if transfer_counter = "11" then + if transfer_counter = c_F3 then if saved_packet_type = TYPE_TRM then -- or saved_packet_type = TYPE_EOB reset_DATA_COUNT <= '1'; CRC_RESET <= '1'; @@ -299,7 +305,7 @@ begin current_output_data_buffer <= current_EOB_word; if sbuf_free = '1' then comb_dataready <= '1'; - if (transfer_counter = "11") then + if (transfer_counter = c_F3) then next_sending_state <= idle; CRC_RESET <= '1'; reset_DATA_COUNT <= '1'; @@ -313,18 +319,18 @@ begin current_output_data_buffer <= current_ACK_word; if sbuf_free = '1' then comb_dataready <= '1'; - if (transfer_counter = "11") then + if (transfer_counter = c_F3) then next_SEND_ACK_IN <= '0'; next_sending_state <= idle; end if; end if; end if; - if send_EOB = '1' and transfer_counter = "00" and (reg_INT_READ_OUT and INT_DATAREADY_IN) = '0' then + if send_EOB = '1' and transfer_counter = c_H0 and (reg_INT_READ_OUT and INT_DATAREADY_IN) = '0' then next_sending_state <= sending_eob; next_INT_READ_OUT <= '0'; end if; - if send_ACK = '1' and transfer_counter = "00" and (reg_INT_READ_OUT and INT_DATAREADY_IN) = '0' then + if send_ACK = '1' and transfer_counter = c_H0 and (reg_INT_READ_OUT and INT_DATAREADY_IN) = '0' then next_sending_state <= sending_ack; next_INT_READ_OUT <= '0'; end if; diff --git a/trb_net16_obuf_nodata.vhd b/trb_net16_obuf_nodata.vhd index 498e49a..365d553 100644 --- a/trb_net16_obuf_nodata.vhd +++ b/trb_net16_obuf_nodata.vhd @@ -28,13 +28,13 @@ architecture trb_net16_obuf_nodata_arch of trb_net16_obuf_nodata is signal SEND_BUFFER_SIZE_IN : std_logic_vector(3 downto 0); signal SEND_ACK_IN : std_logic; - signal current_NOP_word : std_logic_vector(15 downto 0); - signal current_ACK_word : std_logic_vector(15 downto 0); - signal transfer_counter : std_logic_vector(1 downto 0); + signal current_NOP_word : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal current_ACK_word : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_MED_DATAREADY_OUT, next_MED_DATAREADY_OUT : std_logic; - signal buf_MED_DATA_OUT, next_MED_DATA_OUT : std_logic_vector(15 downto 0); - signal buf_MED_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + signal buf_MED_DATA_OUT, next_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal sending_ACK, next_sending_ACK : std_logic; signal send_ACK : std_logic; signal reg_SEND_ACK_IN_2, next_SEND_ACK_IN_2 : std_logic; @@ -61,7 +61,7 @@ begin if reg_SEND_ACK_IN = '1' then next_MED_DATA_OUT <= current_ACK_word; next_MED_DATAREADY_OUT <= '1'; - if transfer_counter <= "11" and MED_READ_IN = '1' then + if transfer_counter <= c_F3 and MED_READ_IN = '1' then next_SEND_ACK_IN <= '0'; end if; end if; @@ -87,9 +87,9 @@ begin current_NOP_word <= (others => '0'); current_NOP_word(2 downto 0) <= TYPE_ILLEGAL; current_ACK_word <= (others => '0'); - if transfer_counter = "10" then + if transfer_counter = c_F1 then current_ACK_word(3 downto 0) <= SEND_BUFFER_SIZE_IN; - elsif transfer_counter = "00" then + elsif transfer_counter = c_H0 then current_ACK_word(2 downto 0) <= TYPE_ACK; end if; end process; @@ -100,7 +100,11 @@ begin if RESET = '1' then transfer_counter <= (others => '0'); elsif buf_MED_DATAREADY_OUT = '1' and MED_READ_IN = '1' then - transfer_counter <= transfer_counter + 1; + if transfer_counter = c_max_word_number then + transfer_counter <= (others => '0'); + else + transfer_counter <= transfer_counter + 1; + end if; end if; end if; end process; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index f80ad1c..8f369c9 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -11,8 +11,6 @@ use work.trb_net_std.all; entity trb_net16_regIO is generic ( - REGISTER_WIDTH : integer range 32 to 32 := 32; - ADDRESS_WIDTH : integer range 8 to 16 := 16; NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers --standard values for output registers @@ -64,19 +62,19 @@ entity trb_net16_regIO is MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); --Common Register in / out - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0); - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); --Custom Register in / out - REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); - REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + REGISTERS_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); + REGISTERS_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); --Internal Data Port - DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); + DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); DAT_READ_ENABLE_OUT : out std_logic; DAT_WRITE_ENABLE_OUT: out std_logic; - DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0); + DAT_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); --Data input can only be used as reaction on read or write access. write operation should return data --if successful - DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0); + DAT_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); DAT_DATAREADY_IN : in std_logic; DAT_NO_MORE_DATA_IN : in std_logic; --finish transmission, when reading from a fifo and it got empty @@ -110,19 +108,19 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - API_DATA_IN : in std_logic_vector(15 downto 0); + API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); API_DATAREADY_IN : in std_logic; API_READ_OUT : out std_logic; RAM_DATA_IN : in std_logic_vector(15 downto 0); RAM_DATA_OUT : out std_logic_vector(15 downto 0); RAM_ADDR_IN : in std_logic_vector(2 downto 0); RAM_WR_IN : in std_logic; - API_DATA_OUT : out std_logic_vector(15 downto 0); - API_PACKET_NUM_OUT: out std_logic_vector(1 downto 0); + API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); API_DATAREADY_OUT : out std_logic; API_READ_IN : in std_logic; - API_SEND_OUT : out std_logic; ADDRESS_REJECTED : out std_logic; + API_SEND_OUT : out std_logic; ADDRESS_OUT : out std_logic_vector(15 downto 0) ); end component; @@ -148,8 +146,8 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE, ONE_READ, ONE_WRITE, SEND_REPLY_SHORT_TRANSFER, MEM_START_WRITE, MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV,MEM_START_READ); signal current_state, next_state : fsm_state_t; - signal HDR_F1, HDR_F2, HDR_F3 : std_logic_vector(15 downto 0); - signal next_HDR_F1, next_HDR_F2, next_HDR_F3 : std_logic_vector(15 downto 0); + signal HDR_F1, HDR_F2, HDR_F3, HDR_F0 : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal next_HDR_F1, next_HDR_F2, next_HDR_F3, next_HDR_F0 : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal next_Reg_high, saved_Reg_high : std_logic_vector(15 downto 0); signal next_Reg_low, saved_Reg_low : std_logic_vector(15 downto 0); signal next_address, address : std_logic_vector(15 downto 0) := x"0000"; @@ -157,35 +155,35 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is signal buf_API_READ_OUT : std_logic; signal buf_API_SEND_OUT, next_API_SEND_OUT : std_logic; - signal buf_API_PACKET_NUM_OUT, next_API_PACKET_NUM_OUT : std_logic_vector(1 downto 0); - signal buf_API_DATA_OUT, next_API_DATA_OUT : std_logic_vector(15 downto 0); + signal buf_API_PACKET_NUM_OUT, next_API_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal buf_API_DATA_OUT, next_API_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal buf_API_SHORT_TRANSFER_OUT, next_API_SHORT_TRANSFER_OUT : std_logic; signal buf_API_DATAREADY_OUT, next_API_DATAREADY_OUT : std_logic; - signal buf_DAT_DATA_OUT : std_logic_vector(REGISTER_WIDTH-1 downto 0); - signal buf_DAT_DATA_IN : std_logic_vector(REGISTER_WIDTH-1 downto 0); + signal buf_DAT_DATA_OUT : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + signal buf_DAT_DATA_IN : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); signal buf_DAT_READ_ENABLE_OUT, next_DAT_READ_ENABLE_OUT : std_logic; signal buf_DAT_WRITE_ENABLE_OUT, next_DAT_WRITE_ENABLE_OUT : std_logic; - signal buf_DAT_ADDR_OUT : std_logic_vector(ADDRESS_WIDTH-1 downto 0); + signal buf_DAT_ADDR_OUT : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); - signal buf_REGISTERS_OUT : std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + signal buf_REGISTERS_OUT : std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); signal REGISTERS_OUT_write_enable : std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0); signal next_REGISTERS_OUT_write_enable : std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0); signal reg_enable_pattern : std_logic_vector(63 downto 0); signal next_COMMON_REGISTERS_OUT_write_enable: std_logic_vector(std_COMCTRLREG - 1 downto 0); signal COMMON_REGISTERS_OUT_write_enable : std_logic_vector(std_COMCTRLREG - 1 downto 0); - signal buf_COMMON_CTRL_REG_OUT : std_logic_vector(REGISTER_WIDTH*std_COMCTRLREG-1 downto 0); + signal buf_COMMON_CTRL_REG_OUT : std_logic_vector(c_REGIO_REGISTER_WIDTH*std_COMCTRLREG-1 downto 0); signal state_bits : std_logic_vector(3 downto 0); signal ADR_SEND_OUT : std_logic; signal ADR_DATAREADY_IN : std_logic; signal ADR_READ_OUT : std_logic; - signal ADR_DATA_OUT : std_logic_vector(15 downto 0); + signal ADR_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal ADR_READ_IN : std_logic; signal ADR_DATAREADY_OUT : std_logic; - signal ADR_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + signal ADR_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal ADR_REJECTED : std_logic; signal buf_API_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); signal rom_read_addr,buf_rom_read_addr : std_logic_vector(2 downto 0); @@ -283,15 +281,18 @@ begin when HEADER_RECV => --read and save HDR if API_DATAREADY_IN = '1' then - if API_PACKET_NUM_IN = "01" then + if API_PACKET_NUM_IN = c_F0 then + next_HDR_F0 <= API_DATA_IN; + end if; + if API_PACKET_NUM_IN = c_F1 then next_HDR_F1 <= API_DATA_IN; end if; - if API_PACKET_NUM_IN = "10" then + if API_PACKET_NUM_IN = c_F2 then next_HDR_F2 <= API_DATA_IN; end if; - if API_PACKET_NUM_IN = "11" then + if API_PACKET_NUM_IN = c_F3 then next_HDR_F3 <= API_DATA_IN; - next_API_PACKET_NUM_OUT <= "11"; + next_API_PACKET_NUM_OUT <= "011"; case API_DATA_IN(3 downto 0) is when c_read_register_type => next_state <= ONE_READ; when c_write_register_type => next_state <= ONE_WRITE; @@ -329,10 +330,10 @@ begin when ONE_READ => --wait for register address - if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = "01" and API_DATAREADY_IN = '1' then + if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = c_F0 and API_DATAREADY_IN = '1' then next_address <= API_DATA_IN; rom_read_addr <= API_DATA_IN(1 downto 0) & '1'; - if or_all(API_DATA_IN(ADDRESS_WIDTH-1 downto 8)) = '1' then --data port address + if or_all(API_DATA_IN(c_REGIO_ADDRESS_WIDTH-1 downto 8)) = '1' then --data port address if USE_DAT_PORT = c_YES then next_DAT_READ_ENABLE_OUT <= '1'; next_state <= DAT_READ; @@ -346,9 +347,9 @@ begin end if; when ONE_WRITE => --wait for register address - if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = "01" and API_DATAREADY_IN = '1' then + if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = c_F0 and API_DATAREADY_IN = '1' then next_address <= API_DATA_IN; - if or_all(API_DATA_IN(ADDRESS_WIDTH-1 downto 8)) = '1' then --data port address + if or_all(API_DATA_IN(c_REGIO_ADDRESS_WIDTH-1 downto 8)) = '1' then --data port address if USE_DAT_PORT = c_YES then next_state <= REG_WRITE; else @@ -374,9 +375,9 @@ begin when REG_WRITE => case API_PACKET_NUM_IN is - when "10" => + when c_F1 => next_Reg_high <= API_DATA_IN; - when "11" => + when c_F2 => next_Reg_low <= API_DATA_IN; if or_all(address(15 downto 8)) = '0' then if address(7 downto 6) = "11" then @@ -398,36 +399,39 @@ begin next_API_DATAREADY_OUT <= '0'; else next_API_DATAREADY_OUT <= '1'; - if buf_API_PACKET_NUM_OUT = "11" then - next_API_PACKET_NUM_OUT <= "01"; + if buf_API_PACKET_NUM_OUT = c_F3 then + next_API_PACKET_NUM_OUT <= c_F0; next_API_DATA_OUT <= address; - elsif buf_API_PACKET_NUM_OUT = "01" then - next_API_PACKET_NUM_OUT <= "10"; + elsif buf_API_PACKET_NUM_OUT = c_F0 then + next_API_PACKET_NUM_OUT <= c_F1; if address(7 downto 6) = "01" then next_API_DATA_OUT <= rom_read_dout; rom_read_addr <= address(1 downto 0) & '0'; elsif address(7 downto 6) = "10" then - next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*REGISTER_WIDTH+31 downto regnum_STAT*REGISTER_WIDTH+16); + next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REGISTER_WIDTH+31 downto regnum_STAT*c_REGIO_REGISTER_WIDTH+16); elsif address(7 downto 6) = "11" then - next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*REGISTER_WIDTH+31 downto regnum_CTRL*REGISTER_WIDTH+16); + next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REGISTER_WIDTH+31 downto regnum_CTRL*c_REGIO_REGISTER_WIDTH+16); elsif address(5) = '0' then - next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*REGISTER_WIDTH+31 downto regnum_cSTAT*REGISTER_WIDTH+16); + next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REGISTER_WIDTH+31 downto regnum_cSTAT*c_REGIO_REGISTER_WIDTH+16); else --if address(5) = '1' then - next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*REGISTER_WIDTH+31 downto regnum_cCTRL*REGISTER_WIDTH+16); + next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REGISTER_WIDTH+31 downto regnum_cCTRL*c_REGIO_REGISTER_WIDTH+16); end if; - elsif buf_API_PACKET_NUM_OUT = "10" then - next_API_PACKET_NUM_OUT <= "11"; + elsif buf_API_PACKET_NUM_OUT = c_F1 then + next_API_PACKET_NUM_OUT <= c_F2; if address(7 downto 6) = "01" then next_API_DATA_OUT <= rom_read_dout; elsif address(7 downto 6) = "10" then - next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*REGISTER_WIDTH+15 downto regnum_STAT*REGISTER_WIDTH); + next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REGISTER_WIDTH+15 downto regnum_STAT*c_REGIO_REGISTER_WIDTH); elsif address(7 downto 6) = "11" then - next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*REGISTER_WIDTH+15 downto regnum_CTRL*REGISTER_WIDTH); + next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REGISTER_WIDTH+15 downto regnum_CTRL*c_REGIO_REGISTER_WIDTH); elsif address(5) = '0' then - next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*REGISTER_WIDTH+15 downto regnum_cSTAT*REGISTER_WIDTH); + next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REGISTER_WIDTH+15 downto regnum_cSTAT*c_REGIO_REGISTER_WIDTH); else --if address(5) = '1' then - next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*REGISTER_WIDTH+15 downto regnum_cCTRL*REGISTER_WIDTH); + next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REGISTER_WIDTH+15 downto regnum_cCTRL*c_REGIO_REGISTER_WIDTH); end if; + elsif buf_API_PACKET_NUM_OUT = c_F2 then + next_API_PACKET_NUM_OUT <= c_F3; + next_API_DATA_OUT <= (others => '0'); next_state <= SEND_REPLY_DATA_finish; end if; end if; @@ -436,10 +440,10 @@ begin next_state <= SEND_REPLY_SHORT_TRANSFER; next_dont_understand <= '1'; else - if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = "10" and API_DATAREADY_IN = '1' then + if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = c_F1 and API_DATAREADY_IN = '1' then next_length <= API_DATA_IN; next_state <= MEM_READ; - elsif API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = "01" and API_DATAREADY_IN = '1' then + elsif API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = c_F0 and API_DATAREADY_IN = '1' then next_address <= API_DATA_IN; if API_DATA_IN(15 downto 8) = 0 then next_state <= SEND_REPLY_SHORT_TRANSFER; @@ -447,37 +451,36 @@ begin end if; end if; end if; - when MEM_READ => - if buf_API_PACKET_NUM_OUT = "11" and API_READ_IN = '1' then - if length = 0 then - next_state <= SEND_REPLY_DATA_finish; - else - next_DAT_READ_ENABLE_OUT <= '1'; - next_API_SEND_OUT <= '1'; - next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1; - end if; - elsif buf_API_PACKET_NUM_OUT = "00" then - if DAT_DATAREADY_IN = '1' then - next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1; - next_API_DATA_OUT <= address; - next_API_DATAREADY_OUT <= '1'; - elsif DAT_NO_MORE_DATA_IN = '1' then - next_state <= SEND_REPLY_DATA_finish; - end if; - elsif buf_API_PACKET_NUM_OUT = "01" and API_READ_IN = '1' then - next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1; - next_API_DATA_OUT <= buf_DAT_DATA_IN(31 downto 16); - next_API_DATAREADY_OUT <= '1'; - elsif buf_API_PACKET_NUM_OUT = "10" and API_READ_IN = '1' then - next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1; - next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0); - next_API_DATAREADY_OUT <= '1'; - next_length <= length-1; - end if; + when MEM_READ => --needs a review + next_state <= SEND_REPLY_DATA_finish; +-- if buf_API_PACKET_NUM_OUT = c_F3 and API_READ_IN = '1' then +-- if length = 0 or DAT_NO_MORE_DATA_IN = '1' then +-- next_state <= SEND_REPLY_DATA_finish; +-- else +-- next_DAT_READ_ENABLE_OUT <= '1'; +-- next_API_SEND_OUT <= '1'; +-- next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1; +-- end if; +-- elsif buf_API_PACKET_NUM_OUT = c_F0_next then +-- if DAT_DATAREADY_IN = '1' then +-- next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1; +-- next_API_DATA_OUT <= address; +-- next_API_DATAREADY_OUT <= '1'; +-- end if; +-- elsif buf_API_PACKET_NUM_OUT = c_F1_next and API_READ_IN = '1' then +-- next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1; +-- next_API_DATA_OUT <= buf_DAT_DATA_IN(31 downto 16); +-- next_API_DATAREADY_OUT <= '1'; +-- elsif buf_API_PACKET_NUM_OUT = c_F2_next and API_READ_IN = '1' then +-- next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1; +-- next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0); +-- next_API_DATAREADY_OUT <= '1'; +-- next_length <= length-1; +-- end if; when MEM_START_WRITE => - if API_PACKET_NUM_IN = "01" and API_TYP_IN = TYPE_DAT and API_DATAREADY_IN = '1' then + if API_PACKET_NUM_IN = c_F0 and API_TYP_IN = TYPE_DAT and API_DATAREADY_IN = '1' then next_address <= API_DATA_IN; next_state <= MEM_WRITE; end if; @@ -488,8 +491,8 @@ begin next_dont_understand <= '1'; elsif API_DATAREADY_IN = '1' then case API_PACKET_NUM_IN is - when "10" => next_Reg_high <= API_DATA_IN; - when "11" => + when c_F1 => next_Reg_high <= API_DATA_IN; + when c_F2 => next_Reg_low <= API_DATA_IN; next_DAT_WRITE_ENABLE_OUT <= '1'; when others => null; @@ -505,17 +508,17 @@ begin when DAT_READ => if DAT_DATAREADY_IN = '1' and API_READ_IN = '1' then - next_API_PACKET_NUM_OUT <= "01"; + next_API_PACKET_NUM_OUT <= c_F0; next_API_DATA_OUT <= address; next_API_SEND_OUT <= '1'; next_API_DATAREADY_OUT <= '1'; end if; - if buf_API_PACKET_NUM_OUT = "01" and API_READ_IN = '1' then - next_API_PACKET_NUM_OUT <= "10"; + if buf_API_PACKET_NUM_OUT = c_F0 and API_READ_IN = '1' then + next_API_PACKET_NUM_OUT <= c_F1; next_API_DATA_OUT <= buf_DAT_DATA_IN(31 downto 16); next_API_DATAREADY_OUT <= '1'; - elsif buf_API_PACKET_NUM_OUT = "10" and API_READ_IN = '1' then - next_API_PACKET_NUM_OUT <= "11"; + elsif buf_API_PACKET_NUM_OUT = c_F1 and API_READ_IN = '1' then + next_API_PACKET_NUM_OUT <= c_F0; next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0); next_API_DATAREADY_OUT <= '1'; next_state <= SEND_REPLY_DATA_finish; @@ -534,7 +537,7 @@ begin current_state <= IDLE; buf_API_SEND_OUT <= '0'; buf_API_DATAREADY_OUT <= '0'; - buf_API_PACKET_NUM_OUT <= "11"; + buf_API_PACKET_NUM_OUT <= "011"; buf_DAT_READ_ENABLE_OUT <= '0'; buf_DAT_WRITE_ENABLE_OUT <= '0'; buf_API_DATA_OUT <= (others => '0'); @@ -547,6 +550,7 @@ begin dont_understand <= '0'; else current_state <= next_state; + HDR_F0 <= next_HDR_F0; HDR_F1 <= next_HDR_F1; HDR_F2 <= next_HDR_F2; HDR_F3 <= next_HDR_F3; @@ -571,19 +575,19 @@ begin end process; gen_regout : for i in 0 to 2**(NUM_CTRL_REGS)-1 generate - gen_regoutff1 : for j in i*REGISTER_WIDTH to (i+1)*REGISTER_WIDTH-1 generate + gen_regoutff1 : for j in i*c_REGIO_REGISTER_WIDTH to (i+1)*c_REGIO_REGISTER_WIDTH-1 generate gen_regoutff : if USED_CTRL_REGS(i) = '1' and USED_CTRL_BITMASK(j) = '1' generate process(CLK) - variable tmp : std_logic_vector(REGISTER_WIDTH-1 downto 0); + variable tmp : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); begin if rising_edge(CLK) then if RESET = '1' then buf_REGISTERS_OUT(j) <= INIT_CTRL_REGS(j); elsif REGISTERS_OUT_write_enable(i) = '1' then tmp := saved_Reg_high & saved_Reg_low; - buf_REGISTERS_OUT(j) <= tmp(j-i*REGISTER_WIDTH); + buf_REGISTERS_OUT(j) <= tmp(j-i*c_REGIO_REGISTER_WIDTH); elsif EXT_REG_WRITE_IN = '1' and EXT_REG_ADDR_IN = (conv_std_logic_vector(i,8) or x"D0") then - buf_REGISTERS_OUT(j) <= EXT_REG_DATA_IN(j-i*REGISTER_WIDTH); + buf_REGISTERS_OUT(j) <= EXT_REG_DATA_IN(j-i*c_REGIO_REGISTER_WIDTH); end if; end if; end process; @@ -595,18 +599,18 @@ begin end generate; gen_cregout : for i in 0 to std_COMCTRLREG-1 generate - gen_cregoutff1 : for j in i*REGISTER_WIDTH to (i+1)*REGISTER_WIDTH-1 generate + gen_cregoutff1 : for j in i*c_REGIO_REGISTER_WIDTH to (i+1)*c_REGIO_REGISTER_WIDTH-1 generate process(CLK) - variable tmp : std_logic_vector(REGISTER_WIDTH-1 downto 0); + variable tmp : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); begin if rising_edge(CLK) then if RESET = '1' then buf_COMMON_CTRL_REG_OUT(j) <= '0'; elsif COMMON_REGISTERS_OUT_write_enable(i) = '1' then tmp := saved_Reg_high & saved_Reg_low; - buf_COMMON_CTRL_REG_OUT(j) <= tmp(j-i*REGISTER_WIDTH); + buf_COMMON_CTRL_REG_OUT(j) <= tmp(j-i*c_REGIO_REGISTER_WIDTH); elsif EXT_REG_WRITE_IN = '1' and EXT_REG_ADDR_IN = (conv_std_logic_vector(i,8) or x"20") then - buf_COMMON_CTRL_REG_OUT(j) <= EXT_REG_DATA_IN(j-i*REGISTER_WIDTH); + buf_COMMON_CTRL_REG_OUT(j) <= EXT_REG_DATA_IN(j-i*c_REGIO_REGISTER_WIDTH); end if; end if; end process; @@ -630,13 +634,13 @@ begin elsif EXT_REG_ADDR_IN(7 downto 6) = "01" then EXT_REG_DATA_OUT <= (others => '0'); elsif EXT_REG_ADDR_IN(7 downto 6) = "10" then - EXT_REG_DATA_OUT <= REGISTERS_IN(regnum_STAT*REGISTER_WIDTH+31 downto regnum_STAT*REGISTER_WIDTH); + EXT_REG_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REGISTER_WIDTH+31 downto regnum_STAT*c_REGIO_REGISTER_WIDTH); elsif EXT_REG_ADDR_IN(7 downto 6) = "11" then - EXT_REG_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*REGISTER_WIDTH+31 downto regnum_CTRL*REGISTER_WIDTH); + EXT_REG_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REGISTER_WIDTH+31 downto regnum_CTRL*c_REGIO_REGISTER_WIDTH); elsif EXT_REG_ADDR_IN(5) = '0' then - EXT_REG_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*REGISTER_WIDTH+31 downto regnum_cSTAT*REGISTER_WIDTH); + EXT_REG_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REGISTER_WIDTH+31 downto regnum_cSTAT*c_REGIO_REGISTER_WIDTH); else --if EXT_CTRL_ADDR_IN(5) = '1' then - EXT_REG_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*REGISTER_WIDTH+31 downto regnum_cCTRL*REGISTER_WIDTH); + EXT_REG_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REGISTER_WIDTH+31 downto regnum_cCTRL*c_REGIO_REGISTER_WIDTH); end if; end if; end process; @@ -690,10 +694,10 @@ begin COMMON_CTRL_REG_OUT <= buf_COMMON_CTRL_REG_OUT; STAT(3 downto 0) <= state_bits; - STAT(5 downto 4) <= next_API_PACKET_NUM_OUT; - STAT(6) <= next_API_DATAREADY_OUT; - STAT(14 downto 7) <= next_API_DATA_OUT(7 downto 0); - STAT(31 downto 15) <= (others => '0'); + STAT(6 downto 4) <= next_API_PACKET_NUM_OUT; + STAT(7) <= next_API_DATAREADY_OUT; + STAT(15 downto 8) <= next_API_DATA_OUT(7 downto 0); + STAT(31 downto 16) <= (others => '0'); process(current_state) begin diff --git a/trb_net16_term.vhd b/trb_net16_term.vhd index 8d8b108..856d87b 100644 --- a/trb_net16_term.vhd +++ b/trb_net16_term.vhd @@ -27,23 +27,23 @@ entity trb_net16_term is RESET : in std_logic; CLK_EN : in std_logic; - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr + INT_DATAREADY_OUT : out std_logic; + INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN : in std_logic; + + INT_DATAREADY_IN : in std_logic; + INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out std_logic; + + -- "mini" APL, just to see terminations coming in + APL_DTYPE_OUT : out std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + APL_GOT_TRM : out std_logic; + APL_RELEASE_TRM : in std_logic; + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) ); end entity; @@ -53,16 +53,16 @@ architecture trb_net16_term_arch of trb_net16_term is signal reg_APL_ERROR_PATTERN_OUT: std_logic_vector(31 downto 0); signal next_APL_SEQNR_OUT, reg_APL_SEQNR_OUT: std_logic_vector(7 downto 0); signal next_APL_GOT_TRM, reg_APL_GOT_TRM: std_logic; - signal reg_APL_DTYPE_IN, buf_APL_DTYPE_IN : std_logic_vector(3 downto 0); + signal reg_APL_DTYPE_IN : std_logic_vector(3 downto 0); signal reg_APL_ERROR_PATTERN_IN, buf_APL_ERROR_PATTERN_IN: std_logic_vector(31 downto 0); signal saved_packet_type : std_logic_vector(2 downto 0); - signal transfer_counter : std_logic_vector(1 downto 0); + signal transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal send_trm, next_send_trm : std_logic; signal buf_INT_DATAREADY_OUT, next_INT_DATAREADY_OUT : std_logic; - signal buf_INT_DATA_OUT, next_INT_DATA_OUT : std_logic_vector(15 downto 0); + signal buf_INT_DATA_OUT, next_INT_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); begin @@ -79,20 +79,20 @@ begin APL_SEQNR_OUT <= (others => '0'); APL_GOT_TRM <= '0'; INT_READ_OUT <= '1'; --not send_trm; - end generate; + end generate; process(RESET, reg_APL_DTYPE_OUT, reg_APL_SEQNR_OUT, reg_APL_GOT_TRM, INT_PACKET_NUM_IN, INT_DATA_IN, APL_RELEASE_TRM, send_trm, transfer_counter, INT_READ_IN, saved_packet_type, buf_APL_ERROR_PATTERN_IN, - buf_APL_DTYPE_IN, buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT) + buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT) begin if USE_APL_PORT = 1 then next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; next_APL_GOT_TRM <= reg_APL_GOT_TRM; if saved_packet_type = TYPE_TRM then - if INT_PACKET_NUM_IN = "11" then + if INT_PACKET_NUM_IN = c_F3 then next_APL_DTYPE_OUT <= INT_DATA_IN(3 downto 0); next_APL_SEQNR_OUT <= INT_DATA_IN(11 downto 4); next_APL_GOT_TRM <= '1'; @@ -106,7 +106,7 @@ begin if (reg_APL_GOT_TRM = '1' and (APL_RELEASE_TRM = '1' or USE_APL_PORT = 0)) or send_trm = '1' then -- if (reg_APL_GOT_TRM = '1' and (APL_RELEASE_TRM = '1' )) or send_trm = '1' or 0 = 0 then --next_transfer_counter is used for transmission! - if transfer_counter = "10" and INT_READ_IN = '1' then + if transfer_counter = c_F3_next and INT_READ_IN = '1' then next_send_trm <= '0'; else next_send_trm <= '1'; @@ -114,12 +114,14 @@ begin next_INT_DATAREADY_OUT <= '1'; end if; if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then - if transfer_counter = "11" then + if transfer_counter = c_F3_next then next_INT_DATA_OUT <= (others => '0'); next_INT_DATA_OUT(2 downto 0) <= TYPE_TRM; - elsif transfer_counter = "00" then + elsif transfer_counter = c_F0_next then + next_INT_DATA_OUT <= (others => '0'); + elsif transfer_counter = c_F1_next then next_INT_DATA_OUT <= buf_APL_ERROR_PATTERN_IN(31 downto 16); - elsif transfer_counter = "01" then + elsif transfer_counter = c_F2_next then next_INT_DATA_OUT <= buf_APL_ERROR_PATTERN_IN(15 downto 0); else next_INT_DATA_OUT <= (others => '0'); @@ -148,7 +150,7 @@ begin SECURE_GEN2: if SECURE_MODE = 0 generate buf_APL_ERROR_PATTERN_IN <= APL_ERROR_PATTERN_IN; end generate; - + --count packets REG_TRANSFER_COUNTER : process(CLK) @@ -156,8 +158,12 @@ begin if rising_edge(CLK) then if RESET = '1' then transfer_counter <= (others => '0'); - elsif buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then - transfer_counter <= transfer_counter + 1; + elsif CLK_EN = '1' and buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then + if transfer_counter = c_max_word_number then + transfer_counter <= (others => '0'); + else + transfer_counter <= transfer_counter + 1; + end if; end if; end if; end process; @@ -182,9 +188,9 @@ begin process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or (INT_PACKET_NUM_IN = "11" and INT_DATAREADY_IN = '1') then --or + if RESET = '1' or (INT_PACKET_NUM_IN = c_F3 and INT_DATAREADY_IN = '1') then --or saved_packet_type <= "111"; - elsif INT_PACKET_NUM_IN = "00" then + elsif INT_PACKET_NUM_IN = c_H0 then saved_packet_type <= INT_DATA_IN(2 downto 0); end if; end if; @@ -203,8 +209,8 @@ begin reg_APL_SEQNR_OUT <= next_APL_SEQNR_OUT; end if; end if; - end process; - + end process; + g2: if USE_APL_PORT = 1 generate CLK_REG: process(CLK) begin @@ -222,7 +228,7 @@ begin if rising_edge(CLK) then if RESET = '1' then reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= (others => '0'); - elsif INT_PACKET_NUM_IN = "01" then + elsif INT_PACKET_NUM_IN = c_F1 then reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= INT_DATA_IN; end if; end if; @@ -232,7 +238,7 @@ begin if rising_edge(CLK) then if RESET = '1' then reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= (others => '0'); - elsif INT_PACKET_NUM_IN = "10" then + elsif INT_PACKET_NUM_IN = c_F3 then reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= INT_DATA_IN; end if; end if; diff --git a/trb_net16_term_buf.vhd b/trb_net16_term_buf.vhd index 6a63747..25c3a52 100644 --- a/trb_net16_term_buf.vhd +++ b/trb_net16_term_buf.vhd @@ -16,20 +16,20 @@ entity trb_net16_term_buf is RESET : in std_logic; CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; - - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; - - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic ); end entity; @@ -37,36 +37,26 @@ architecture trb_net16_term_buf_arch of trb_net16_term_buf is signal INIT_SEQNR, next_INIT_SEQNR : std_logic_vector(7 downto 0); signal saved_packet_type : std_logic_vector(3 downto 0); - signal INIT_transfer_counter : std_logic_vector(1 downto 0); + signal INIT_transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_MED_INIT_DATAREADY_OUT, next_MED_INIT_DATAREADY_OUT : std_logic; - signal buf_MED_INIT_DATA_OUT, next_MED_INIT_DATA_OUT : std_logic_vector(15 downto 0); - signal buf_MED_INIT_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + signal buf_MED_INIT_DATA_OUT, next_MED_INIT_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal send_INIT_ack : std_logic; signal next_send_INIT_ack : std_logic; - signal sent_INIT_ack : std_logic; - signal REPLY_saved_packet_type : std_logic_vector(2 downto 0); - signal REPLY_transfer_counter : std_logic_vector(1 downto 0); + signal REPLY_transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_MED_REPLY_DATAREADY_OUT, next_MED_REPLY_DATAREADY_OUT : std_logic; - signal buf_MED_REPLY_DATA_OUT, next_MED_REPLY_DATA_OUT : std_logic_vector(15 downto 0); - signal buf_MED_REPLY_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + signal buf_MED_REPLY_DATA_OUT, next_MED_REPLY_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal send_REPLY_trm : std_logic; signal next_send_REPLY_trm : std_logic; - signal sent_REPLY_trm : std_logic; - signal init_channel : std_logic; - signal sending_REPLY_ACK, next_sending_REPLY_ACK : std_logic; begin MED_READ_OUT <= '1'; - process(MED_DATAREADY_IN, MED_PACKET_NUM_IN, MED_DATA_IN, - send_INIT_ack, send_REPLY_trm, - REPLY_transfer_counter, REPLY_saved_packet_type, MED_INIT_READ_IN, + process(MED_DATAREADY_IN, MED_PACKET_NUM_IN, MED_DATA_IN, REPLY_transfer_counter, + send_INIT_ack, send_REPLY_trm, MED_INIT_READ_IN, INIT_SEQNR, INIT_transfer_counter, saved_packet_type, MED_REPLY_READ_IN, buf_MED_INIT_DATA_OUT, buf_MED_REPLY_DATA_OUT, buf_MED_INIT_DATAREADY_OUT, buf_MED_REPLY_DATAREADY_OUT) begin - sent_INIT_ack <= '0'; - sent_REPLY_trm <= '0'; next_send_INIT_ack <= send_INIT_ack; next_send_REPLY_trm <= send_REPLY_trm; next_MED_INIT_DATA_OUT <= buf_MED_INIT_DATA_OUT; @@ -79,12 +69,13 @@ begin if send_INIT_ack = '1' then next_MED_INIT_DATAREADY_OUT <= '1'; if buf_MED_INIT_DATAREADY_OUT = '1' and MED_INIT_READ_IN = '1' then - if INIT_transfer_counter = "11" then + next_MED_INIT_DATA_OUT <= (others => '0'); + if INIT_transfer_counter = c_H0_next then next_MED_INIT_DATA_OUT(2 downto 0) <= TYPE_ACK; - elsif INIT_transfer_counter = "01" then + elsif INIT_transfer_counter = c_F1_next then next_MED_INIT_DATA_OUT(3 downto 0) <= "0111"; end if; - if INIT_transfer_counter = "10" then + if INIT_transfer_counter = c_F3_next then next_send_INIT_ack <= '0'; end if; end if; @@ -93,9 +84,9 @@ begin next_MED_REPLY_DATAREADY_OUT <= '1'; if buf_MED_REPLY_DATAREADY_OUT = '1' and MED_REPLY_READ_IN = '1' then next_MED_REPLY_DATA_OUT <= (others => '0'); - if REPLY_transfer_counter = "11" then + if REPLY_transfer_counter = c_H0_next then next_MED_REPLY_DATA_OUT(2 downto 0) <= TYPE_TRM; - elsif REPLY_transfer_counter = "10" then + elsif REPLY_transfer_counter = c_F3_next then next_MED_REPLY_DATA_OUT(11 downto 4) <= INIT_SEQNR; next_send_REPLY_trm <= '0'; end if; @@ -104,7 +95,7 @@ begin -- input data if MED_DATAREADY_IN = '1' then - if MED_PACKET_NUM_IN = "11" then + if MED_PACKET_NUM_IN = c_F3 then if saved_packet_type = '0' & TYPE_EOB then next_send_INIT_ack <= '1'; next_MED_INIT_DATAREADY_OUT <= '1'; @@ -129,9 +120,13 @@ begin begin if rising_edge(CLK) then if RESET = '1' then - INIT_transfer_counter <= "00"; + INIT_transfer_counter <= c_H0; elsif buf_MED_INIT_DATAREADY_OUT = '1' and MED_INIT_READ_IN = '1' then - INIT_transfer_counter <= INIT_transfer_counter + 1; + if INIT_transfer_counter = c_max_word_number then + INIT_transfer_counter <= (others => '0'); + else + INIT_transfer_counter <= INIT_transfer_counter + 1; + end if; end if; end if; end process; @@ -140,30 +135,32 @@ begin begin if rising_edge(CLK) then if RESET = '1' then - REPLY_transfer_counter <= "00"; + REPLY_transfer_counter <= c_H0; elsif buf_MED_REPLY_DATAREADY_OUT = '1' and MED_REPLY_READ_IN = '1' then - REPLY_transfer_counter <= REPLY_transfer_counter + 1; + if REPLY_transfer_counter = c_max_word_number then + REPLY_transfer_counter <= (others => '0'); + else + REPLY_transfer_counter <= REPLY_transfer_counter + 1; + end if; end if; end if; end process; MED_REPLY_DATAREADY_OUT <= buf_MED_REPLY_DATAREADY_OUT; MED_REPLY_DATA_OUT <= buf_MED_REPLY_DATA_OUT; - MED_REPLY_PACKET_NUM_OUT <= REPLY_transfer_counter; -- buf_MED_REPLY_PACKET_NUM_OUT; -- + MED_REPLY_PACKET_NUM_OUT <= REPLY_transfer_counter; MED_INIT_DATAREADY_OUT <= buf_MED_INIT_DATAREADY_OUT; MED_INIT_DATA_OUT <= buf_MED_INIT_DATA_OUT; - MED_INIT_PACKET_NUM_OUT <= INIT_transfer_counter; --buf_MED_INIT_PACKET_NUM_OUT; + MED_INIT_PACKET_NUM_OUT <= INIT_transfer_counter; MED_INIT_OUT_REG: process(CLK) begin if rising_edge(CLK) then if RESET = '1' then buf_MED_INIT_DATA_OUT <= (others => '0'); - buf_MED_INIT_PACKET_NUM_OUT <= "00"; buf_MED_INIT_DATAREADY_OUT <= '0'; - else + elsif CLK_EN = '1' then buf_MED_INIT_DATA_OUT <= next_MED_INIT_DATA_OUT; - buf_MED_INIT_PACKET_NUM_OUT <= INIT_transfer_counter; buf_MED_INIT_DATAREADY_OUT <= next_MED_INIT_DATAREADY_OUT; end if; end if; @@ -174,11 +171,9 @@ begin if rising_edge(CLK) then if RESET = '1' then buf_MED_REPLY_DATA_OUT <= (others => '0'); - buf_MED_REPLY_PACKET_NUM_OUT <= "00"; buf_MED_REPLY_DATAREADY_OUT <= '0'; - else + elsif CLK_EN = '1' then buf_MED_REPLY_DATA_OUT <= next_MED_REPLY_DATA_OUT; - buf_MED_REPLY_PACKET_NUM_OUT <= REPLY_transfer_counter; buf_MED_REPLY_DATAREADY_OUT <= next_MED_REPLY_DATAREADY_OUT; end if; end if; @@ -192,7 +187,7 @@ begin send_REPLY_trm <= '0'; send_INIT_ack <= '0'; INIT_SEQNR <= (others => '0'); - else + elsif CLK_EN = '1' then send_REPLY_trm <= next_send_REPLY_trm; send_INIT_ack <= next_send_INIT_ack; INIT_SEQNR <= next_INIT_SEQNR; @@ -206,7 +201,7 @@ begin if rising_edge(CLK) then if RESET = '1' then saved_packet_type <= "1111"; - elsif MED_PACKET_NUM_IN = "00" then + elsif MED_PACKET_NUM_IN = c_H0 then saved_packet_type <= MED_DATA_IN(3 downto 0); end if; end if; diff --git a/trb_net16_term_ibuf.vhd b/trb_net16_term_ibuf.vhd index 9b49b53..3cd79ef 100644 --- a/trb_net16_term_ibuf.vhd +++ b/trb_net16_term_ibuf.vhd @@ -89,13 +89,13 @@ begin if rising_edge(CLK) then if RESET = '1' then saved_packet_type <= "0111"; - elsif MED_PACKET_NUM_IN = "00" then + elsif MED_PACKET_NUM_IN = c_H0 then saved_packet_type <= MED_DATA_IN(3 downto 0); end if; end if; end process; --create comb. real packet type - current_packet_type <= MED_DATA_IN(3 downto 0) when (MED_PACKET_NUM_IN = "00") + current_packet_type <= MED_DATA_IN(3 downto 0) when (MED_PACKET_NUM_IN = c_H0) else saved_packet_type; -- this process controls the writing of the media into the fifo @@ -113,18 +113,18 @@ begin if MED_DATAREADY_IN = '1' then if current_packet_type = '1' & TYPE_ACK then --ACK in reply - if MED_PACKET_NUM_IN = "00" then + if MED_PACKET_NUM_IN = c_H0 then got_ack_internal <= '1'; - elsif MED_PACKET_NUM_IN = "10" then + elsif MED_PACKET_NUM_IN = c_F1 then next_rec_buffer_size_out <= MED_DATA_IN(3 downto 0); end if; elsif current_packet_type = '0' & TYPE_TRM then --TRM in init - if MED_PACKET_NUM_IN = "11" then + if MED_PACKET_NUM_IN = c_F3 then got_eob_out <= '1'; end if; tmp_INT_DATAREADY_OUT <= '1'; elsif current_packet_type = '0' & TYPE_EOB then --EOB in init - if MED_PACKET_NUM_IN = "11" then + if MED_PACKET_NUM_IN = c_F3 then got_eob_out <= '1'; end if; end if; diff --git a/trb_net16_trigger.vhd b/trb_net16_trigger.vhd index fb06d57..e1722b4 100644 --- a/trb_net16_trigger.vhd +++ b/trb_net16_trigger.vhd @@ -33,7 +33,7 @@ entity trb_net16_trigger is INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_OUT: out std_logic; - + -- Trigger information output TRG_TYPE_OUT : out std_logic_vector (3 downto 0); TRG_NUMBER_OUT : out std_logic_vector (15 downto 0); @@ -57,10 +57,10 @@ architecture trb_net16_trigger_arch of trb_net16_trigger is signal saved_packet_type : std_logic_vector(2 downto 0); - signal transfer_counter : std_logic_vector(1 downto 0); + signal transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal send_trm, next_send_trm : std_logic; signal buf_INT_DATAREADY_OUT, next_INT_DATAREADY_OUT : std_logic; - signal buf_INT_DATA_OUT, next_INT_DATA_OUT : std_logic_vector(15 downto 0); + signal buf_INT_DATA_OUT, next_INT_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); begin @@ -81,7 +81,7 @@ begin TRG_INFORMATION_OUT <= (others => '0'); TRG_RECEIVED_OUT <= '0'; INT_READ_OUT <= '1'; --not send_trm; - end generate; + end generate; process(RESET, transfer_counter, INT_READ_IN, saved_packet_type, buf_TRG_ERROR_PATTERN_IN, @@ -97,12 +97,12 @@ begin next_TRG_INFORMATION_OUT <= reg_TRG_INFORMATION_OUT; next_TRG_RECEIVED_OUT <= reg_TRG_RECEIVED_OUT; if saved_packet_type = TYPE_TRM then - if INT_PACKET_NUM_IN = "01" then + if INT_PACKET_NUM_IN = c_F1 then next_TRG_INFORMATION_OUT <= INT_DATA_IN(15 downto 0); - elsif INT_PACKET_NUM_IN = "10" then + elsif INT_PACKET_NUM_IN = c_F2 then next_TRG_NUMBER_OUT(15 downto 8) <= INT_DATA_IN(7 downto 0); next_TRG_CODE_OUT <= INT_DATA_IN(15 downto 8); - elsif INT_PACKET_NUM_IN = "11" then + elsif INT_PACKET_NUM_IN = c_F3 then next_TRG_TYPE_OUT <= INT_DATA_IN(3 downto 0); next_TRG_NUMBER_OUT(7 downto 0) <= INT_DATA_IN(11 downto 4); next_TRG_RECEIVED_OUT <= '1'; @@ -116,7 +116,7 @@ begin if (reg_TRG_RECEIVED_OUT = '1' and (TRG_RELEASE_IN = '1' or USE_TRG_PORT = 0)) or send_trm = '1' then -- if (reg_APL_GOT_TRM = '1' and (APL_RELEASE_TRM = '1' )) or send_trm = '1' or 0 = 0 then --next_transfer_counter is used for transmission! - if transfer_counter = "10" and INT_READ_IN = '1' then + if transfer_counter = c_F3_next and INT_READ_IN = '1' then next_send_trm <= '0'; else next_send_trm <= '1'; @@ -124,12 +124,14 @@ begin next_INT_DATAREADY_OUT <= '1'; end if; if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then - if transfer_counter = "11" then + if transfer_counter = c_H0_next then next_INT_DATA_OUT <= (others => '0'); next_INT_DATA_OUT(2 downto 0) <= TYPE_TRM; - elsif transfer_counter = "00" then + elsif transfer_counter = c_F0_next then + next_INT_DATA_OUT <= (others => '0'); + elsif transfer_counter = c_F1_next then next_INT_DATA_OUT <= buf_TRG_ERROR_PATTERN_IN(31 downto 16); - elsif transfer_counter = "01" then + elsif transfer_counter = c_F2_next then next_INT_DATA_OUT <= buf_TRG_ERROR_PATTERN_IN(15 downto 0); else next_INT_DATA_OUT <= (others => '0'); @@ -158,7 +160,7 @@ begin SECURE_GEN2: if SECURE_MODE = 0 generate buf_TRG_ERROR_PATTERN_IN <= TRG_ERROR_PATTERN_IN; end generate; - + --count packets REG_TRANSFER_COUNTER : process(CLK) @@ -167,7 +169,11 @@ begin if RESET = '1' then transfer_counter <= (others => '0'); elsif CLK_EN = '1' and buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then - transfer_counter <= transfer_counter + 1; + if transfer_counter = c_max_word_number then + transfer_counter <= (others => '0'); + else + transfer_counter <= transfer_counter + 1; + end if; end if; end if; end process; @@ -192,9 +198,9 @@ begin process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or (INT_PACKET_NUM_IN = "11" and INT_DATAREADY_IN = '1') then --or + if RESET = '1' or (INT_PACKET_NUM_IN = c_F3 and INT_DATAREADY_IN = '1') then --or saved_packet_type <= "111"; - elsif CLK_EN = '1' and INT_PACKET_NUM_IN = "00" then + elsif CLK_EN = '1' and INT_PACKET_NUM_IN = c_H0 then saved_packet_type <= INT_DATA_IN(2 downto 0); end if; end if; diff --git a/trb_net_dummy_fifo.vhd b/trb_net_dummy_fifo.vhd index 19835da..1efbf2f 100644 --- a/trb_net_dummy_fifo.vhd +++ b/trb_net_dummy_fifo.vhd @@ -10,18 +10,17 @@ use work.trb_net_std.all; entity trb_net_dummy_fifo is generic ( WIDTH : integer := 18 - ); + ); port ( - CLK : in std_logic; - RESET : in std_logic; + CLK : in std_logic; + RESET : in std_logic; CLK_EN : in std_logic; DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; + WRITE_ENABLE_IN : in std_logic; DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data - READ_ENABLE_IN : in std_logic; + READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) + EMPTY_OUT : out std_logic ); end trb_net_dummy_fifo; @@ -30,16 +29,14 @@ architecture arch_trb_net_dummy_fifo of trb_net_dummy_fifo is signal current_DOUT : std_logic_vector(WIDTH -1 downto 0); signal current_FULL, next_FULL : std_logic; - signal current_EMPTY, next_EMPTY : std_logic; - + signal current_EMPTY, next_EMPTY : std_logic; + begin FULL_OUT <= current_FULL; EMPTY_OUT <= current_EMPTY; DATA_OUT <= current_DOUT; - DEPTH_OUT <= (others => '0'); - process(READ_ENABLE_IN, WRITE_ENABLE_IN, current_EMPTY, current_FULL) begin if WRITE_ENABLE_IN = '1' and READ_ENABLE_IN = '1' then @@ -56,7 +53,7 @@ architecture arch_trb_net_dummy_fifo of trb_net_dummy_fifo is next_EMPTY <= current_EMPTY; end if; end process; - + reg_empty: process(CLK) begin if rising_edge(CLK) then @@ -75,11 +72,11 @@ architecture arch_trb_net_dummy_fifo of trb_net_dummy_fifo is if rising_edge(CLK) then if RESET = '1' then current_DOUT <= (others => '0'); - elsif WRITE_ENABLE_IN = '1' then + elsif WRITE_ENABLE_IN = '1' and CLK_EN = '1' then current_DOUT <= DATA_IN; end if; end if; end process; - + end arch_trb_net_dummy_fifo; diff --git a/trb_net_med_8bit_slow.vhd b/trb_net_med_8bit_slow.vhd index 6e10fde..fb34b38 100644 --- a/trb_net_med_8bit_slow.vhd +++ b/trb_net_med_8bit_slow.vhd @@ -16,35 +16,21 @@ entity trb_net_med_8bit_slow is RESET : in std_logic; CLK_EN : in std_logic; -- Internal direction port (MII) - -- 1st part: from the medium to the internal logic (trbnet) - INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media - --and ready to be read out (the IOBUF MUST read) - INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT:out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in STD_LOGIC; - INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- 2nd part: from the internal logic (trbnet) to the medium - INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media - INT_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out STD_LOGIC; -- offered word is read - INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - + INT_DATAREADY_OUT : out STD_LOGIC; + INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_READ_IN : in STD_LOGIC; + INT_ERROR_OUT : out STD_LOGIC_VECTOR (2 downto 0); + INT_DATAREADY_IN : in STD_LOGIC; + INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out STD_LOGIC; -- Media direction port - -- in this case for the cable => 32 lines in total - MED_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word - --(incl. debugging errorbits) - MED_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word - - -- Status and control port => this never can hurt + MED_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0); + MED_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0); + -- Status and control port STAT: out STD_LOGIC_VECTOR (31 downto 0); - --STAT(0): Busy reading from media - --STAT(1): Busy writing to media - --STAT(31 downto 28): packets_in (mod 16) - --STAT(27 downto 24): packets_out (mod 16) - --STAT(11 downto 8): INT2MED state - --STAT(15 downto 12): MED2INT state + --STAT(5 downto 2): Debug bits in CTRL: in STD_LOGIC_VECTOR (31 downto 0) --CTRL(24..31) -> lvds-data(63 downto 56) via lvds @@ -55,41 +41,34 @@ end entity trb_net_med_8bit_slow; architecture trb_net_med_8bit_slow_arch of trb_net_med_8bit_slow is signal buf_INT_DATA_IN, next_buf_INT_DATA_IN :std_logic_vector(7 downto 0); - signal buf_INT_PACKET_NUM_IN, next_buf_INT_PACKET_NUM_IN :std_logic_vector(1 downto 0); - signal next_INT_DATA_OUT, buf_INT_DATA_OUT: std_logic_vector(15 downto 0); - signal next_INT_PACKET_NUM_OUT, buf_INT_PACKET_NUM_OUT: std_logic_vector(1 downto 0); + signal next_INT_DATA_OUT, buf_INT_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal next_INT_PACKET_NUM_OUT, buf_INT_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); signal next_INT_DATAREADY_OUT, buf_INT_DATAREADY_OUT: std_logic; - signal next_buf_INT_READ_OUT, buf_INT_READ_OUT: std_logic; + signal buf_INT_READ_OUT: std_logic; signal reg_MED_FIRST_PACKET_IN : std_logic; signal next_buf_MED_DATA_OUT, buf_MED_DATA_OUT: std_logic_vector(7 downto 0); signal buf_MED_TRANSMISSION_CLK_OUT: std_logic; signal buf_MED_CARRIER_OUT, next_MED_CARRIER_OUT: STD_LOGIC; signal buf_MED_PARITY_OUT, next_MED_PARITY_OUT: STD_LOGIC; signal buf_MED_FIRST_PACKET_OUT, next_MED_FIRST_PACKET_OUT : std_logic; - signal my_error,next_my_error : std_logic_vector(2 downto 0); + signal my_error : std_logic_vector(2 downto 0); signal fatal_error, media_not_connected : std_logic; signal next_media_not_connected : std_logic; signal transmission_clk_Counter : std_logic_vector(4 downto 0); signal next_transmission_clk_Counter : std_logic_vector(4 downto 0); signal next_TRANSMISSION_CLK: std_logic; - signal buf_CTRL, next_STAT, buf_STAT : std_logic_vector(31 downto 0); - signal next_RECV_STAT, RECV_STAT : std_logic_vector(8 downto 0); + signal buf_STAT : std_logic_vector(31 downto 0); signal last_TRCLK, this_TRCLK: std_logic; signal CLK_counter,next_CLK_counter: std_logic_vector(7 downto 0); - signal packets_in_counter, next_packets_in_counter: std_logic_vector(7 downto 0); - signal packets_in_compl_counter, next_packets_in_compl_counter: std_logic_vector(3 downto 0); - signal packets_out_counter, next_packets_out_counter: std_logic_vector(3 downto 0); - signal last_MED_TRANSMISSION_CLK_IN : std_logic; signal last_MED_FIRST_PACKET_IN : std_logic; signal reg_MED_DATA_IN : std_logic_vector(7 downto 0); signal reg_MED_TRANSMISSION_CLK_IN, reg_MED_CARRIER_IN : std_logic; signal reg_MED_PARITY_IN : std_logic; - signal med2int_state_sig :std_logic_vector(2 downto 0); - signal recv_counter : std_logic_vector(2 downto 0); + signal recv_counter : std_logic_vector(3 downto 0); signal transmission_running, next_transmission_running : std_logic; signal buf_MED_DATA_IN, next_buf_MED_DATA_IN : std_logic_vector(7 downto 0); @@ -98,16 +77,16 @@ begin INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; INT_DATA_OUT <= buf_INT_DATA_OUT; INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; - INT_ERROR_OUT <= "000";--my_error; + INT_ERROR_OUT <= my_error; INT_READ_OUT <= buf_INT_READ_OUT; STAT <= buf_STAT; + buf_STAT(1 downto 0) <= (others => '0'); + buf_STAT(5 downto 2) <= MED_DATA_IN(11 downto 8); + buf_STAT(31 downto 6)<= (others => '0'); + MED_DATA_OUT(7 downto 0) <= buf_MED_DATA_OUT; - --MED_DATA_OUT(10 downto 8) <= recv_counter; - -- MED_DATA_OUT(8) <= buf_INT_DATAREADY_OUT; - -- MED_DATA_OUT(9) <= INT_READ_IN; - -- MED_DATA_OUT(10)<= buf_INT_PACKET_NUM_OUT(0); MED_DATA_OUT(10 downto 8) <= buf_MED_DATA_IN(2 downto 0); @@ -131,10 +110,10 @@ begin if rising_edge(CLK) then if RESET = '1' or media_not_connected = '1' or MED_DATA_IN(11) = '0' then my_error <= ERROR_NC; - elsif fatal_error = '1' then - next_my_error <= ERROR_FATAL; + elsif fatal_error = '1' or (INT_READ_IN = '0' and buf_INT_DATAREADY_OUT = '1') then + my_error <= ERROR_FATAL; else - next_my_error <= ERROR_OK; + my_error <= ERROR_OK; end if; end if; end process; @@ -220,7 +199,6 @@ begin next_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; next_MED_PARITY_OUT <= buf_MED_PARITY_OUT; next_buf_INT_DATA_IN <= buf_INT_DATA_IN; - next_buf_INT_READ_OUT <= buf_INT_READ_OUT; next_transmission_running <= transmission_running; next_MED_FIRST_PACKET_OUT <= buf_MED_FIRST_PACKET_OUT; buf_INT_READ_OUT <= '0'; @@ -235,7 +213,7 @@ begin next_MED_PARITY_OUT <= xor_all(INT_DATA_IN(15 downto 8)); next_transmission_running <= '1'; buf_INT_READ_OUT <= '1'; - if INT_PACKET_NUM_IN = "00" then + if INT_PACKET_NUM_IN = c_H0 then next_MED_FIRST_PACKET_OUT <= '1'; else next_MED_FIRST_PACKET_OUT <= '0'; @@ -292,12 +270,16 @@ begin begin if rising_edge(CLK) then if RESET = '1' then - recv_counter <= "111"; + recv_counter <= "0111"; elsif reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then - recv_counter <= recv_counter + 1; + if recv_counter = "1001" then + recv_counter <= "0000"; + else + recv_counter <= recv_counter + 1; + end if; last_MED_FIRST_PACKET_IN <= reg_MED_FIRST_PACKET_IN; if reg_MED_FIRST_PACKET_IN = '1' and last_MED_FIRST_PACKET_IN = '0' then - recv_counter <= "000"; + recv_counter <= "1000"; end if; end if; end if; @@ -307,7 +289,7 @@ begin MED2INT_fsm: process(buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT, buf_MED_DATA_IN, last_MED_TRANSMISSION_CLK_IN, reg_MED_TRANSMISSION_CLK_IN, reg_MED_DATA_IN, recv_counter, INT_READ_IN, reg_MED_CARRIER_IN, - buf_INT_PACKET_NUM_OUT) + buf_INT_PACKET_NUM_OUT, reg_MED_FIRST_PACKET_IN, last_MED_FIRST_PACKET_IN) begin next_INT_DATA_OUT <= buf_INT_DATA_OUT; next_INT_DATAREADY_OUT <= '0'; --buf_INT_DATAREADY_OUT; @@ -324,7 +306,7 @@ begin else next_INT_DATA_OUT(7 downto 0) <= reg_MED_DATA_IN; next_INT_DATA_OUT(15 downto 8) <= buf_MED_DATA_IN; - next_INT_PACKET_NUM_OUT <= recv_counter(2 downto 1); + next_INT_PACKET_NUM_OUT <= recv_counter(3 downto 1); next_INT_DATAREADY_OUT <= '1'; end if; end if; diff --git a/trb_net_priority_arbiter.vhd b/trb_net_priority_arbiter.vhd index 09ee4ce..2ea6829 100755 --- a/trb_net_priority_arbiter.vhd +++ b/trb_net_priority_arbiter.vhd @@ -7,21 +7,20 @@ library work; use work.trb_net_std.all; entity trb_net_priority_arbiter is - generic ( WIDTH : integer := 8 ); - port( + port( -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - ENABLE : in std_logic; - CTRL : in STD_LOGIC_VECTOR (31 downto 0) + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INPUT_IN : in std_logic_vector (WIDTH-1 downto 0); + RESULT_OUT: out std_logic_vector (WIDTH-1 downto 0); + ENABLE : in std_logic; + CTRL : in std_logic_vector (31 downto 0) ); -END trb_net_priority_arbiter; +end trb_net_priority_arbiter; architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter is diff --git a/trb_net_sbuf.vhd b/trb_net_sbuf.vhd index b3ce134..36fa354 100644 --- a/trb_net_sbuf.vhd +++ b/trb_net_sbuf.vhd @@ -27,25 +27,25 @@ entity trb_net_sbuf is ); port( -- Misc - CLK : in std_logic; - RESET : in std_logic; + CLK : in std_logic; + RESET : in std_logic; CLK_EN : in std_logic; -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT : out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN : in STD_LOGIC; --comb logic IS reading -- the COMB_next_READ_OUT should be connected via comb. logic to a register -- to provide COMB_READ_IN (feedback path with 1 cycle delay) -- The "REAL" READ_OUT can be constructed in the comb via COMB_next_READ_ -- OUT and the READ_IN: If one of these is ='1', no problem to read in next -- step. - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word -- Port to synchronous output. - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_READ_IN: in STD_LOGIC; + SYN_DATAREADY_OUT : out STD_LOGIC; + SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + SYN_READ_IN : in STD_LOGIC; -- Status and control port - STAT_BUFFER: out STD_LOGIC + STAT_BUFFER : out STD_LOGIC ); end trb_net_sbuf; @@ -57,15 +57,15 @@ architecture trb_net_sbuf_arch of trb_net_sbuf is signal next_SYN_DATAREADY_OUT, current_SYN_DATAREADY_OUT : std_logic; signal move_b1_buffer, move_b2_buffer: std_logic; - + type BUFFER_STATE is (BUFFER_EMPTY, BUFFER_B2_FULL, BUFFER_B1_FULL); signal current_buffer_state, next_buffer_state : BUFFER_STATE; signal current_buffer_state_int : STD_LOGIC_VECTOR (1 downto 0); - + signal current_got_overflow, next_got_overflow : std_logic; signal combined_COMB_DATAREADY_IN: std_logic; signal use_current_b1_buffer: std_logic; - + begin SYN_DATA_OUT <= current_b2_buffer; @@ -75,7 +75,7 @@ begin combined_COMB_DATAREADY_IN <= (COMB_DATAREADY_IN and COMB_READ_IN); - GEN1: if VERSION = 0 generate + GEN1: if VERSION = 0 generate MUX: process (use_current_b1_buffer, COMB_DATA_IN, current_b1_buffer) begin -- simple MUX @@ -86,7 +86,7 @@ begin end if; end process; end generate; - + GEN2: if VERSION = 1 generate next_b2_buffer <= COMB_DATA_IN; end generate; @@ -180,7 +180,7 @@ begin next_next_READ_OUT <= '0'; end if; end if; - + end process COMB; -- the next lines are an emergency stop @@ -220,7 +220,7 @@ begin end if; end process; - GEN6: if VERSION = 0 generate + GEN6: if VERSION = 0 generate REG2 : process(CLK) begin if rising_edge(CLK) then @@ -247,6 +247,6 @@ begin - + end trb_net_sbuf_arch; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 0b3cb0e..f255800 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -12,7 +12,7 @@ package trb_net_std is ----------------------------------------------- constant c_DATA_WIDTH : integer := 16; - constant c_NUM_WIDTH : integer := 2; + constant c_NUM_WIDTH : integer := 3; constant c_MUX_WIDTH : integer := 1; --!!! @@ -100,6 +100,8 @@ package trb_net_std is constant std_COMCTRLREG : integer := 1; --needed address width for common registers constant std_COMneededwidth : integer := 1; + constant c_REGIO_ADDRESS_WIDTH : integer := 16; + constant c_REGIO_REGISTER_WIDTH : integer := 32; --RegIO operation dtype constant c_network_control_type : std_logic_vector(3 downto 0) := x"F"; @@ -109,6 +111,21 @@ package trb_net_std is constant c_write_multiple_type : std_logic_vector(3 downto 0) := x"B"; +--Names of 16bit words + constant c_H0 : std_logic_vector(2 downto 0) := "100"; + constant c_F0 : std_logic_vector(2 downto 0) := "000"; + constant c_F1 : std_logic_vector(2 downto 0) := "001"; + constant c_F2 : std_logic_vector(2 downto 0) := "010"; + constant c_F3 : std_logic_vector(2 downto 0) := "011"; + + constant c_H0_next : std_logic_vector(2 downto 0) := "011"; + constant c_F0_next : std_logic_vector(2 downto 0) := "100"; + constant c_F1_next : std_logic_vector(2 downto 0) := "000"; + constant c_F2_next : std_logic_vector(2 downto 0) := "001"; + constant c_F3_next : std_logic_vector(2 downto 0) := "010"; + + constant c_max_word_number : std_logic_vector(2 downto 0) := "100"; + --function declarations function and_all (arg : std_logic_vector) diff --git a/xilinx/virtex2/trb_net16_fifo_arch.vhd b/xilinx/virtex2/trb_net16_fifo_arch.vhd index 46d2b6a..4d10ca5 100644 --- a/xilinx/virtex2/trb_net16_fifo_arch.vhd +++ b/xilinx/virtex2/trb_net16_fifo_arch.vhd @@ -8,26 +8,25 @@ use work.trb_net_std.all; entity trb_net16_fifo is generic ( USE_VENDOR_CORES : integer range 0 to 1 := c_NO; - DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets + DEPTH : integer := 6 -- Depth of the FIFO ); port ( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) + EMPTY_OUT : out std_logic ); end entity; architecture arch_trb_net16_fifo of trb_net16_fifo is -attribute box_type: string; + attribute box_type: string; component xilinx_fifo_18x1k port ( clk: IN std_logic; @@ -40,7 +39,7 @@ attribute box_type: string; empty: OUT std_logic ); end component; -attribute box_type of xilinx_fifo_18x1k : component is "black_box"; + attribute box_type of xilinx_fifo_18x1k : component is "black_box"; component xilinx_fifo_18x16 port ( @@ -54,7 +53,7 @@ attribute box_type of xilinx_fifo_18x1k : component is "black_box"; empty: OUT std_logic ); end component; -attribute box_type of xilinx_fifo_18x16 : component is "black_box"; + attribute box_type of xilinx_fifo_18x16 : component is "black_box"; component xilinx_fifo_18x32 port ( @@ -101,15 +100,15 @@ attribute box_type of xilinx_fifo_18x64 : component is "black_box"; ); end component; - signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH-1 downto 0); + signal din, dout : std_logic_vector(c_DATA_WIDTH + 2-1 downto 0); begin din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; - din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; + din(c_DATA_WIDTH + 2 -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); - DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8)); + PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 2 - 1 downto c_DATA_WIDTH); + gen_FIFO6 : if DEPTH = 6 generate fifo:xilinx_fifo_18x1k diff --git a/xilinx/virtex4/trb_net16_fifo_arch.vhd b/xilinx/virtex4/trb_net16_fifo_arch.vhd index f743310..2da24ca 100644 --- a/xilinx/virtex4/trb_net16_fifo_arch.vhd +++ b/xilinx/virtex4/trb_net16_fifo_arch.vhd @@ -8,21 +8,20 @@ use work.trb_net_std.all; entity trb_net16_fifo is generic ( USE_VENDOR_CORES : integer range 0 to 1 := c_NO; - DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets + DEPTH : integer := 6 ); port ( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic ); end entity; @@ -102,15 +101,13 @@ attribute box_type of xilinx_fifo_18x64 : component is "black_box"; ); end component; - signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH-1 downto 0); - signal depth16 : std_logic_vector(7 downto 0); + signal din, dout : std_logic_vector(c_DATA_WIDTH + 2-1 downto 0); begin din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; - din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; + din(c_DATA_WIDTH + 2 -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); - DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8)); + PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 2 - 1 downto c_DATA_WIDTH); gen_FIFO6 : if DEPTH = 6 generate fifo:xilinx_fifo_18x1k @@ -124,14 +121,14 @@ begin full => FULL_OUT, empty => EMPTY_OUT ); - + end generate; gen_OWN_CORES : if USE_VENDOR_CORES = c_NO generate gen_FIFO_LUT : if DEPTH < 6 generate fifo:xilinx_fifo_lut generic map ( - WIDTH => c_DATA_WIDTH + c_NUM_WIDTH, + WIDTH => c_DATA_WIDTH + 2, DEPTH => ((DEPTH+3)) ) port map (