From: hadaq Date: Sat, 10 Nov 2012 20:56:42 +0000 (+0000) Subject: deprecated X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0cea2ff4f13e9fdc8319e7426c80268dd3329861;p=trb3.git deprecated --- diff --git a/nxyter/source/i2c_gstart.vhd b/nxyter/source/i2c_gstart.vhd deleted file mode 100644 index 54b2c41..0000000 --- a/nxyter/source/i2c_gstart.vhd +++ /dev/null @@ -1,238 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.adcmv3_components.all; - -entity I2C_GSTART is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; - DOSTART_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector(8 downto 0); - SDONE_OUT : out std_logic; - SOK_OUT : out std_logic; - SDA_IN : in std_logic; - SCL_IN : in std_logic; - R_SCL_OUT : out std_logic; - S_SCL_OUT : out std_logic; - R_SDA_OUT : out std_logic; - S_SDA_OUT : out std_logic; - BSM_OUT : out std_logic_vector(3 downto 0) - ); -end entity; - -architecture Behavioral of I2C_GSTART is - --- Signals - type STATES is (SLEEP, - P_SCL, - WCTR0, - P_SDA, - WCTR1, - P_CHK, - S_CHK0, - RS_SDA, - S_CHK1, - ERROR, - DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - signal bsm : std_logic_vector(3 downto 0); - signal cctr : unsigned(8 downto 0); -- counter for bit length - - signal cycdone_x : std_logic; - signal cycdone : std_logic; -- one counter period done - - signal load_cyc_x : std_logic; - signal load_cyc : std_logic; - signal dec_cyc_x : std_logic; - signal dec_cyc : std_logic; - signal sdone_x : std_logic; - signal sdone : std_logic; -- Start/Stop done - signal sok_x : std_logic; - signal sok : std_logic; -- Start/Stop OK - - signal r_scl : std_logic; - signal s_scl : std_logic; - signal r_sda : std_logic; - signal s_sda : std_logic; - --- Moduls - -begin - --- Countdown for one half of SCL (adjustable clock width) - THE_CYC_CTR_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - cctr <= (others => '0'); - elsif( load_cyc = '1' ) then - cctr <= i2c_speed_in; - elsif( dec_cyc = '1' ) then - cctr <= cctr - 1; - end if; - end if; - end process THE_CYC_CTR_PROC; - --- end of cycle recognition - cycdone_x <= '1' when (cctr = 0) else '0'; - --- The main state machine --- State memory process - STATE_MEM: process( clk_in ) - begin - if ( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - CURRENT_STATE <= SLEEP; - load_cyc <= '0'; - dec_cyc <= '0'; - sdone <= '0'; - sok <= '0'; - cycdone <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - load_cyc <= load_cyc_x; - dec_cyc <= dec_cyc_x; - sdone <= sdone_x; - sok <= sok_x; - cycdone <= cycdone_x; - end if; - end if; - end process STATE_MEM; - --- Transition matrix - TRANSFORM: process(CURRENT_STATE, dostart_in, start_in, sda_in, scl_in, cycdone) - begin - NEXT_STATE <= SLEEP; - load_cyc_x <= '0'; - dec_cyc_x <= '0'; - sdone_x <= '0'; - sok_x <= '1'; - case CURRENT_STATE is - when SLEEP => if ( (dostart_in = '1') and (start_in = '1') ) then - NEXT_STATE <= S_CHK0; -- generate a start condition - load_cyc_x <= '1'; - elsif( (dostart_in = '1') and (start_in = '0') ) then - NEXT_STATE <= P_SCL; -- generate a stop condition - load_cyc_x <= '1'; - else - NEXT_STATE <= SLEEP; - end if; - when P_SCL => NEXT_STATE <= WCTR0; - dec_cyc_x <= '1'; - when S_CHK0 => if( (sda_in = '1') and (scl_in = '1') ) then - NEXT_STATE <= RS_SDA; - else - NEXT_STATE <= ERROR; - sok_x <= '0'; - end if; - when RS_SDA => NEXT_STATE <= WCTR0; - dec_cyc_x <= '1'; - when WCTR0 => if ( (cycdone = '1') and (start_in = '1') ) then - NEXT_STATE <= S_CHK1; - elsif( (cycdone = '1') and (start_in = '0') ) then - NEXT_STATE <= P_SDA; - load_cyc_x <= '1'; - else - NEXT_STATE <= WCTR0; - dec_cyc_x <= '1'; - end if; - when S_CHK1 => if( (sda_in = '0') and (scl_in = '1') ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= ERROR; - sok_x <= '0'; - end if; - when P_SDA => NEXT_STATE <= WCTR1; - dec_cyc_x <= '1'; - when WCTR1 => if( (cycdone = '1') ) then - NEXT_STATE <= P_CHK; - else - NEXT_STATE <= WCTR1; - dec_cyc_x <= '1'; - end if; - when P_CHK => if( (sda_in = '1') and (scl_in = '1') ) then - NEXT_STATE <= DONE; - sdone_x <= '1'; - else - NEXT_STATE <= ERROR; - sok_x <= '0'; - end if; - when ERROR => if( dostart_in = '0' ) then - NEXT_STATE <= SLEEP; - else - NEXT_STATE <= ERROR; - sdone_x <= '1'; - sok_x <= '0'; - end if; - when DONE => if( dostart_in = '0' ) then - NEXT_STATE <= SLEEP; - else - NEXT_STATE <= DONE; - sdone_x <= '1'; - end if; - when others => NEXT_STATE <= SLEEP; - end case; - end process TRANSFORM; - --- Output decoding - DECODE: process(CURRENT_STATE) - begin - case CURRENT_STATE is - when SLEEP => bsm <= x"0"; - when S_CHK0 => bsm <= x"1"; - when RS_SDA => bsm <= x"2"; - when P_SCL => bsm <= x"3"; - when WCTR0 => bsm <= x"4"; - when S_CHK1 => bsm <= x"5"; - when P_SDA => bsm <= x"6"; - when WCTR1 => bsm <= x"7"; - when P_CHK => bsm <= x"8"; - when DONE => bsm <= x"9"; - when ERROR => bsm <= x"e"; - when others => bsm <= x"f"; - end case; - end process DECODE; - - S_R_GEN: process(CURRENT_STATE) - begin - if ( CURRENT_STATE = P_SCL ) then - r_scl <= '0'; - s_scl <= '1'; - r_sda <= '0'; - s_sda <= '0'; - elsif( CURRENT_STATE = RS_SDA ) then - r_scl <= '0'; - s_scl <= '0'; - r_sda <= '1'; - s_sda <= '0'; - elsif( CURRENT_STATE = P_SDA ) then - r_scl <= '0'; - s_scl <= '0'; - r_sda <= '0'; - s_sda <= '1'; - else - r_scl <= '0'; - s_scl <= '0'; - r_sda <= '0'; - s_sda <= '0'; - end if; - end process S_R_GEN; - --- Outputs - r_scl_out <= r_scl; - s_scl_out <= s_scl; - r_sda_out <= r_sda; - s_sda_out <= s_sda; - sdone_out <= sdone; - sok_out <= sok; - --- Debug - bsm_out <= bsm; - -end Behavioral; diff --git a/nxyter/source/i2c_master.vhd b/nxyter/source/i2c_master.vhd deleted file mode 100644 index 59c9769..0000000 --- a/nxyter/source/i2c_master.vhd +++ /dev/null @@ -1,215 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.adcmv3_components.all; - -entity i2c_master is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - - -- I2C connections - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); -end entity; - -architecture Behavioral of i2c_master is - --- Signals - type STATES is (SLEEP, - RD_BSY, - WR_BSY, - RD_RDY, - WR_RDY, - RD_ACK, - WR_ACK, - DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - --- slave bus signals - signal slv_busy_x : std_logic; - signal slv_busy : std_logic; - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - - signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input - signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data - signal reg_busy : std_logic; - - signal status_data : std_logic_vector(31 downto 0); - signal i2c_debug : std_logic_vector(31 downto 0); - - signal i2c_speed_static : std_logic_vector(8 downto 0); - -begin - ---------------------------------------------------------- --- I2C master -- ---------------------------------------------------------- - - THE_I2C_SLIM: i2c_slim - port map( - CLK_IN => clk_in, - RESET_IN => reset_in, - -- I2C command / setup - I2C_GO_IN => reg_slv_data_in(31), - ACTION_IN => reg_slv_data_in(30), - I2C_SPEED_IN => i2c_speed_static, - I2C_ADR_IN => reg_slv_data_in(23 downto 16), - I2C_CMD_IN => reg_slv_data_in(15 downto 8), - I2C_DW_IN => reg_slv_data_in(7 downto 0), - I2C_DR_OUT => status_data(7 downto 0), - STATUS_OUT => status_data(31 downto 24), - I2C_BUSY_OUT => reg_busy, - -- I2C connections - SDA_IN => sda_in, - SDA_OUT => sda_out, - SCL_IN => scl_in, - SCL_OUT => scl_out, - -- Debug - STAT => i2c_debug - ); - - status_data(23 downto 21) <= (others => '0'); - status_data(20 downto 16) <= i2c_debug(4 downto 0); - status_data(15 downto 8) <= (others => '0'); - i2c_speed_static <= (others => '1'); - --- Fake - stat <= i2c_debug; - ---------------------------------------------------------- --- Statemachine -- ---------------------------------------------------------- --- State memory process - STATE_MEM: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - CURRENT_STATE <= SLEEP; - slv_busy <= '0'; - slv_ack <= '0'; - store_wr <= '0'; - store_rd <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - slv_busy <= slv_busy_x; - slv_ack <= slv_ack_x; - store_wr <= store_wr_x; - store_rd <= store_rd_x; - end if; - end if; - end process STATE_MEM; - --- Transition matrix - TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy ) - begin - NEXT_STATE <= SLEEP; - slv_busy_x <= '0'; - slv_ack_x <= '0'; - store_wr_x <= '0'; - store_rd_x <= '0'; - case CURRENT_STATE is - when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then - NEXT_STATE <= RD_RDY; - store_rd_x <= '1'; - elsif( (reg_busy = '0') and (slv_write_in = '1') ) then - NEXT_STATE <= WR_RDY; - store_wr_x <= '1'; - elsif( (reg_busy = '1') and (slv_read_in = '1') ) then - NEXT_STATE <= RD_BSY; - slv_busy_x <= '1'; - elsif( (reg_busy = '1') and (slv_write_in = '1') ) then - NEXT_STATE <= WR_BSY; - slv_busy_x <= '1'; - else - NEXT_STATE <= SLEEP; - end if; - when RD_RDY => NEXT_STATE <= RD_ACK; - slv_ack_x <= '1'; - when WR_RDY => NEXT_STATE <= WR_ACK; - slv_ack_x <= '1'; - when RD_ACK => if ( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= RD_ACK; - slv_ack_x <= '1'; - end if; - when WR_ACK => if ( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= WR_ACK; - slv_ack_x <= '1'; - end if; - when RD_BSY => if ( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= RD_BSY; - slv_busy_x <= '1'; - end if; - when WR_BSY => if ( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= WR_BSY; - slv_busy_x <= '1'; - end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; - end case; - end process TRANSFORM; - ---------------------------------------------------------- --- data handling -- ---------------------------------------------------------- - --- register write - THE_WRITE_REG_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if ( reset_in = '1' ) then - reg_slv_data_in <= (others => '0'); - elsif( store_wr = '1' ) then - reg_slv_data_in <= slv_data_in; - end if; - end if; - end process THE_WRITE_REG_PROC; - --- register read - THE_READ_REG_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if ( reset_in = '1' ) then - reg_slv_data_out <= (others => '0'); - elsif( store_rd = '1' ) then - reg_slv_data_out <= status_data; - end if; - end if; - end process THE_READ_REG_PROC; - --- output signals - slv_ack_out <= slv_ack; - slv_busy_out <= slv_busy; - slv_data_out <= reg_slv_data_out; - -end Behavioral; diff --git a/nxyter/source/i2c_sendb.vhd b/nxyter/source/i2c_sendb.vhd deleted file mode 100644 index af29247..0000000 --- a/nxyter/source/i2c_sendb.vhd +++ /dev/null @@ -1,305 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.adcmv3_components.all; - -entity i2c_sendb is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - DOBYTE_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector( 8 downto 0 ); - I2C_BYTE_IN : in std_logic_vector( 8 downto 0 ); - I2C_BACK_OUT : out std_logic_vector( 8 downto 0 ); - SDA_IN : in std_logic; - R_SDA_OUT : out std_logic; - S_SDA_OUT : out std_logic; - R_SCL_OUT : out std_logic; - S_SCL_OUT : out std_logic; - BDONE_OUT : out std_logic; - BOK_OUT : out std_logic; - BSM_OUT : out std_logic_vector( 3 downto 0 ) - ); -end entity; - -architecture Behavioral of i2c_sendb is - --- Signals - type STATES is (SLEEP, - LCL, - WCL, - LCH, - WCH, - FREE, - DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - signal bsm : std_logic_vector( 3 downto 0 ); - - signal inc_bit_x : std_logic; - signal inc_bit : std_logic; -- increment bit counter for byte to send - signal rst_bit_x : std_logic; - signal rst_bit : std_logic; -- reset bit counter for byte to send - signal load_cyc_x : std_logic; - signal load_cyc : std_logic; -- load cycle counter (SCL length) - signal dec_cyc_x : std_logic; - signal dec_cyc : std_logic; -- decrement cycle counter (SCL length) - signal load_sr_x : std_logic; - signal load_sr : std_logic; -- load output shift register - signal shift_o_x : std_logic; - signal shift_o : std_logic; -- output shift register control - signal shift_i_x : std_logic; - signal shift_i : std_logic; -- input shift register control - signal bdone_x : std_logic; - signal bdone : std_logic; - signal r_scl_x : std_logic; - signal r_scl : std_logic; -- output for SCL - signal s_scl_x : std_logic; - signal s_scl : std_logic; -- output for SCL - - signal bctr : std_logic_vector( 3 downto 0 ); -- bit counter (1...9) - signal cctr : unsigned(8 downto 0); -- counter for bit length - signal bok : std_logic; - signal cycdone : std_logic; -- one counter period done - signal bytedone : std_logic; -- all bits sents - signal in_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte in - signal out_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte out - signal i2c_back : std_logic_vector( 8 downto 0 ); -- shift register for byte in - signal r_sda : std_logic; -- output for SDA - signal s_sda : std_logic; -- output for SDA - signal load : std_logic; -- delay register - signal i2c_d : std_logic; -- auxiliary register - --- Moduls - -begin - --- Bit counter (for byte to send) - THE_BIT_CTR_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - bctr <= (others => '0'); - elsif( rst_bit = '1' ) then - bctr <= (others => '0'); - elsif( inc_bit = '1' ) then - bctr <= bctr + 1; - end if; - end if; - end process THE_BIT_CTR_PROC; - --- end of byte recognition - bytedone <= '1' when (bctr = x"a") else '0'; - --- Countdown for one half of SCL (adjustable clock width) - THE_CYC_CTR_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - cctr <= (others => '0'); - elsif( load_cyc = '1' ) then - cctr <= i2c_speed_in; - elsif( dec_cyc = '1' ) then - cctr <= cctr - 1; - end if; - end if; - end process THE_CYC_CTR_PROC; - --- end of cycle recognition - cycdone <= '1' when (cctr = 0) else '0'; - --- Bit output - THE_BIT_OUT_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - out_sr <= (others => '0'); - i2c_d <= '1'; - elsif( load_sr = '1' ) then - out_sr <= i2c_byte_in; - i2c_d <= '1'; - elsif( shift_o = '1' ) then - i2c_d <= out_sr(8); - out_sr(8 downto 0) <= out_sr(7 downto 0) & '0'; - end if; - end if; - end process THE_BIT_OUT_PROC; - --- Bit input - THE_BIT_IN_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if ( reset_in = '1' ) then - in_sr <= (others => '1'); - elsif( shift_o = '1' ) then - in_sr(8 downto 1) <= in_sr(7 downto 0); - in_sr(0) <= sda_in; - end if; - end if; - end process THE_BIT_IN_PROC; - --- Output register for readback data (could be reduced to SR_IN_INT) - THE_I2C_BACK_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - i2c_back <= (others => '1'); - elsif( shift_i = '1' ) then - i2c_back(8 downto 1) <= in_sr(7 downto 0); - i2c_back(0) <= sda_in; - end if; - end if; - end process THE_I2C_BACK_PROC; - --- ByteOK is the inverted ACK bit from readback data. - bok <= not i2c_back(0); -- BUG - --- The main state machine --- State memory process - STATE_MEM: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1') then - CURRENT_STATE <= SLEEP; - inc_bit <= '0'; - rst_bit <= '0'; - load_cyc <= '0'; - dec_cyc <= '0'; - load_sr <= '0'; - shift_o <= '0'; - shift_i <= '0'; - bdone <= '0'; - r_scl <= '0'; - s_scl <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - inc_bit <= inc_bit_x; - rst_bit <= rst_bit_x; - load_cyc <= load_cyc_x; - dec_cyc <= dec_cyc_x; - load_sr <= load_sr_x; - shift_o <= shift_o_x; - shift_i <= shift_i_x; - bdone <= bdone_x; - r_scl <= r_scl_x; - s_scl <= s_scl_x; - end if; - end if; - end process STATE_MEM; - --- Transition matrix - TRANSFORM: process(CURRENT_STATE, dobyte_in, cycdone, bytedone) - begin - NEXT_STATE <= SLEEP; - inc_bit_x <= '0'; - rst_bit_x <= '0'; - load_cyc_x <= '0'; - dec_cyc_x <= '0'; - load_sr_x <= '0'; - shift_o_x <= '0'; - shift_i_x <= '0'; - bdone_x <= '0'; - r_scl_x <= '0'; - s_scl_x <= '0'; - case CURRENT_STATE is - when SLEEP => if( dobyte_in = '1' ) then - NEXT_STATE <= LCL; - inc_bit_x <= '1'; - load_cyc_x <= '1'; - shift_o_x <= '1'; - r_scl_x <= '1'; - else - NEXT_STATE <= SLEEP; - load_sr_x <= '1'; - end if; - when LCL => NEXT_STATE <= WCL; - dec_cyc_x <= '1'; - when WCL => if( cycdone = '1' ) then - NEXT_STATE <= LCH; - load_cyc_x <= '1'; - s_scl_x <= '1'; - else - NEXT_STATE <= WCL; - dec_cyc_x <= '1'; - end if; - when LCH => NEXT_STATE <= WCH; - dec_cyc_x <= '1'; - when WCH => if ( (cycdone = '1') and (bytedone = '0') ) then - NEXT_STATE <= LCL; - inc_bit_x <= '1'; - load_cyc_x <= '1'; - shift_o_x <= '1'; - r_scl_x <= '1'; - elsif( (cycdone = '1') and (bytedone = '1') ) then - NEXT_STATE <= FREE; - shift_o_x <= '1'; - shift_i_x <= '1'; - r_scl_x <= '1'; - else - NEXT_STATE <= WCH; - dec_cyc_x <= '1'; - end if; - when FREE => NEXT_STATE <= DONE; - rst_bit_x <= '1'; - bdone_x <= '1'; - when DONE => if( dobyte_in = '0' ) then - NEXT_STATE <= SLEEP; - else - NEXT_STATE <= DONE; - rst_bit_x <= '1'; - bdone_x <= '1'; - end if; - -- Just in case... - when others => NEXT_STATE <= SLEEP; - end case; - end process TRANSFORM; - --- Output decoding - DECODE: process(CURRENT_STATE) - begin - case CURRENT_STATE is - when SLEEP => bsm <= x"0"; - when LCL => bsm <= x"1"; - when WCL => bsm <= x"2"; - when LCH => bsm <= x"3"; - when WCH => bsm <= x"4"; - when FREE => bsm <= x"5"; - when DONE => bsm <= x"6"; - when others => bsm <= x"f"; - end case; - end process DECODE; - --- SCL and SDA output pulses - THE_SDA_OUT_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - load <= '0'; -- was a bug, found 081008 - r_sda <= '0'; - s_sda <= '0'; - else - load <= shift_o; - r_sda <= load and not i2c_d; - s_sda <= load and i2c_d; - end if; - end if; - end process THE_SDA_OUT_PROC; - --- Outputs - r_scl_out <= r_scl; - s_scl_out <= s_scl; - r_sda_out <= r_sda; - s_sda_out <= s_sda; - - i2c_back_out <= i2c_back; - - bdone_out <= bdone; - bok_out <= bok; - --- Debugging - bsm_out <= bsm; - -end Behavioral; diff --git a/nxyter/source/i2c_slim.vhd b/nxyter/source/i2c_slim.vhd deleted file mode 100644 index a219332..0000000 --- a/nxyter/source/i2c_slim.vhd +++ /dev/null @@ -1,465 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.adcmv3_components.all; - -entity i2c_slim is - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- I2C command / setup - I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions - ACTION_IN : in std_logic; -- '0' -> write, '1' -> read - I2C_SPEED_IN : in std_logic_vector( 8 downto 0 ); -- speed adjustment - I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored) - I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte) - I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command - I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command - STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits - I2C_BUSY_OUT : out std_logic; - - -- I2C connections - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - - -- Debug - STAT : out std_logic_vector(31 downto 0) - ); -end i2c_slim; - -architecture Behavioral of i2c_slim is - --- Signals - type STATES is (SLEEP, - LOADA, - GSTART, - SENDA, - LOADC, - SENDC, - LOADD, - SENDD, - GSTOP, - INC, - E_START, - E_ADDR, - E_CMD, - E_WD, - E_RSTART, - E_RADDR, - DONE, - FAILED, - CLRERR); - signal CURRENT_STATE, NEXT_STATE: STATES; - - signal bsm : std_logic_vector( 4 downto 0 ); - signal phase : std_logic; -- '0' => first phase, '1' => second phase of read cycle - - signal start_x : std_logic; - signal start : std_logic; -- '0' => generate STOP, '1' => generate START - signal dostart_x : std_logic; - signal dostart : std_logic; -- trigger the GenStart module - signal dobyte_x : std_logic; - signal dobyte : std_logic; -- trigger the ByteSend module - signal i2c_done_x : std_logic; - signal i2c_done : std_logic; -- acknowledge signal to the outside world - signal running_x : std_logic; - signal running : std_logic; -- legacy - - signal load_a_x : std_logic; - signal load_a : std_logic; - signal load_c_x : std_logic; - signal load_c : std_logic; - signal load_d_x : std_logic; - signal load_d : std_logic; - - signal sdone : std_logic; -- acknowledge signal from GenStart module - signal sok : std_logic; -- status signal from GenStart module - signal bdone : std_logic; -- acknowledge signal from SendByte module - signal bok : std_logic; -- status signal from SendByte module - signal e_sf : std_logic; -- Start failed - signal e_anak : std_logic; -- Adress byte NAK - signal e_cnak : std_logic; -- Command byte NAK - signal e_dnak : std_logic; -- Data byte NAK - signal e_rsf : std_logic; -- Repeated Start failed - signal e_ranak : std_logic; -- Repeated Adress NAK - signal i2c_byte : std_logic_vector( 8 downto 0 ); - signal i2c_dr : std_logic_vector( 8 downto 0 ); - - signal s_scl : std_logic; - signal r_scl : std_logic; - signal s_sda : std_logic; - signal r_sda : std_logic; - signal r_scl_gs : std_logic; - signal s_scl_gs : std_logic; - signal r_sda_gs : std_logic; - signal s_sda_gs : std_logic; - signal r_scl_sb : std_logic; - signal s_scl_sb : std_logic; - signal r_sda_sb : std_logic; - signal s_sda_sb : std_logic; - - signal gs_debug : std_logic_vector(3 downto 0); - - signal i2c_speed : std_logic_vector(8 downto 0); - -begin - - i2c_speed <= I2C_SPEED_IN & "00"; - --- Read phase indicator - THE_PHASE_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - phase <= '0'; - elsif( CURRENT_STATE = INC ) then - phase <= '1'; - elsif( (CURRENT_STATE = DONE) or (CURRENT_STATE = SLEEP) ) then - phase <= '0'; - end if; - end if; - end process THE_PHASE_PROC; - --- The main state machine --- State memory process - STATE_MEM: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - CURRENT_STATE <= SLEEP; - start <= '0'; - dostart <= '0'; - dobyte <= '0'; - i2c_done <= '0'; - running <= '0'; - load_a <= '0'; - load_c <= '0'; - load_d <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - start <= start_x; - dostart <= dostart_x; - dobyte <= dobyte_x; - i2c_done <= i2c_done_x; - running <= running_x; - load_a <= load_a_x; - load_c <= load_c_x; - load_d <= load_d_x; - end if; - end if; - end process STATE_MEM; - --- Transition matrix - TRANSFORM: process(CURRENT_STATE, i2c_go_in, sdone, sok, phase, bdone, bok, action_in) - begin - NEXT_STATE <= SLEEP; - start_x <= '0'; - dostart_x <= '0'; - dobyte_x <= '0'; - i2c_done_x <= '0'; - running_x <= '1'; - load_a_x <= '0'; - load_c_x <= '0'; - load_d_x <= '0'; - case CURRENT_STATE is - when SLEEP => if( i2c_go_in = '1' ) then - NEXT_STATE <= CLRERR; - else - NEXT_STATE <= SLEEP; - running_x <= '0'; - end if; - when CLRERR => NEXT_STATE <= LOADA; - load_a_x <= '1'; - when LOADA => NEXT_STATE <= GSTART; - start_x <= '1'; - dostart_x <= '1'; - when GSTART => if ( (sdone = '1') and (sok = '1') ) then - NEXT_STATE <= SENDA; - dobyte_x <= '1'; - elsif( (sdone = '1') and (sok = '0') and (phase = '0') ) then - NEXT_STATE <= E_START; -- first START condition failed - elsif( (sdone = '1') and (sok = '0') and (phase = '1') ) then - NEXT_STATE <= E_RSTART; -- second START condition failed - else - NEXT_STATE <= GSTART; - start_x <= '1'; - dostart_x <= '1'; - end if; - when E_START => NEXT_STATE <= FAILED; - dostart_x <= '1'; - when E_RSTART => NEXT_STATE <= FAILED; - dostart_x <= '1'; - when SENDA => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then - NEXT_STATE <= LOADC; -- I2C write - load_c_x <= '1'; - elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '0') ) then - NEXT_STATE <= LOADC; -- I2C read, send register address - load_c_x <= '1'; - elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '1') ) then - NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte - load_d_x <= '1'; - elsif( (bdone = '1') and (bok = '0') and (phase = '0') ) then - NEXT_STATE <= E_ADDR; -- first address phase failed - elsif( (bdone = '1') and (bok = '0') and (phase = '1') ) then - NEXT_STATE <= E_RADDR; -- second address phase failed - else - NEXT_STATE <= SENDA; - dobyte_x <= '1'; - end if; - when E_ADDR => NEXT_STATE <= FAILED; - dostart_x <= '1'; - when E_RADDR => NEXT_STATE <= FAILED; - dostart_x <= '1'; - when LOADC => NEXT_STATE <= SENDC; --- dobyte_x <= '1'; - when SENDC => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then - NEXT_STATE <= LOADD; -- I2C write, prepare data - load_d_x <= '1'; - elsif( (bdone = '1') and (bok = '1') and (action_in = '1') ) then - NEXT_STATE <= GSTOP; -- I2C read, first phase ends - dostart_x <= '1'; - elsif( (bdone = '1') and (bok = '0') ) then - NEXT_STATE <= E_CMD; -- command phase failed - else - NEXT_STATE <= SENDC; - dobyte_x <= '1'; - end if; - when E_CMD => NEXT_STATE <= FAILED; - dostart_x <= '1'; - when LOADD => NEXT_STATE <= SENDD; - when SENDD => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then - NEXT_STATE <= GSTOP; -- I2C write, data phase failed - dostart_x <= '1'; - elsif( (bdone = '1') and (action_in = '1') ) then - NEXT_STATE <= GSTOP; -- I2C read, data phase - dostart_x <= '1'; - elsif( (bdone = '1') and (bok = '0') and (action_in = '0') ) then - NEXT_STATE <= E_WD; -- I2C write, data phase failed - else - NEXT_STATE <= SENDD; - dobyte_x <= '1'; - end if; - when E_WD => NEXT_STATE <= FAILED; - dostart_x <= '1'; - when GSTOP => if ( (sdone = '1') and (action_in = '0') ) then - NEXT_STATE <= DONE; - elsif( (sdone = '1') and (action_in = '1') and (phase = '1') ) then - NEXT_STATE <= DONE; - elsif( (sdone = '1') and (action_in = '1') and (phase = '0') ) then - NEXT_STATE <= INC; - else - NEXT_STATE <= GSTOP; - dostart_x <= '1'; - end if; - when INC => NEXT_STATE <= LOADA; - load_a_x <= '1'; - when FAILED => if( sdone = '1' ) then - NEXT_STATE <= DONE; - i2c_done_x <= '1'; - running_x <= '0'; - else - NEXT_STATE <= FAILED; - dostart_x <= '1'; - end if; - when DONE => if( i2c_go_in = '1' ) then - NEXT_STATE <= DONE; - i2c_done_x <= '1'; - running_x <= '0'; - else - NEXT_STATE <= SLEEP; - end if; - -- Just in case... - when others => NEXT_STATE <= SLEEP; - end case; - end process TRANSFORM; - --- Output decoding - DECODE: process(CURRENT_STATE) - begin - case CURRENT_STATE is - when SLEEP => bsm <= b"00000"; -- 00 - when CLRERR => bsm <= b"01100"; -- 0c - when LOADA => bsm <= b"00001"; -- 01 - when GSTART => bsm <= b"00010"; -- 02 - when SENDA => bsm <= b"00011"; -- 03 - when LOADC => bsm <= b"00100"; -- 04 - when SENDC => bsm <= b"00101"; -- 05 - when LOADD => bsm <= b"00110"; -- 06 - when SENDD => bsm <= b"00111"; -- 07 - when GSTOP => bsm <= b"01000"; -- 08 - when INC => bsm <= b"01001"; -- 09 - when FAILED => bsm <= b"01010"; -- 0a - when DONE => bsm <= b"01011"; -- 0b - when E_START => bsm <= b"10000"; -- 10 - when E_RSTART => bsm <= b"10001"; -- 11 - when E_ADDR => bsm <= b"10010"; -- 12 - when E_RADDR => bsm <= b"10011"; -- 13 - when E_CMD => bsm <= b"10100"; -- 14 - when E_WD => bsm <= b"10101"; -- 15 - when others => bsm <= b"11111"; -- 1f - end case; - end process DECODE; - --- We need to load different data sets - LOAD_DATA_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if ( reset_in = '1' ) then - i2c_byte <= (others => '1'); - elsif( (CURRENT_STATE = LOADA) and (phase = '0') ) then - i2c_byte <= i2c_adr_in(6 downto 0) & '0' & '1'; -- send write address, receive ACK - elsif( (CURRENT_STATE = LOADA) and (phase = '1') ) then - i2c_byte <= i2c_adr_in(6 downto 0) & '1' & '1'; -- send read address, receive ACK - elsif( (CURRENT_STATE = LOADC) and (action_in = '0') ) then - i2c_byte <= i2c_cmd_in(7 downto 0) & '1'; -- send command byte, receive ACK - elsif( (CURRENT_STATE = LOADC) and (action_in = '1') ) then - i2c_byte <= i2c_cmd_in(7 downto 0) & '1'; -- send command byte, receive ACK - elsif( (CURRENT_STATE = LOADD) and (action_in = '0') ) then - i2c_byte <= i2c_dw_in & '1'; -- send data byte, receive ACK - elsif( (CURRENT_STATE = LOADD) and (action_in = '1') ) then - i2c_byte <= x"ff" & '1'; -- send 0xff byte, send NACK - end if; - end if; - end process LOAD_DATA_PROC; - --- The SendByte module - THE_I2C_SENDB: I2C_SENDB - port map( - CLK_IN => clk_in, - RESET_IN => reset_in, - DOBYTE_IN => dobyte, - I2C_SPEED_IN => i2c_speed, - I2C_BYTE_IN => i2c_byte, - I2C_BACK_OUT => i2c_dr, - SDA_IN => sda_in, - R_SDA_OUT => r_sda_sb, - S_SDA_OUT => s_sda_sb, - R_SCL_OUT => r_scl_sb, - S_SCL_OUT => s_scl_sb, - BDONE_OUT => bdone, - BOK_OUT => bok, - BSM_OUT => open - ); - --- The GenStart module - THE_I2C_GSTART: I2C_GSTART - port map( - CLK_IN => clk_in, - RESET_IN => reset_in, - START_IN => start, - DOSTART_IN => dostart, - I2C_SPEED_IN => i2c_speed, - SDONE_OUT => sdone, - SOK_OUT => sok, - SDA_IN => sda_in, - SCL_IN => scl_in, - R_SCL_OUT => r_scl_gs, - S_SCL_OUT => s_scl_gs, - R_SDA_OUT => r_sda_gs, - S_SDA_OUT => s_sda_gs, - BSM_OUT => gs_debug --open - ); - - r_scl <= r_scl_gs or r_scl_sb; - s_scl <= s_scl_gs or s_scl_sb; - r_sda <= r_sda_gs or r_sda_sb; - s_sda <= s_sda_gs or s_sda_sb; - --- Output flipflops for SCL and SDA lines - THE_SCL_SDA_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - scl_out <= '1'; - sda_out <= '1'; - elsif( (r_scl = '1') and (s_scl = '0') ) then - scl_out <= '0'; - elsif( (r_scl = '0') and (s_scl = '1') ) then - scl_out <= '1'; - elsif( (r_sda = '1') and (s_sda = '0') ) then - sda_out <= '0'; - elsif( (r_sda = '0') and (s_sda = '1') ) then - sda_out <= '1'; - end if; - end if; - end process THE_SCL_SDA_PROC; - --- Error bits - THE_ERR_REG_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - e_sf <= '0'; - e_anak <= '0'; - e_cnak <= '0'; - e_dnak <= '0'; - e_rsf <= '0'; - e_ranak <= '0'; - elsif( CURRENT_STATE = CLRERR ) then - e_sf <= '0'; - e_anak <= '0'; - e_cnak <= '0'; - e_dnak <= '0'; - e_rsf <= '0'; - e_ranak <= '0'; - elsif( CURRENT_STATE = E_START ) then - e_sf <= '1'; - elsif( CURRENT_STATE = E_RSTART ) then - e_rsf <= '1'; - elsif( CURRENT_STATE = E_ADDR ) then - e_anak <= '1'; - elsif( CURRENT_STATE = E_RADDR ) then - e_ranak <= '1'; - elsif( CURRENT_STATE = E_CMD ) then - e_cnak <= '1'; - elsif( CURRENT_STATE = E_WD ) then - e_dnak <= '1'; - end if; - end if; - end process THE_ERR_REG_PROC; - - status_out(7) <= running; - status_out(6) <= i2c_done; - status_out(5) <= e_ranak; - status_out(4) <= e_rsf; - status_out(3) <= e_dnak; - status_out(2) <= e_cnak; - status_out(1) <= e_anak; - status_out(0) <= e_sf; - --- Outputs - i2c_dr_out <= i2c_dr(8 downto 1); - i2c_busy_out <= running; - --- Debug stuff - stat(31 downto 28) <= (others => '0'); - stat(27) <= s_sda; - stat(26) <= r_sda; - stat(25) <= s_scl; - stat(24) <= r_scl; - stat(23) <= s_sda_sb; - stat(22) <= r_sda_sb; - stat(21) <= s_scl_sb; - stat(20) <= r_scl_sb; - stat(19) <= s_sda_gs; - stat(18) <= r_sda_gs; - stat(17) <= s_scl_gs; - stat(16) <= r_scl_gs; - stat(15 downto 12) <= gs_debug; - stat(11) <= bok; - stat(10) <= bdone; - stat(9) <= dobyte; - stat(8) <= sok; - stat(7) <= dobyte; - stat(6) <= s_sda_sb; - stat(5) <= r_sda_sb; - stat(4 downto 0) <= bsm; - - -end Behavioral; diff --git a/nxyter/source/nx_i2c_master.vhd- b/nxyter/source/nx_i2c_master.vhd- deleted file mode 100644 index 18eba6a..0000000 --- a/nxyter/source/nx_i2c_master.vhd- +++ /dev/null @@ -1,381 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.nxyter_components.all; - -entity nx_i2c_master is - generic ( - i2c_speed : unsigned(11 downto 0) := x"3e8" - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- I2C connections - SDA_INOUT : inout std_logic; - SCL_INOUT : inout std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - -- Debug Line - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture Behavioral of nx_i2c_master is - - signal sda_i : std_logic; - signal sda_x : std_logic; - signal sda : std_logic; - - signal scl_i : std_logic; - signal scl_x : std_logic; - signal scl : std_logic; - - -- I2C Master - signal sda_o : std_logic; - signal scl_o : std_logic; - signal i2c_start : std_logic; - - signal sda_startstop : std_logic; - signal scl_startstop : std_logic; - signal startstop_select : std_logic; - signal startstop_seq_start : std_logic; - signal startstop_done : std_logic; - - signal sda_sendbyte : std_logic; - signal scl_sendbyte : std_logic; - signal sendbyte_seq_start : std_logic; - signal sendbyte_byte : std_logic_vector(7 downto 0); - signal sendbyte_done : std_logic; - signal sendbyte_ack : std_logic; - - signal i2c_byte : unsigned(7 downto 0); - signal bit_ctr : unsigned(3 downto 0); - signal i2c_ack : std_logic; - signal i2c_error : std_logic_vector(3 downto 0); - - type STATES is (S_IDLE, - S_START, - S_START_WAIT, - - S_SEND_BYTE, - S_SET_SDA, - S_SET_SCL, - S_UNSET_SCL, - S_NEXT_BIT, - - S_GET_ACK, - S_ACK_SET_SCL, - S_STORE_ACK, - S_ACK_UNSET_SCL, - S_VERIFY_ACK, - S_ACK_ERROR, - - S_STOP, - S_STOP_WAIT - ); - signal STATE : STATES; - - - -- I2C Timer - signal wait_timer_init : unsigned(11 downto 0); - signal wait_timer_done : std_logic; - - -- TRBNet Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - signal reg_data : std_logic_vector(31 downto 0); - signal i2c_chipid : std_logic_vector(6 downto 0); - signal i2c_rw_bit : std_logic; - - -begin - - -- Timer - nx_i2c_timer_1: nx_i2c_timer - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - -- Start / Stop Sequence - nx_i2c_startstop_1: nx_i2c_startstop - generic map ( - i2c_speed => i2c_speed - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - START_IN => startstop_seq_start, - SELECT_IN => startstop_select, - SEQUENCE_DONE_OUT => startstop_done, - SDA_OUT => sda_startstop, - SCL_OUT => scl_startstop - ); - - nx_i2c_sendbyte_1: nx_i2c_sendbyte - generic map ( - i2c_speed => i2c_speed - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - START_IN => sendbyte_seq_start, - BYTE_IN => sendbyte_byte, - SEQUENCE_DONE_OUT => sendbyte_done, - SDA_OUT => sda_sendbyte, - SCL_OUT => scl_sendbyte, - SDA_IN => sda, - ACK_OUT => sendbyte_ack - ); - - -- Debug Line - DEBUG_OUT(0) <= sda_o; - DEBUG_OUT(1) <= scl_o; - DEBUG_OUT(2) <= i2c_start; - DEBUG_OUT(3) <= wait_timer_done; - DEBUG_OUT(7 downto 4) <= i2c_error; - - DEBUG_OUT(15 downto 8) <= (others => '0'); - - -- Sync I2C Lines - sda_i <= SDA_INOUT; - scl_i <= SCL_INOUT; - - PROC_I2C_LINES_SYNC: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - sda_x <= '1'; - sda <= '1'; - - scl_x <= '1'; - scl <= '1'; - else - sda_x <= sda_i; - sda <= sda_x; - - scl_x <= scl_i; - scl <= scl_x; - end if; - end if; - end process PROC_I2C_LINES_SYNC; - - PROC_I2C_MASTER: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - sda_o <= '1'; - scl_o <= '1'; - wait_timer_init <= (others => '0'); - bit_ctr <= (others => '0'); - i2c_ack <= '0'; - i2c_error <= (others => '0'); - startstop_select <= '0'; - startstop_seq_start <= '0'; - STATE <= S_IDLE; - else - sda_o <= '1'; - scl_o <= '1'; - wait_timer_init <= (others => '0'); - startstop_select <= '0'; - startstop_seq_start <= '0'; - case STATE is - when S_IDLE => - if (i2c_start = '1') then - STATE <= S_START; - else - STATE <= S_IDLE; - end if; - - -- I2C START Sequence - when S_START => - i2c_ack <= '0'; - startstop_select <= '1'; - startstop_seq_start <= '1'; - STATE <= S_START_WAIT; - - when S_START_WAIT => - if (startstop_done = '0') then - STATE <= S_START_WAIT; - else - STATE <= S_SEND_BYTE; - end if; - - -- I2C Send byte - when S_SEND_BYTE => - bit_ctr <= x"7"; - sda_o <= '0'; - scl_o <= '0'; - i2c_byte(7 downto 1) <= i2c_chipid; - i2c_byte(0) <= i2c_rw_bit; - wait_timer_init <= i2c_speed srl 2; - STATE <= S_SET_SDA; - - when S_SET_SDA => - sda_o <= i2c_byte(7); - scl_o <= '0'; - if (wait_timer_done = '0') then - STATE <= S_SET_SDA; - else - wait_timer_init <= i2c_speed srl 1; - STATE <= S_SET_SCL; - end if; - - when S_SET_SCL => - sda_o <= i2c_byte(7); - if (wait_timer_done = '0') then - STATE <= S_SET_SCL; - else - wait_timer_init <= i2c_speed srl 2; - STATE <= S_UNSET_SCL; - end if; - - when S_UNSET_SCL => - sda_o <= i2c_byte(7); - scl_o <= '0'; - if (wait_timer_done = '0') then - STATE <= S_UNSET_SCL; - else - STATE <= S_NEXT_BIT; - end if; - - when S_NEXT_BIT => - sda_o <= i2c_byte(7); - scl_o <= '0'; - if (bit_ctr > 0) then - bit_ctr <= bit_ctr - 1; - i2c_byte <= i2c_byte sll 1; - wait_timer_init <= i2c_speed srl 2; - STATE <= S_SET_SDA; - else - wait_timer_init <= i2c_speed srl 2; - STATE <= S_GET_ACK; - end if; - - -- I2C Check ACK Sequence - when S_GET_ACK => - scl_o <= '0'; - if (wait_timer_done = '0') then - STATE <= S_GET_ACK; - else - wait_timer_init <= i2c_speed srl 2; - STATE <= S_ACK_SET_SCL; - end if; - - when S_ACK_SET_SCL => - if (wait_timer_done = '0') then - STATE <= S_ACK_SET_SCL; - else - STATE <= S_STORE_ACK; - end if; - - when S_STORE_ACK => - i2c_ack <= sda; - wait_timer_init <= i2c_speed srl 2; - STATE <= S_ACK_UNSET_SCL; - - when S_ACK_UNSET_SCL => - scl_o <= '0'; - if (wait_timer_done = '0') then - STATE <= S_ACK_UNSET_SCL; - else - STATE <= S_VERIFY_ACK; - end if; - - when S_VERIFY_ACK => - scl_o <= '0'; - if (i2c_ack = '0') then - STATE <= S_STOP; - else - STATE <= S_ACK_ERROR; - end if; - - when S_ACK_ERROR => - scl_o <= '0'; - i2c_error(1) <= '1'; - STATE <= S_STOP; - - -- I2C STOP Sequence - when S_STOP => - startstop_select <= '0'; - startstop_seq_start <= '1'; - STATE <= S_STOP_WAIT; - - when S_STOP_WAIT => - if (startstop_done = '0') then - STATE <= S_STOP_WAIT; - else - STATE <= S_IDLE; - end if; - - end case; - - end if; - end if; - end process PROC_I2C_MASTER; - - ----------------------------------------------------------------------------- - -- TRBNet Slave Bus - ----------------------------------------------------------------------------- - - PROC_SLAVE_BUS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - reg_data <= x"affeaffe"; - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_ack_o <= '0'; - i2c_start <= '0'; - else - slv_ack_o <= '1'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - slv_data_out_o <= (others => '0'); - i2c_start <= '0'; - - if (SLV_WRITE_IN = '1') then - i2c_chipid <= SLV_DATA_IN(6 downto 0); - i2c_rw_bit <= SLV_DATA_IN(7); - i2c_start <= '1'; - elsif (SLV_READ_IN = '1') then - slv_data_out_o <= reg_data; - - else - slv_ack_o <= '0'; - end if; - end if; - end if; - end process PROC_SLAVE_BUS; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - -- I2c Outputs - SDA_INOUT <= '0' when (sda_o = '0' or sda_startstop = '0') else 'Z'; - SCL_INOUT <= '0' when (scl_o = '0' or scl_startstop = '0') else 'Z'; - - -- Slave Bus - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - -end Behavioral;