From: Jan Michel <j.michel@gsi.de>
Date: Tue, 24 Jan 2017 17:08:40 +0000 (+0100)
Subject: Update threshold FPGA code
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0cf271c1ef7ddeca4f043381c9566e73bcd8d2c5;p=dirich.git

Update threshold FPGA code
---

0cf271c1ef7ddeca4f043381c9566e73bcd8d2c5
diff --cc thresholds/thresholds.prj
index 5c90a7c,34f9f15..0bb55f3
--- a/thresholds/thresholds.prj
+++ b/thresholds/thresholds.prj
@@@ -8,16 -8,14 +8,14 @@@
  
  #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
  add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
- add_file -vhdl -lib work "../../logicbox/code/uart_sctrl.vhd"
+ add_file -vhdl -lib work "../../dirich/code/spi_slave.vhd"
  add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd"
 -add_file -vhdl -lib work "../../mdcfee/code/pwm.vhd"
 +add_file -vhdl -lib work "../code/pwm_machxo.vhd"
- add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
- add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
  
- add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
- add_file -vhdl -lib work "../../logicbox/cores/efb.vhd"
- add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v"
- add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v"
+ #add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
+ #add_file -vhdl -lib work "../../logicbox/cores/efb.vhd"
+ #add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v"
+ #add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v"
  
  add_file -vhdl -lib work "thresholds.vhd"
  
diff --cc thresholds/thresholds.vhd
index 4bac299,f219a07..b0de791
--- a/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@@ -10,14 -10,15 +10,12 @@@ use work.trb_net_std.all
  
  entity thresholds is
    port(
 -    --CLK    : in  std_logic;
 -  
 +    ID     : in  std_logic;
      OUTPUT : out std_logic_vector(15 downto 0);
-     TX_IN  : in  std_logic;
-     RX_OUT : out std_logic
- --     MISO_OUT : out std_logic;
- --     MOSI_IN  : in  std_logic;
- --     SCLK_IN  : in  std_logic;
- --     CS_IN    : in  std_logic
+     MISO_OUT : out std_logic;
+     MOSI_IN  : in  std_logic;
+     SCLK_IN  : in  std_logic;
 -    CS_IN    : in  std_logic;
 -    
 -    LED      : out std_logic_vector(7 downto 0)
++    CS_IN    : in  std_logic    
      );
  end entity;
  
@@@ -57,9 -58,8 +55,10 @@@ architecture arch of thresholds i
    signal flash_go      : std_logic;
    signal flash_busy    : std_logic;
    signal flash_err     : std_logic;
 -  
 +
 +  signal compensate_i  : signed(15 downto 0);
 +  signal pwm_i         : std_logic_vector(15 downto 0);
+   signal dummy_register : std_logic_vector(15 downto 0);
  
    component OSCH
      generic (NOM_FREQ: string := "33.25");
@@@ -135,20 -133,24 +132,23 @@@ PROC_REGS : process begi
    pwm_write_i<= '0';
    if bus_read = '1' then
      bus_ready <= '1';
-     case uart_addr is
+     case spi_addr is
 +      when x"10" => uart_tx_data <= std_logic_vector(compensate_i);
-       when x"ee" => uart_tx_data <= sed_debug;
+       when x"ee" => spi_tx_data <= sed_debug(15 downto 0);
+       when x"ef" => spi_tx_data <= sed_debug(31 downto 16);
 - 
+       when x"e4" => spi_tx_data <= dummy_register;
 -      
      end case;
    elsif bus_write = '1' then
-     if uart_addr < x"10" then
-       pwm_data_i <= uart_rx_data(15 downto 0);
-       pwm_addr_i <= uart_addr(4 downto 0);
+     if spi_addr < x"10" then
+       pwm_data_i <= spi_rx_data(15 downto 0);
+       pwm_addr_i <= spi_addr(4 downto 0);
        pwm_write_i<= '1';
      else
-       case uart_addr is
- --         when x"10" => reg <= uart_rx_data;
+       case spi_addr is
 ---         when x"10" => reg <= spi_rx_data;
 +        when x"10" => compensate_i <= signed(uart_rx_data(15 downto 0);
 +        when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);
+         when x"ee" => controlsed_i <= spi_rx_data(3 downto 0);
 -        
+         when x"e4" => dummy_register <= spi_rx_data ;
        end case;
      end if;  
    end if;