From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Fri, 6 Mar 2015 14:29:21 +0000 (+0100)
Subject: Try with 64 MHz, 80 seems a little bit unstable on ADC init
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0cf5b53d3378aa76ac2149c4b7745191ad389e9d;p=trb3.git

Try with 64 MHz, 80 seems a little bit unstable on ADC init
---

diff --git a/ADC/config.vhd b/ADC/config.vhd
index 99c0258..9204326 100644
--- a/ADC/config.vhd
+++ b/ADC/config.vhd
@@ -26,11 +26,11 @@ package config is
     constant INIT_ADDRESS           : std_logic_vector := x"F30a";
     constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4b";
    
---ADC sampling frequency: 40 or 80 MHz supported
+--ADC sampling frequency: 40, 64 or 80 MHz supported
 --note that not all READOUT_MODEs will lead to timing-error free designs
 --the READOUT_MODE_PSA mode is usually only working with 40MHz
 --the READOUT_MODE_CFD mode is more robust against clock domain crossing issues 
-    constant ADC_SAMPLING_RATE      : integer := 80;
+    constant ADC_SAMPLING_RATE      : integer := 64;
     
 --These are currently used for the included features table only
     constant ADC_BASELINE_LOGIC     : integer := c_YES;
diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index 5c5a198..50f71e1 100644
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -102,6 +102,22 @@ begin
       );
   end generate;
 
+  gen_64MHz : if ADC_SAMPLING_RATE = 64 generate
+    THE_ADC_REF : entity work.pll_in200_out64
+      port map(
+        CLK   => CLK_ADCRAW,
+        CLKOP => clk_adc,
+        LOCK  => open
+      );
+    THE_ADC_PLL_0 : entity work.pll_adc10bit_64
+
+      port map(
+        CLK   => CLK_ADCRAW,
+        CLKOP => clk_adcfast_i,
+        LOCK  => open
+      );
+  end generate;
+
   restart_i <= RESTART_IN when rising_edge(clk_data);
 
   gen_7 : if NUM_DEVICES = 7 generate
diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj
index 4903b36..3c98e45 100644
--- a/ADC/trb3_periph_adc.prj
+++ b/ADC/trb3_periph_adc.prj
@@ -142,8 +142,10 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v
 
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out40.vhd"
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out64.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out80.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd"
+add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_64.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_80.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"