From: Thomas Gessler Date: Sat, 12 Sep 2020 12:46:45 +0000 (+0200) Subject: hub_test: Remove bd/ directory X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0d056a0cc8ab304b5bbfbda2a7f945ae9d12a967;p=cri.git hub_test: Remove bd/ directory It is apparently sufficient to track the .bd file. --- diff --git a/hub_test/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci b/hub_test/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci deleted file mode 100644 index 0be1902..0000000 --- a/hub_test/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci +++ /dev/null @@ -1,150 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_axi_gpio_0_0 - - - 1 - 9 - 0 - 0 - 0 - design_1_Clk - 32 - 100000000 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 2 - 1 - 2 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - design_1_Clk - 100000000 - 0 - 0 - 0.000 - 0 - 0 - 0 - 1 - 1 - 0xFFFFFFFF - 0xFFFFFFFF - kintexu - 24 - 24 - 0 - 1 - 0xFFFFFFFF - 0xFFFFFFFF - 0 - 0 - 1 - 1 - 0xFFFFFFFF - 0xFFFFFFFF - 24 - 24 - 0 - 1 - 0xFFFFFFFF - 0xFFFFFFFF - design_1_axi_gpio_0_0 - Custom - Custom - false - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Integrator - 23 - TRUE - . - - ../../ipshared - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xml b/hub_test/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xml deleted file mode 100644 index 194cd35..0000000 --- a/hub_test/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xml +++ /dev/null @@ -1,1748 +0,0 @@ - - - xilinx.com - customized_ip - design_1_axi_gpio_0_0 - 1.0 - - - S_AXI - S_AXI - - - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 9 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 2 - - - none - - - - - NUM_WRITE_OUTSTANDING - 2 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXI_ACLK - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - S_AXI - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXI_ARESETN - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - IP2INTC_IRQ - IP2Intc_irq - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - GPIO - GPIO - - - - - - - TRI_I - - - gpio_io_i - - - - - TRI_O - - - gpio_io_o - - - - - TRI_T - - - gpio_io_t - - - - - - BOARD.ASSOCIATED_PARAM - GPIO_BOARD_INTERFACE - - - - required - - - - - - - - - true - - - - - - GPIO2 - GPIO2 - - - - - - - TRI_I - - - gpio2_io_i - - - - - TRI_O - - - gpio2_io_o - - - - - TRI_T - - - gpio2_io_t - - - - - - BOARD.ASSOCIATED_PARAM - GPIO2_BOARD_INTERFACE - - - - required - - - - - - - - - true - - - - - - - - S_AXI - S_AXI_MEM - Memory Map for S_AXI - - Reg - Reg - Register Block - 0 - 4096 - 32 - register - read-write - - GPIO_DATA - Channel_1_GPIO_DATA - Channel-1 AXI GPIO Data register - 0x0 - 24 - true - read-write - - 0x0 - - - Channel_1_GPIO_DATA - Channel_1_GPIO_DATA - AXI GPIO Data Register. -For each I/O bit programmed as input - R - Reads value on the input pin. - W - No effect. -For each I/O bit programmed as output - R - Reads value on GPIO_O pins - W - Writes value to the corresponding AXI GPIO - data register bit and output pin - - 0 - 24 - true - read-write - - 0 - 0 - - false - - - - GPIO_TRI - Channel_1_GPIO_TRI - Channel-1 AXI GPIO 3-State Control register - 0x4 - 24 - true - read-write - - 0x0 - - - Channel_1_GPIO_TRI - Channel_1_GPIO_DATA - AXI GPIO 3-State Control Register -Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input - - 0 - 24 - true - read-write - - 0 - 0 - - false - - - - GPIO2_DATA - Channel_2_GPIO_DATA - Channel-2 AXI GPIO Data register - 0x8 - 24 - true - read-write - - 0x0 - - - Channel_2_GPIO_DATA - Channel_2_GPIO_DATA - AXI GPIO Data Register. -For each I/O bit programmed as input - R - Reads value on the input pin. - W - No effect. -For each I/O bit programmed as output - R - Reads value on GPIO_O pins - W - Writes value to the corresponding AXI GPIO - data register bit and output pin - - 0 - 24 - true - read-write - - 0 - 0 - - false - - - - GPIO2_TRI - Channel_2_GPIO_TRI - Channel-2 AXI GPIO 3-State Control register - 0xC - 24 - true - read-write - - 0x0 - - - Channel_2_GPIO_TRI - Channel_2_GPIO_DATA - AXI GPIO 3-State Control Register -Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input - - 0 - 24 - true - read-write - - 0 - 0 - - false - - - - GIER - Global_Interrupt_Enable register - Global_Interrupt_Enable register - 0x11C - 32 - true - read-write - - 0x0 - - - Global_Interrupt_Enable - Global_Interrupt_Enable - Master enable for the device interrupt output - 0 - Disabled - 1 - Enabled - - 31 - 1 - true - read-write - - 0 - 0 - - false - - - - IP_IER - IP Interrupt Enable register - IP Interrupt Enable register - 0x128 - 32 - true - read-write - - 0x0 - - - Channel_1_Interrupt_Enable - Channel_1_Interrupt_Enable - Enable Channel 1 Interrupt - 0 - Disabled (masked) - 1 - Enabled - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - Channel_2_Interrupt_Enable - Channel_2_Interrupt_Enable - Enable Channel 2 Interrupt - 0 - Disabled (masked) - 1 - Enabled - - 1 - 1 - true - read-write - - 0 - 0 - - false - - - - IP_ISR - IP Interrupt Status register - IP Interrupt Status register - 0x120 - 32 - true - read-write - - 0x0 - - - Channel_1_Interrupt_Status - Channel_1_Interrupt_Status - Channel 1 Interrupt Status - 0 - No Channel 1 input interrupt - 1 - Channel 1 input interrupt - - 0 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - Channel_2_Interrupt_Status - Channel_2_Interrupt_Status - Channel 2 Interrupt Status - 0 - No Channel 2 input interrupt - 1 - Channel 2 input interrupt - - 1 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - - - - - - - s_axi_aclk - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_aresetn - - in - - - std_logic - dummy_view - - - - 1 - - - - - s_axi_awaddr - - in - - 8 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - s_axi_awvalid - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_awready - - out - - - std_logic - dummy_view - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - s_axi_wvalid - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_wready - - out - - - std_logic - dummy_view - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_bvalid - - out - - - std_logic - dummy_view - - - - - - s_axi_bready - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_araddr - - in - - 8 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - s_axi_arvalid - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_arready - - out - - - std_logic - dummy_view - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_rvalid - - out - - - std_logic - dummy_view - - - - - - s_axi_rready - - in - - - std_logic - dummy_view - - - - 0 - - - - - ip2intc_irpt - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - gpio_io_i - - in - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - gpio_io_o - - out - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - - - - true - - - - - - gpio_io_t - - out - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - gpio2_io_i - - in - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - gpio2_io_o - - out - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - - - - true - - - - - - gpio2_io_t - - out - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - - - C_FAMILY - kintexu - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 9 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_GPIO_WIDTH - GPIO Width - 24 - - - C_GPIO2_WIDTH - GPIO2 Data Width - 24 - - - C_ALL_INPUTS - All Inputs - 0 - - - C_ALL_INPUTS_2 - All Inputs - 0 - - - C_ALL_OUTPUTS - All Outputs - 1 - - - C_ALL_OUTPUTS_2 - All Outputs - 1 - - - C_INTERRUPT_PRESENT - Enable Interrupt - 0 - - - C_DOUT_DEFAULT - Default DOUT value - 0xFFFFFFFF - - - C_TRI_DEFAULT - Default tri state value - 0xFFFFFFFF - - - C_IS_DUAL - Enable Dual channel - 1 - - - C_DOUT_DEFAULT_2 - Default DOUT value2 - 0xFFFFFFFF - - - C_TRI_DEFAULT_2 - Default tri state value2 - 0xFFFFFFFF - - - - - - choice_list_ac75ef1e - Custom - - - choice_pairs_4873554b - 0 - 1 - - - Advanced eXtensible Interface General Purpose Input/Output (AXI GPIO) core provides a general purpose input/output interface to the AXI interface. - - - C_TRI_DEFAULT - Default Tri State Value - 0xFFFFFFFF - - - - false - - - - - - C_GPIO_WIDTH - GPIO Width - 24 - - - - true - - - - - - C_GPIO2_WIDTH - GPIO Width - 24 - - - - true - - - - - - C_IS_DUAL - Enable Dual Channel - 1 - - - - true - - - - - - C_ALL_INPUTS - All Inputs - 0 - - - - true - - - - - - C_TRI_DEFAULT_2 - Default Tri State Value - 0xFFFFFFFF - - - - false - - - - - - C_DOUT_DEFAULT_2 - Default Output Value - 0xFFFFFFFF - - - - true - - - - - - C_DOUT_DEFAULT - Default Output Value - 0xFFFFFFFF - - - - true - - - - - - C_ALL_INPUTS_2 - All Inputs - 0 - - - - true - - - - - - C_INTERRUPT_PRESENT - Enable Interrupt - 0 - - - - true - - - - - - Component_Name - design_1_axi_gpio_0_0 - - - - true - - - - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - - true - - - - - - GPIO_BOARD_INTERFACE - Custom - - - - true - - - - - - GPIO2_BOARD_INTERFACE - Custom - - - - true - - - - - - C_ALL_OUTPUTS - All Outputs - 1 - - - - true - - - - - - C_ALL_OUTPUTS_2 - All Outputs - 1 - - - - true - - - - - - - - AXI GPIO - 23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci b/hub_test/bd/design_1/ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci deleted file mode 100644 index fb97f51..0000000 --- a/hub_test/bd/design_1/ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci +++ /dev/null @@ -1,148 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_axi_gpio_0_1 - - - 1 - 9 - 0 - 0 - 0 - design_1_Clk - 32 - 100000000 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - design_1_Clk - 100000000 - 0 - 0 - 0.000 - 0 - 1 - 1 - 0 - 0 - 0x00000000 - 0x00000000 - kintexu - 24 - 24 - 0 - 1 - 0xFFFFFFFF - 0xFFFFFFFF - 1 - 1 - 0 - 0 - 0x00000000 - 0x00000000 - 24 - 24 - 0 - 1 - 0xFFFFFFFF - 0xFFFFFFFF - design_1_axi_gpio_0_1 - Custom - Custom - false - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Integrator - 23 - TRUE - . - - ../../ipshared - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xml b/hub_test/bd/design_1/ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xml deleted file mode 100644 index dbc92e5..0000000 --- a/hub_test/bd/design_1/ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xml +++ /dev/null @@ -1,1746 +0,0 @@ - - - xilinx.com - customized_ip - design_1_axi_gpio_0_1 - 1.0 - - - S_AXI - S_AXI - - - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 9 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXI_ACLK - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - S_AXI - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXI_ARESETN - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - IP2INTC_IRQ - IP2Intc_irq - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - GPIO - GPIO - - - - - - - TRI_I - - - gpio_io_i - - - - - TRI_O - - - gpio_io_o - - - - - TRI_T - - - gpio_io_t - - - - - - BOARD.ASSOCIATED_PARAM - GPIO_BOARD_INTERFACE - - - - required - - - - - - - - - true - - - - - - GPIO2 - GPIO2 - - - - - - - TRI_I - - - gpio2_io_i - - - - - TRI_O - - - gpio2_io_o - - - - - TRI_T - - - gpio2_io_t - - - - - - BOARD.ASSOCIATED_PARAM - GPIO2_BOARD_INTERFACE - - - - required - - - - - - - - - true - - - - - - - - S_AXI - S_AXI_MEM - Memory Map for S_AXI - - Reg - Reg - Register Block - 0 - 4096 - 32 - register - read-write - - GPIO_DATA - Channel_1_GPIO_DATA - Channel-1 AXI GPIO Data register - 0x0 - 24 - true - read-write - - 0x0 - - - Channel_1_GPIO_DATA - Channel_1_GPIO_DATA - AXI GPIO Data Register. -For each I/O bit programmed as input - R - Reads value on the input pin. - W - No effect. -For each I/O bit programmed as output - R - Reads value on GPIO_O pins - W - Writes value to the corresponding AXI GPIO - data register bit and output pin - - 0 - 24 - true - read-write - - 0 - 0 - - false - - - - GPIO_TRI - Channel_1_GPIO_TRI - Channel-1 AXI GPIO 3-State Control register - 0x4 - 24 - true - read-write - - 0x0 - - - Channel_1_GPIO_TRI - Channel_1_GPIO_DATA - AXI GPIO 3-State Control Register -Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input - - 0 - 24 - true - read-write - - 0 - 0 - - false - - - - GPIO2_DATA - Channel_2_GPIO_DATA - Channel-2 AXI GPIO Data register - 0x8 - 24 - true - read-write - - 0x0 - - - Channel_2_GPIO_DATA - Channel_2_GPIO_DATA - AXI GPIO Data Register. -For each I/O bit programmed as input - R - Reads value on the input pin. - W - No effect. -For each I/O bit programmed as output - R - Reads value on GPIO_O pins - W - Writes value to the corresponding AXI GPIO - data register bit and output pin - - 0 - 24 - true - read-write - - 0 - 0 - - false - - - - GPIO2_TRI - Channel_2_GPIO_TRI - Channel-2 AXI GPIO 3-State Control register - 0xC - 24 - true - read-write - - 0x0 - - - Channel_2_GPIO_TRI - Channel_2_GPIO_DATA - AXI GPIO 3-State Control Register -Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input - - 0 - 24 - true - read-write - - 0 - 0 - - false - - - - GIER - Global_Interrupt_Enable register - Global_Interrupt_Enable register - 0x11C - 32 - true - read-write - - 0x0 - - - Global_Interrupt_Enable - Global_Interrupt_Enable - Master enable for the device interrupt output - 0 - Disabled - 1 - Enabled - - 31 - 1 - true - read-write - - 0 - 0 - - false - - - - IP_IER - IP Interrupt Enable register - IP Interrupt Enable register - 0x128 - 32 - true - read-write - - 0x0 - - - Channel_1_Interrupt_Enable - Channel_1_Interrupt_Enable - Enable Channel 1 Interrupt - 0 - Disabled (masked) - 1 - Enabled - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - Channel_2_Interrupt_Enable - Channel_2_Interrupt_Enable - Enable Channel 2 Interrupt - 0 - Disabled (masked) - 1 - Enabled - - 1 - 1 - true - read-write - - 0 - 0 - - false - - - - IP_ISR - IP Interrupt Status register - IP Interrupt Status register - 0x120 - 32 - true - read-write - - 0x0 - - - Channel_1_Interrupt_Status - Channel_1_Interrupt_Status - Channel 1 Interrupt Status - 0 - No Channel 1 input interrupt - 1 - Channel 1 input interrupt - - 0 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - Channel_2_Interrupt_Status - Channel_2_Interrupt_Status - Channel 2 Interrupt Status - 0 - No Channel 2 input interrupt - 1 - Channel 2 input interrupt - - 1 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - - - - - - - s_axi_aclk - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_aresetn - - in - - - std_logic - dummy_view - - - - 1 - - - - - s_axi_awaddr - - in - - 8 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - s_axi_awvalid - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_awready - - out - - - std_logic - dummy_view - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - s_axi_wvalid - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_wready - - out - - - std_logic - dummy_view - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_bvalid - - out - - - std_logic - dummy_view - - - - - - s_axi_bready - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_araddr - - in - - 8 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - s_axi_arvalid - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_arready - - out - - - std_logic - dummy_view - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_rvalid - - out - - - std_logic - dummy_view - - - - - - s_axi_rready - - in - - - std_logic - dummy_view - - - - 0 - - - - - ip2intc_irpt - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - gpio_io_i - - in - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - true - - - - - - gpio_io_o - - out - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - gpio_io_t - - out - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - gpio2_io_i - - in - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - true - - - - - - gpio2_io_o - - out - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - gpio2_io_t - - out - - 23 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - - - C_FAMILY - kintexu - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 9 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_GPIO_WIDTH - GPIO Width - 24 - - - C_GPIO2_WIDTH - GPIO2 Data Width - 24 - - - C_ALL_INPUTS - All Inputs - 1 - - - C_ALL_INPUTS_2 - All Inputs - 1 - - - C_ALL_OUTPUTS - All Outputs - 0 - - - C_ALL_OUTPUTS_2 - All Outputs - 0 - - - C_INTERRUPT_PRESENT - Enable Interrupt - 0 - - - C_DOUT_DEFAULT - Default DOUT value - 0x00000000 - - - C_TRI_DEFAULT - Default tri state value - 0xFFFFFFFF - - - C_IS_DUAL - Enable Dual channel - 1 - - - C_DOUT_DEFAULT_2 - Default DOUT value2 - 0x00000000 - - - C_TRI_DEFAULT_2 - Default tri state value2 - 0xFFFFFFFF - - - - - - choice_list_ac75ef1e - Custom - - - choice_pairs_4873554b - 0 - 1 - - - Advanced eXtensible Interface General Purpose Input/Output (AXI GPIO) core provides a general purpose input/output interface to the AXI interface. - - - C_TRI_DEFAULT - Default Tri State Value - 0xFFFFFFFF - - - - false - - - - - - C_GPIO_WIDTH - GPIO Width - 24 - - - - true - - - - - - C_GPIO2_WIDTH - GPIO Width - 24 - - - - true - - - - - - C_IS_DUAL - Enable Dual Channel - 1 - - - - true - - - - - - C_ALL_INPUTS - All Inputs - 1 - - - - true - - - - - - C_TRI_DEFAULT_2 - Default Tri State Value - 0xFFFFFFFF - - - - false - - - - - - C_DOUT_DEFAULT_2 - Default Output Value - 0x00000000 - - - - false - - - - - - C_DOUT_DEFAULT - Default Output Value - 0x00000000 - - - - false - - - - - - C_ALL_INPUTS_2 - All Inputs - 1 - - - - true - - - - - - C_INTERRUPT_PRESENT - Enable Interrupt - 0 - - - - true - - - - - - Component_Name - design_1_axi_gpio_0_1 - - - - true - - - - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - - true - - - - - - GPIO_BOARD_INTERFACE - Custom - - - - true - - - - - - GPIO2_BOARD_INTERFACE - Custom - - - - true - - - - - - C_ALL_OUTPUTS - All Outputs - 0 - - - - false - - - - - - C_ALL_OUTPUTS_2 - All Outputs - 0 - - - - false - - - - - - - - AXI GPIO - 23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_axi_iic_0_0/design_1_axi_iic_0_0.xci b/hub_test/bd/design_1/ip/design_1_axi_iic_0_0/design_1_axi_iic_0_0.xci deleted file mode 100644 index 6241098..0000000 --- a/hub_test/bd/design_1/ip/design_1_axi_iic_0_0/design_1_axi_iic_0_0.xci +++ /dev/null @@ -1,142 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_axi_iic_0_0 - - - 1 - 9 - 0 - 0 - 0 - design_1_Clk - 32 - 100000000 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 2 - 1 - 2 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - design_1_Clk - 100000000 - 0 - 0 - 0.000 - 0 - 0x00 - 0 - kintexu - 1 - 100000 - 0 - 0 - 1 - 0 - 100000000 - 0 - 32 - 100.0 - 0x00 - 0 - 1 - 0 - 0 - 1 - 0 - 32 - design_1_axi_iic_0_0 - Custom - 100 - 7_bit - false - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Integrator - 24 - TRUE - . - - ../../ipshared - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_axi_iic_0_0/design_1_axi_iic_0_0.xml b/hub_test/bd/design_1/ip/design_1_axi_iic_0_0/design_1_axi_iic_0_0.xml deleted file mode 100644 index b12193d..0000000 --- a/hub_test/bd/design_1/ip/design_1_axi_iic_0_0/design_1_axi_iic_0_0.xml +++ /dev/null @@ -1,2385 +0,0 @@ - - - xilinx.com - customized_ip - design_1_axi_iic_0_0 - 1.0 - - - S_AXI - S_AXI - AXI4-Lite slave - - - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 9 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 2 - - - none - - - - - NUM_WRITE_OUTSTANDING - 2 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXI_ACLK - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - S_AXI - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXI_ARESETN - s_axi_aresetn - s_axi_aresetn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - INTERRUPT - Interrupt - Slave Interrupt to INTC - - - - - - - INTERRUPT - - - iic2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - PortWidth - 1 - - - none - - - - - - - IIC - IIC - IIC - - - - - - - SCL_I - - - scl_i - - - - - SCL_O - - - scl_o - - - - - SCL_T - - - scl_t - - - - - SDA_I - - - sda_i - - - - - SDA_O - - - sda_o - - - - - SDA_T - - - sda_t - - - - - - BOARD.ASSOCIATED_PARAM - IIC_BOARD_INTERFACE - - - - - - - S_AXI - S_AXI_MEM - Memory Map for S_AXI - - Reg - Reg - Register Block - 0 - 4096 - 32 - register - read-write - - GIE - GIE - Global Interrupt Enable Register - 0x1c - 32 - read-write - - 0x0 - - - GIE - GIE - Global Interrupt Enable -0 - All Interrupts disabled; no interrupt (even if unmasked in IER) possible from AXI IIC core -1 - Unmasked AXI IIC core interrupts are passed to processor - - 31 - 1 - true - read-write - - 0 - 0 - - false - - - - ISR - ISR - Interrupt Status Register - 0x020 - 32 - read-write - - 0xd0 - - - int0 - int0 - Interrupt0 - Arbitration Lost - - 0 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - int1 - int1 - Interrupt1 - Transmit Error/Slave Transmit Complete - - 1 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - int2 - int2 - Interrupt2 - Transmit FIFO Empty - - 2 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - int3 - int3 - Interrupt3 - Recieve FIFO FULL - - 3 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - int4 - int4 - Interrupt4 - IIC Bus is Not Busy - - 4 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - int5 - int5 - Interrupt5 - Addressed As Slave - - 5 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - int6 - int6 - Interrupt6 - Not Addessed As Slave - - 6 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - int7 - int7 - Interrupt7 - Transmit FIFO Half Empty - - 7 - 1 - true - read-write - oneToToggle - - 0 - 0 - - false - - - - IER - IER - Interrupt Enable Register - 0x028 - 32 - read-write - - 0x0 - - - int0 - int0 - Interrupt0 - Arbitration Lost - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - int1 - int1 - Interrupt1 - Transmit Error/Slave Transmit Complete - - 1 - 1 - true - read-write - - 0 - 0 - - false - - - int2 - int2 - Interrupt2 - Transmit FIFO Empty - - 2 - 1 - true - read-write - - 0 - 0 - - false - - - int3 - int3 - Interrupt3 - Recieve FIFO FULL - - 3 - 1 - true - read-write - - 0 - 0 - - false - - - int4 - int4 - Interrupt4 - IIC Bus is Not Busy - - 4 - 1 - true - read-write - - 0 - 0 - - false - - - int5 - int5 - Interrupt5 - Addressed As Slave - - 5 - 1 - true - read-write - - 0 - 0 - - false - - - int6 - int6 - Interrupt6 - Not Addessed As Slave - - 6 - 1 - true - read-write - - 0 - 0 - - false - - - int7 - int7 - Interrupt7 - Transmit FIFO Half Empty - - 7 - 1 - true - read-write - - 0 - 0 - - false - - - - SOFTR - SOFTR - Soft Reset Register - 0x040 - 32 - read-write - - 0x0 - - - RKEY - RKEY - Reset Key - Firmware must write a value of 0xA to this field to - cause a soft reset of the Interrupt registers of AXI IIC controller. - Writing any other value results in an AXI transaction - acknowledgement with SLVERR and no reset occurs. - - 0 - 4 - true - write-only - - 0 - 0 - - false - - - - CR - CR - Control Register - 0x100 - 32 - read-write - - 0x0 - - - EN - AXI IIC Enable - This bit must be set before any other CR bits have any effect -0 - resets and disables the AXI IIC controller but not the registers or FIFOs -1 - enables the AXI IIC controller - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - TX_FIFO_Reset - Transmit FIFO Reset - This bit must be set to flush the FIFO if either (a) arbitration is lost or (b) if a transmit error occurs -0 - transmit FIFO normal operation -1 - resets the transmit FIFO - - 1 - 1 - true - read-write - - 0 - 0 - - false - - - MSMS - Master/Slave Mode Select - When this bit is changed from 0 to 1, the -AXI IIC bus interface generates a START condition in master mode. When -this bit is cleared, a STOP condition is generated and the AXI IIC bus -interface switches to slave mode. When this bit is cleared by the -hardware, because arbitration for the bus has been lost, a STOP -condition is not generated - - 2 - 1 - true - read-write - - 0 - 0 - - false - - - TX - Transmit/Recieve Mode Select - This bit selects the direction of master/slave transfers. -0 - selects an AXI IIC receive -1 - selects an AXI IIC transmit - - 3 - 1 - true - read-write - - 0 - 0 - - false - - - TXAK - Transmit Acknowledgement - This bit specifies the value driven onto -the sda line during acknowledge cycles for both master and slave recievers. -0 - acknowledge -1 - not-acknowledge - - 4 - 1 - true - read-write - - 0 - 0 - - false - - - RSTA - Repeated Start - Writing a 1 to this bit generates a repeated START -condition on the bus if the AXI IIC bus interface is the current bus -master. Attempting a repeated START at the wrong time, if the bus is -owned by another master, results in a loss of arbitration. This bit is reset -when the repeated start occurs. This bit must be set prior to writing the -new address to the TX_FIFO or DTR - - 5 - 1 - true - read-write - - 0 - 0 - - false - - - GC_EN - General Call Enable - Setting this bit High allows the AXI IIC to respond to a general call address. -0 - General Call Disabled -1 - General Call Enabled - - 6 - 1 - true - read-write - - 0 - 0 - - false - - - - SR - SR - Status Register - 0x104 - 32 - read-only - - 0x0 - - - ABGC - Addressed By a General Call - This bit is set to 1 when another master has issued a general call and -the general call enable bit is set to 1, CR(6) = 1. - - 0 - 1 - true - read-only - - 0 - 0 - - false - - - AAS - Addressed As Slave - When the address on the IIC bus matches the slave address in the Address register (ADR), the IIC bus interface -is being addressed as a slave and switches to slave mode. If 10-bit addressing is selected this device only responds to a 10-bit -address or general call if enabled. This bit is cleared when a stop -condition is detected or a repeated start occurs. -0 - indicates not being addressed as a slave -1 - indicates being addressed as a slave - - 1 - 1 - true - read-only - - 0 - 0 - - false - - - BB - Bus Busy - This bit indicates the status of the IIC bus. This bit is set -when a START condition is detected and cleared when a STOP -condition is detected. -0 - indicates the bus is idle -1 - indicates the bus is busy - - 2 - 1 - true - read-only - - 0 - 0 - - false - - - ARW - Slave Read/Write - When the IIC bus interface has been addressed as a slave (AAS is set), -this bit indicates the value of the read/write bit sent by the master. -This bit is only valid when a complete transfer has occurred and -no other transfers have been initiated. -0 - indicates master writing to slave -1 - indicates master reading from slave - - 3 - 1 - true - read-only - - 0 - 0 - - false - - - TX_FIFO_Full - Transmit FIFO Full - This bit is set High when the transmit FIFO is full. - - 4 - 1 - true - read-only - - 0 - 0 - - false - - - RX_FIFO_Full - Recieve FUFO Full - This bit is set High when the receive FIFO is full. -This bit is set only when all 16 locations in the FIFO are full, -regardless of the compare value field of the RX_FIFO_PIRQ register. - - 5 - 1 - true - read-only - - 0 - 0 - - false - - - RX_FIFO_Empty - Receive FIFO empty - This is set High when the receive FIFO is empty. - - 6 - 1 - true - read-only - - 0 - 0 - - false - - - TX_FIFO_Empty - Transmit FIFO Empty - This is set High when the transmit FIFO is empty. - - 7 - 1 - true - read-only - - 0 - 0 - - false - - - - TX_FIFO - TX_FIFO - Transmit FIFO Register - 0x108 - 32 - write-only - - 0x0 - - - D7_D0 - AXI IIC Transmit Data - If the dynamic stop bit is used and the AXI IIC is a master receiver, -the value is the number of bytes to receive. - - 0 - 8 - true - write-only - - 0 - 0 - - false - - - Start - Start - The dynamic start bit can be used to send a start or repeated start sequence on the -IIC bus. A start sequence is generated if the MSMS = 0, a -repeated start sequence is generated if the MSMS = 1. - - 8 - 1 - true - write-only - - 0 - 0 - - false - - - Stop - Stop - The dynamic stop bit can be used to send an IIC stop -sequence on the IIC bus after the last byte has been transmitted or received. - - 9 - 1 - true - write-only - - 0 - 0 - - false - - - - RX_FIFO - RX_FIFO - Recieve FIFO Register - 0x10C - 32 - read-only - - 0x0 - - - D7_D0 - IIC Receive Data - IIC Receive Data - - 0 - 8 - true - read-only - - 0 - 0 - - false - - - - ADR - ADR - Slave Address Register - 0x110 - 32 - read-write - - 0x0 - - - Slave_Address - Slave Address - Address used by the IIC bus interface when in slave mode. - - 1 - 7 - true - read-write - - 0 - 0 - - false - - - - TX_FIFO_OCY - TX_FIFO_OCY - Transmit FIFO Occupency Register - 0x114 - 32 - read-only - - 0x0 - - - Occupancy_Value - Occupancy_Value - Bit[3] is the MSB. A binary value of 1001 indicates that -10 locations are full in the FIFO - - 0 - 4 - true - read-only - - 0 - 0 - - false - - - - RX_FIFO_OCY - RX_FIFO_OCY - Recieve FIFO Occupency Register - 0x118 - 32 - read-only - - 0x0 - - - Occupancy_Value - Occupancy_Value - Bit[3] is the MSB. A binary value of 1001 indicates that -10 locations are full in the FIFO - - 0 - 4 - true - read-only - - 0 - 0 - - false - - - - TEN_ADR - TEN_ADR - Slave Ten Bit Address Register - 0x11C - 32 - read-write - - 0x0 - - - MSB_of_Slave_Address - MSB_of_Slave_Address - Three MSBs of the 10-bit address used by the AXI IIC bus interface when in slave mode. - - 0 - 3 - true - read-write - - 0 - 0 - - false - - - - RX_FIFO_PIRQ - RX_FIFO_PIRQ - Recieve FIFO Programmable Depth Interrupt Register - 0x120 - 32 - read-write - - 0x0 - - - Compare_Value - Compare Value - Bit[3] is the MSB. A binary value of 1001 implies that when -10 locations in the receive FIFO are filled, the receive FIFO -interrupt is set. - - 0 - 4 - true - read-write - - 0 - 0 - - false - - - - GPO - GPO - General Purpose Output Register - 0x124 - 32 - read-write - - 0x0 - - - General_Purpose_Outputs - General Purpose Outputs - The LSB (Bit[0]) is the first bit populated - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - - TSUSTA - TSUSTA - Timing Parameter TSUSTA Register - 0x128 - 32 - read-write - - 0x0 - - - TSUSTA - TSUSTA - Setup time for a repeated START condition. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - TSUSTO - TSUSTO - Timing Parameter TSUSTO Register - 0x12C - 32 - read-write - - 0x0 - - - TSUSTO - TSUSTO - Setup time for a repeated STOP condition. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - THDSTA - THDSTA - Timing Parameter THDSTA Register - 0x130 - 32 - read-write - - 0x0 - - - THDSTA - THDSTA - Hold time for a repeated START condition. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - TSUDAT - TSUDAT - Timing Parameter TSUDAT Register - 0x134 - 32 - read-write - - 0x0 - - - TSUDAT - TSUDAT - Data Setup time - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - TBUF - TBUF - Timing Parameter TBUF Register - 0x138 - 32 - read-write - - 0x0 - - - TBUF - TBUF - Bus free time between a STOP and START condition - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - THIGH - THIGH - Timing Parameter THIGH Register - 0x13C - 32 - read-write - - 0x0 - - - THIGH - THIGH - High Period of the scl clock. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - TLOW - TLOW - Timing Parameter TLOW Register - 0x140 - 32 - read-write - - 0x0 - - - TLOW - TLOW - Low Period of scl clock. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - THDDAT - THDDAT - Timing Parameter THDDAT Register - 0x144 - 32 - read-write - - 0x0 - - - THDDAT - THDDAT - Data Hold time - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - - - - - s_axi_aclk - - in - - - std_logic - dummy_view - - - - - - s_axi_aresetn - - in - - - std_logic - dummy_view - - - - 0x1 - - - - - iic2intc_irpt - - out - - - std_logic - dummy_view - - - - - - s_axi_awaddr - - in - - 8 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_awvalid - - in - - - std_logic - dummy_view - - - - - - s_axi_awready - - out - - - std_logic - dummy_view - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_wvalid - - in - - - std_logic - dummy_view - - - - - - s_axi_wready - - out - - - std_logic - dummy_view - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_bvalid - - out - - - std_logic - dummy_view - - - - - - s_axi_bready - - in - - - std_logic - dummy_view - - - - - - s_axi_araddr - - in - - 8 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_arvalid - - in - - - std_logic - dummy_view - - - - - - s_axi_arready - - out - - - std_logic - dummy_view - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_rvalid - - out - - - std_logic - dummy_view - - - - - - s_axi_rready - - in - - - std_logic - dummy_view - - - - - - sda_i - - in - - - std_logic - dummy_view - - - - - - sda_o - - out - - - std_logic - dummy_view - - - - - - sda_t - - out - - - std_logic - dummy_view - - - - - - scl_i - - in - - - std_logic - dummy_view - - - - - - scl_o - - out - - - std_logic - dummy_view - - - - - - scl_t - - out - - - std_logic - dummy_view - - - - - - gpo - - out - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - - - - - C_FAMILY - kintexu - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 9 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_IIC_FREQ - C Iic Freq - 100000 - - - C_TEN_BIT_ADR - C Ten Bit Adr - 0 - - - C_GPO_WIDTH - General Purpose Output width - 1 - - - C_S_AXI_ACLK_FREQ_HZ - C S Axi Aclk Freq Hz - 100000000 - - - C_SCL_INERTIAL_DELAY - SCL Inertial delay filter value (in AXI clocks) - 0 - - - C_SDA_INERTIAL_DELAY - SDA Inertial delay value (in AXI clocks) - 0 - - - C_SDA_LEVEL - Serial Data Level - 1 - - - C_SMBUS_PMBUS_HOST - C Smbus Pmbus Host - 0 - - - C_DISABLE_SETUP_VIOLATION_CHECK - SDA setup check - 0 - - - C_STATIC_TIMING_REG_WIDTH - Fix Timing Register width - 0 - - - C_TIMING_REG_WIDTH - Timing Parameter Reg Width - 32 - - - C_DEFAULT_VALUE - Default GPO Port DOUT value - 0x00 - - - - - - choice_list_ac75ef1e - Custom - - - choice_pairs_897f2ba9 - 7_bit - 10_bit - - - AXI IIC controller - - - C_SDA_LEVEL - Active state of SDA - This parameter is used during transmit throttling when the AXI IIC acts as master transmitter. - 1 - - - - true - - - - - - Component_Name - design_1_axi_iic_0_0 - - - - true - - - - - - TEN_BIT_ADR - Address mode - This parameter enables or disables the 10-bit addressing mode. Logic resource savings result when 10-bit addressing is disabled - 7_bit - - - - true - - - - - - AXI_ACLK_FREQ_MHZ - AXI Clock Frequency (in MHz) - This parameter specifies (but does not set) the frequency of the AXI4-Lite interface. - 100.0 - - - - true - - - - - - C_GPO_WIDTH - General Purpose Output width - This parameter sets the width of the general purpose output vector. If the user does not connect anything to this port, then logic optimization removes any resources associated with it. - 1 - - - - true - - - - - - C_DEFAULT_VALUE - Default GPO Port Output Value - 0x00 - - - - true - - - - - - C_SCL_INERTIAL_DELAY - SCL Inertial delay (in AXI clocks) - This parameter specifies the number of S_AXI_ACLK cycles used to define the width of the pulse rejection on SCL signals - 0 - - - - true - - - - - - C_SDA_INERTIAL_DELAY - SDA Inertial delay (in AXI clocks) - This parameter specify the number of S_AXI_ACLK cycles used to define the width of the pulse rejection on SDA signals - 0 - - - - true - - - - - - IIC_FREQ_KHZ - SCL Clock Frequency (in KHz) - This parameter determines the approximate frequency of the master mode generated SCL clock signal (Hz) - 100 - - - - true - - - - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - - true - - - - - - IIC_BOARD_INTERFACE - IIC Board Interface - Custom - - - - true - - - - - - C_STATIC_TIMING_REG_WIDTH - 0 - - - C_TIMING_REG_WIDTH - 32 - - - C_DISABLE_SETUP_VIOLATION_CHECK - 0 - - - - - AXI IIC - 24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci b/hub_test/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci deleted file mode 100644 index 392a5f5..0000000 --- a/hub_test/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci +++ /dev/null @@ -1,130 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_axi_timer_0_0 - - - 1 - 5 - 0 - 0 - 0 - design_1_Clk - 32 - 100000000 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - design_1_Clk - 100000000 - 0 - 0 - 0.000 - 0 - 32 - kintexu - "1" - "1" - 0 - "1" - "1" - 32 - design_1_axi_timer_0_0 - Active_High - Active_High - Active_High - Active_High - 1 - 0 - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Integrator - 23 - TRUE - . - - ../../ipshared - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xml b/hub_test/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xml deleted file mode 100644 index d5b54ad..0000000 --- a/hub_test/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xml +++ /dev/null @@ -1,1683 +0,0 @@ - - - xilinx.com - customized_ip - design_1_axi_timer_0_0 - 1.0 - - - S_AXI - S_AXI - Lite interface - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 5 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXI_ACLK - s_axi_aclk - Axi Clock - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - S_AXI - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - clock frequency - specify frequency of the clock connected to port s_axi_aclk - 100000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - S_AXI_RST - s_axi_rst - AXI Reset - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - INTERRUPT - INTERRUPT - Interrupt - - - - - - - INTERRUPT - - - interrupt - - - - - - SENSITIVITY - LEVEL_HIGH - - - PortWidth - 1 - - - none - - - - - - - - - S_AXI - S_AXI_MEM - Memory Map for S_AXI - - Reg - Reg - Register Block - 0 - 512 - 32 - register - read-write - - TCSR0 - Timer 0 Control and Status Register - Timer 0 Control and Status Register - 0x0 - 32 - true - read-write - - 0x0 - - - MDT0 - Timer 0 Mode - Timer 0 Mode -0 - Timer mode is generate -1 - Timer mode is capture - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - UDT0 - Timer 0 Up/Down Count - Up/Down Count Timer 0 - 0 - Timer functions as up counter - 1 - Timer functions as down counter - - 1 - 1 - true - read-write - - 0 - 0 - - false - - - GENT0 - Generate Signal Timer 0 - Enable External Generate Signal Timer 0 - 0 - Disables external generate signal - 1 - Enables external generate signal - - 2 - 1 - true - read-write - - 0 - 0 - - false - - - CAPT0 - Capture Trigger Timer 0 - Enable External Capture Trigger Timer 0 - 0 - Disables external capture trigger - 1 - Enables external capture trigger - - 3 - 1 - true - read-write - - 0 - 0 - - false - - - ARHT0 - Auto Reload/Hold Timer 0 - Auto Reload/Hold Timer 0. -When the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. -In Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held. 0 = Hold counter or capture value. The TLR must be read before providing the external capture. 1 = Reload generate value or overwrite capture value - - 4 - 1 - true - read-write - - 0 - 0 - - false - - - LOAD0 - Load Timer 0 - Load Timer 0 0 = No load 1 = Loads timer with value in TLR0 Setting this bit loads timer/counter register (TCR0) with a specified value in the timer/counter load register (TLR0). This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT0) bit in TCSR0. - - 5 - 1 - true - read-write - - 0 - 0 - - false - - - ENIT0 - Enable Interrupt for Timer 0 - Enable Interrupt for Timer 0 -Enables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T0INT) in TCSR0. 0 - Disable interrupt signal 1 - Enable interrupt signal - - 6 - 1 - true - read-write - - 0 - 0 - - false - - - ENT0 - Enable Timer 0 - Enable Timer 0 - 0 - Disable timer (counter halts) - 1 - Enable timer (counter runs) - - 7 - 1 - true - read-write - - 0 - 0 - - false - - - T0INT - Timer 0 Interrupt - Timer 0 Interrupt -Indicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1. -Read: 0 - No interrupt has occurred 1 - Interrupt has occurred Write: 0 - No change in state of T0INT 1 - Clear T0INT (clear to 0) - - 8 - 1 - true - read-write - - 0 - 0 - - false - - - PWMA0 - Pulse Width Modulation for Timer 0 - Enable Pulse Width Modulation for Timer 0 0 - Disable pulse width modulation 1 - Enable pulse width modulation PWM requires using Timer 0 and Timer 1 together as a pair. Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0 and C_GEN0_ASSERT and C_GEN1_ASSERT must be 1. - - 9 - 1 - true - read-write - - 0 - 0 - - false - - - ENALL - Enable All Timers - Enable All Timers 0 - No effect on timers 1 - Enable all timers (counters run) This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. -Writing a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. - - 10 - 1 - true - read-write - - 0 - 0 - - false - - - CASC - Cascade Mode of Timers - Enable cascade mode of timers 0 - Disable cascaded operation 1 - Enable cascaded operation Cascaded operation requires using Timer 0 and Timer 1 together as a pair. The counting event for the Timer 1 is when the Timer 0 rolls over from all 1s to all 0s or vice-versa when counting down. -TLR0 and TLR1 are used for lower 32-bit and higher 32-bit respectively. Similarly, TCR0 contains lower 32-bits for the 64-bit counter and TCR1 contains the higher 32-bits. -Only TCSR0 is valid for both the timer/counters in this mode. -This CASC bit must be set before enabling the timer/counter. - - 11 - 1 - true - read-write - - 0 - 0 - - false - - - - TLR0 - Timer 0 Load Register - Timer 0 Load Register - 0x4 - 32 - true - read-write - - 0x0 - - - TCLR0 - Timer/Counter Load Register - Timer/Counter Load Register - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - TCR0 - Timer 0 Counter Register - Timer 0 Counter Register - 0x8 - 32 - true - read-only - - 0x0 - - - TCR0 - Timer/Counter Register - Timer/Counter Register - - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - TCSR1 - Timer 1 Control and Status Register - Timer 1 Control and Status Register - 0x10 - 32 - true - read-write - - 0x0 - - - MDT1 - Timer 1 Mode - Timer 1 Mode - 0 - Timer mode is generate - 1 - Timer mode is capture - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - UDT1 - Timer 1 Up/Down Count - Up/Down Count Timer 1 - 0 - Timer functions as up counter - 1 - Timer functions as down counter - - 1 - 1 - true - read-write - - 0 - 0 - - false - - - GENT1 - Generate Signal Timer 1 - Enable External Generate Signal Timer 1 - 0 - Disables external generate signal - 1 - Enables external generate signal - - 2 - 1 - true - read-write - - 0 - 0 - - false - - - CAPT1 - Capture Trigger Timer 1 - Enable External Capture Trigger Timer 1 - 0 - Disables external capture trigger - 1 - Enables external capture trigger - - 3 - 1 - true - read-write - - 0 - 0 - - false - - - ARHT1 - Auto Reload/Hold Timer 1 - Auto Reload/Hold Timer 1. -When the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. -In Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held. -0 = Hold counter or capture value. The TLR must be read before providing the external capture. -1 = Reload generate value or overwrite capture value - - 4 - 1 - true - read-write - - 0 - 0 - - false - - - LOAD1 - Load Timer 1 - Load Timer 1 0 = No load 1 = Loads timer with value in TLR1 Setting this bit loads timer/counter register (TCR1) with a specified value in the timer/counter load register (TLR1). This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT1) bit in TCSR1. - - 5 - 1 - true - read-write - - 0 - 0 - - false - - - ENIT1 - Enable Interrupt for Timer 1 - Enable Interrupt for Timer 1 -Enables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T1INT) in TCSR1. 0 - Disable interrupt signal 1 - Enable interrupt signal - - 6 - 1 - true - read-write - - 0 - 0 - - false - - - ENT1 - Enable Timer 1 - Enable Timer 1 - 0 - Disable timer (counter halts) - 1 - Enable timer (counter runs) - - 7 - 1 - true - read-write - - 0 - 0 - - false - - - T1INT - Timer 1 Interrupt - Timer 1 Interrupt -Indicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1. -Read: 0 - No interrupt has occurred 1 - Interrupt has occurred Write: 0 - No change in state of T0INT 1 - Clear T1INT (clear to 0) - - 8 - 1 - true - read-write - - 0 - 0 - - false - - - PWMA1 - Pulse Width Modulation for Timer 1 - Enable Pulse Width Modulation for Timer 1 0 - Disable pulse width modulation 1 - Enable pulse width modulation PWM requires using Timer 0 and Timer 1 together as a pair. Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0. - - 9 - 1 - true - read-write - - 0 - 0 - - false - - - ENALL - Enable All Timers - Enable All Timers 0 - No effect on timers 1 - Enable all timers (counters run) This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. Writing a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. - - 10 - 1 - true - read-write - - 0 - 0 - - false - - - - TLR1 - Timer 1 Load Register - Timer 1 Load Register - 0x14 - 32 - true - read-write - - 0x0 - - - TCLR1 - Timer/Counter Load Register - Timer/Counter Load Register - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - TCR1 - Timer 1 Counter Register - Timer 1 Counter Register - 0x18 - 32 - true - read-only - - 0x0 - - - TCR1 - Timer/Counter Register - Timer/Counter Register - - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - - - - - - capturetrig0 - - in - - - std_logic - dummy_view - - - - 0 - - - - - capturetrig1 - - in - - - std_logic - dummy_view - - - - 0 - - - - - generateout0 - - out - - - std_logic - dummy_view - - - - - - generateout1 - - out - - - std_logic - dummy_view - - - - - - pwm0 - - out - - - std_logic - dummy_view - - - - - - interrupt - - out - - - std_logic - dummy_view - - - - - - freeze - - in - - - std_logic - dummy_view - - - - 0 - - - - - s_axi_aclk - - in - - - std_logic - dummy_view - - - - - - s_axi_aresetn - - in - - - std_logic - dummy_view - - - - 0x1 - - - - - s_axi_awaddr - - in - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_awvalid - - in - - - std_logic - dummy_view - - - - - - s_axi_awready - - out - - - std_logic - dummy_view - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_wvalid - - in - - - std_logic - dummy_view - - - - - - s_axi_wready - - out - - - std_logic - dummy_view - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_bvalid - - out - - - std_logic - dummy_view - - - - - - s_axi_bready - - in - - - std_logic - dummy_view - - - - - - s_axi_araddr - - in - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_arvalid - - in - - - std_logic - dummy_view - - - - - - s_axi_arready - - out - - - std_logic - dummy_view - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_rvalid - - out - - - std_logic - dummy_view - - - - - - s_axi_rready - - in - - - std_logic - dummy_view - - - - - - - - C_FAMILY - kintexu - - - C_COUNT_WIDTH - Count Width - 32 - - - C_ONE_TIMER_ONLY - One Timer Only - 0 - - - C_TRIG0_ASSERT - Trig0 Assert - "1" - - - C_TRIG1_ASSERT - Trig1 Assert - "1" - - - C_GEN0_ASSERT - Gen0 Assert - "1" - - - C_GEN1_ASSERT - Gen1 Assert - "1" - - - C_S_AXI_DATA_WIDTH - Axi Data Width - 32 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 5 - - - - - - choice_list_8112d406 - 8 - 16 - 32 - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_4873554b - 0 - 1 - - - The AXI Timer/Counter is a 32/64-bit timer module that attaches to the AXI4-Lite interface - - - Component_Name - design_1_axi_timer_0_0 - - - - true - - - - - - TRIG0_ASSERT - Active state of Capture Trigger - Assertion level for capture trigger0. It can be active high or active low - Active_High - - - - true - - - - - - TRIG1_ASSERT - Active state of Capture Trigger - Assertion level for capture trigger1. It can be active high or active low - Active_High - - - - true - - - - - - GEN0_ASSERT - Active state of Generate Out signal - Assertion level for generateout0. It can be active high or active low - Active_High - - - - true - - - - - - GEN1_ASSERT - Active state of Generate Out signal - Assertion level for generateout1. It can be active high or active low - Active_High - - - - true - - - - - - COUNT_WIDTH - Width of the timer/counter (bits) - Width of timer can be selected from the range of 8 to 32 - 32 - - - - true - - - - - - mode_64bit - Enable 64-bit mode - This is cascaded mode. The two timer are cascaded to operate as a single 64 bit counter - 0 - - - - true - - - - - - enable_timer2 - Enable Timer 2 - This enables the second timer. - 1 - - - - true - - - - - - - - AXI Timer - 23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci b/hub_test/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci deleted file mode 100644 index 7c3c7af..0000000 --- a/hub_test/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci +++ /dev/null @@ -1,179 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_dlmb_bram_if_cntlr_0 - - - NONE - 16384 - 32 - 1 - - design_1_Clk - 100000000 - 0 - 0 - 0.000 - - 100000000 - 0 - 0 - 0.000 - 1 - 0 - 0 - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 256 - 1 - 1 - 1 - 1 - 0.000 - AXI4 - READ_WRITE - 0 - 0 - 1 - 0 - 0 - 0x0000000000000000 - 32 - 0 - 0 - 0 - 0 - 1 - 0 - kintexu - 0 - 0x0000000000003FFF - 0 - 32 - 32 - 0 - 0x0000000040000000 - 0x0000000000800000 - 0x0000000000800000 - 0x0000000000800000 - 1 - 32 - 32 - 0 - 2 - 0x0000000000000000 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0x0000000000003FFF - 0 - 32 - 32 - 0 - 0x0000000040000000 - 0x0000000000800000 - 0x0000000000800000 - 0x0000000000800000 - 1 - 100000000 - 32 - 32 - AXI4LITE - 0 - 2 - design_1_dlmb_bram_if_cntlr_0 - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Integrator - 18 - TRUE - . - - ../../ipshared - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xml b/hub_test/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xml deleted file mode 100644 index 8cc0adc..0000000 --- a/hub_test/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xml +++ /dev/null @@ -1,4012 +0,0 @@ - - - xilinx.com - customized_ip - design_1_dlmb_bram_if_cntlr_0 - 1.0 - - - INTERRUPT.INTERRUPT - Interrupt - Interrupt output - - - - - - - INTERRUPT - - - Interrupt - - - - - - SENSITIVITY - LEVEL_HIGH - - - SUGGESTED_PRIORITY - HIGH - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - SLMB - SLMB - Data Processor Local Bus - - - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - - - - READDBUS - - - Sl_DBus - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - - - - UE - - - Sl_UE - - - - - WAIT - - - Sl_Wait - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - SLMB1 - SLMB1 - Data Processor Local Bus - - - - - - - - - ABUS - - - LMB1_ABus - - - - - ADDRSTROBE - - - LMB1_AddrStrobe - - - - - BE - - - LMB1_BE - - - - - CE - - - Sl1_CE - - - - - READDBUS - - - Sl1_DBus - - - - - READSTROBE - - - LMB1_ReadStrobe - - - - - READY - - - Sl1_Ready - - - - - UE - - - Sl1_UE - - - - - WAIT - - - Sl1_Wait - - - - - WRITEDBUS - - - LMB1_WriteDBus - - - - - WRITESTROBE - - - LMB1_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - SLMB2 - SLMB2 - Data Processor Local Bus - - - - - - - - - ABUS - - - LMB2_ABus - - - - - ADDRSTROBE - - - LMB2_AddrStrobe - - - - - BE - - - LMB2_BE - - - - - CE - - - Sl2_CE - - - - - READDBUS - - - Sl2_DBus - - - - - READSTROBE - - - LMB2_ReadStrobe - - - - - READY - - - Sl2_Ready - - - - - UE - - - Sl2_UE - - - - - WAIT - - - Sl2_Wait - - - - - WRITEDBUS - - - LMB2_WriteDBus - - - - - WRITESTROBE - - - LMB2_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - SLMB3 - SLMB3 - Data Processor Local Bus - - - - - - - - - ABUS - - - LMB3_ABus - - - - - ADDRSTROBE - - - LMB3_AddrStrobe - - - - - BE - - - LMB3_BE - - - - - CE - - - Sl3_CE - - - - - READDBUS - - - Sl3_DBus - - - - - READSTROBE - - - LMB3_ReadStrobe - - - - - READY - - - Sl3_Ready - - - - - UE - - - Sl3_UE - - - - - WAIT - - - Sl3_Wait - - - - - WRITEDBUS - - - LMB3_WriteDBus - - - - - WRITESTROBE - - - LMB3_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - BRAM_PORT - BRAM_PORT - Data Processor Local Bus - - - - - - - ADDR - - - BRAM_Addr_A - - - - - CLK - - - BRAM_Clk_A - - - - - DIN - - - BRAM_Dout_A - - - - - DOUT - - - BRAM_Din_A - - - - - EN - - - BRAM_EN_A - - - - - RST - - - BRAM_Rst_A - - - - - WE - - - BRAM_WEN_A - - - - - - MEM_SIZE - 16384 - - - MASTER_TYPE - BRAM_CTRL - - - MEM_WIDTH - 32 - - - none - - - - - MEM_ECC - NONE - - - none - - - - - READ_WRITE_MODE - - - - none - - - - - READ_LATENCY - 1 - - - none - - - - - - - S_AXI_CTRL - S_AXI_CTRL - Slave AXI4Lite Control - - - - - - - - - ARADDR - - - S_AXI_CTRL_ARADDR - - - - - ARREADY - - - S_AXI_CTRL_ARREADY - - - - - ARVALID - - - S_AXI_CTRL_ARVALID - - - - - AWADDR - - - S_AXI_CTRL_AWADDR - - - - - AWREADY - - - S_AXI_CTRL_AWREADY - - - - - AWVALID - - - S_AXI_CTRL_AWVALID - - - - - BREADY - - - S_AXI_CTRL_BREADY - - - - - BRESP - - - S_AXI_CTRL_BRESP - - - - - BVALID - - - S_AXI_CTRL_BVALID - - - - - RDATA - - - S_AXI_CTRL_RDATA - - - - - RREADY - - - S_AXI_CTRL_RREADY - - - - - RRESP - - - S_AXI_CTRL_RRESP - - - - - RVALID - - - S_AXI_CTRL_RVALID - - - - - WDATA - - - S_AXI_CTRL_WDATA - - - - - WREADY - - - S_AXI_CTRL_WREADY - - - - - WSTRB - - - S_AXI_CTRL_WSTRB - - - - - WVALID - - - S_AXI_CTRL_WVALID - - - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 32 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 1 - - - none - - - - - HAS_LOCK - 1 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 1 - - - none - - - - - HAS_QOS - 1 - - - none - - - - - HAS_REGION - 1 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 1 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 256 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - CLK.LMB_Clk - LMB_Clk - Clock Input - - - - - - - CLK - - - LMB_Clk - - - - - - ASSOCIATED_BUSIF - SLMB:SLMB1:SLMB2:SLMB3 - - - ASSOCIATED_RESET - LMB_Rst - - - FREQ_HZ - LMB_Clk frequency - LMB_Clk frequency - 100000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - RST.LMB_Rst - Reset - Reset - - - - - - - RST - - - LMB_Rst - - - - - - POLARITY - ACTIVE_HIGH - - - TYPE - INTERCONNECT - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - CLK.S_AXI_CTRL_ACLK - S_AXI_CTRL_ACLK - Slave AXI4Lite Control Clock Input - - - - - - - CLK - - - S_AXI_CTRL_ACLK - - - - - - ASSOCIATED_BUSIF - S_AXI_CTRL - - - ASSOCIATED_RESET - S_AXI_CTRL_ARESETN - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - RST.S_AXI_CTRL_ARESETN - S_AXI_CTRL_ARESETN - Slave AXI4Lite Control Reset Input - - - - - - - RST - - - S_AXI_CTRL_ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - SLMB - SLMB memory map - - Mem - 0 - 8192 - 32 - memory - read-write - - - OFFSET_BASE_PARAM - C_BASEADDR - - - OFFSET_HIGH_PARAM - C_HIGHADDR - - - - - - SLMB1 - SLMB1 memory map - - Mem - 0 - 8192 - 32 - memory - read-write - - - OFFSET_BASE_PARAM - C_BASEADDR - - - OFFSET_HIGH_PARAM - C_HIGHADDR - - - - - - SLMB2 - SLMB2 memory map - - Mem - 0 - 8192 - 32 - memory - read-write - - - OFFSET_BASE_PARAM - C_BASEADDR - - - OFFSET_HIGH_PARAM - C_HIGHADDR - - - - - - SLMB3 - SLMB3 memory map - - Mem - 0 - 8192 - 32 - memory - read-write - - - OFFSET_BASE_PARAM - C_BASEADDR - - - OFFSET_HIGH_PARAM - C_HIGHADDR - - - - - - S_AXI_CTRL - S_AXI_CTRL memory map - - Reg - Reg - Register Block - 0 - 4096 - 32 - register - read-write - - ECC_Status - ECC Status Register - ECC Status Register - 0x0 - 2 - true - read-write - - 0x0 - - - UE_Status - UE Status - Indicates if an uncorrectable error has occurred: - 0 - No uncorrectable error occurred. - 1 - Uncorrectable error occurred, cleared when 1 is written. - - 0 - 1 - true - read-write - oneToClear - - 0 - 0 - - false - - - CE_Status - CE Status - Indicates if a correctable error has occurred: - 0 - No correctable error occurred. - 1 - Correctable error occurred, cleared when 1 is written. - - 1 - 1 - true - read-write - oneToClear - - 0 - 0 - - false - - - - - false - - - - - - ECC_EN_IRQ - ECC Interrupt Enable Register - ECC Interrupt Enable Register - 0x4 - 2 - true - read-write - - 0x0 - - - UE_EN_IRQ - UE Enable Interrupt - Determines effect of ECC Status Register UE bit: - 0 - UE bit is not propagated to interrupt signal. - 1 - UE bit is propagated to interrupt signal. - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - CE_EN_IRQ - CE Enable Interrupt - Determines effect of ECC Status Register CE bit: - 0 - CE bit is not propagated to interrupt signal. - 1 - CE bit is propagated to interrupt signal. - - 1 - 1 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - ECC_ONOFF - ECC On/Off Register - ECC On/Off Register - 0x8 - 1 - true - read-write - - 1 - - - ON_OFF - On/Off - Determines if ECC checking is enabled: - 0 - ECC checking is disabled. - 1 - ECC checking is enabled. - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - CE_CNT - Correctable Error Counter Register - Correctable Error Counter Register - 0xC - 1 - true - read-write - - 0 - - - CE_CNT - Correctable Error Count - Holds number of correctable errors encountered. - 0 - 1 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - CE_FFD - Correctable Error First Failing Data Register - Correctable Error First Failing Data Register - 0x100 - 32 - true - read-only - - 0 - - - CE_FFD - Correctable Error First Failing Data - Data of the first occurrence of a correctable error. - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - CE_FFE - Correctable Error First Failing ECC Register - Correctable Error First Failing ECC Register - 0x180 - 7 - true - read-only - - 0 - - - CE_FFE - Correctable Error First Failing ECC - ECC of the first occurrence of a correctable error. - 0 - 7 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - CE_FFA - Correctable Error First Failing Address Register - Correctable Error First Failing Address Register - 0x1C0 - 32 - true - read-only - - 0 - - - CE_FFA - Correctable Error First Failing Address - Address of the first occurrence of a correctable error. - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - UE_FFD - Uncorrectable Error First Failing Data Register - Uncorrectable Error First Failing Data Register - 0x200 - 32 - true - read-only - - 0 - - - UE_FFD - Uncorrectable Error First Failing Data - Data of the first occurrence of an uncorrectable error. - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - UE_FFE - Uncorrectable Error First Failing ECC Register - Uncorrectable Error First Failing ECC Register - 0x280 - 7 - true - read-only - - 0 - - - UE_FFE - Uncorrectable Error First Failing ECC - ECC of the first occurrence of an uncorrectable error. - 0 - 7 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - UE_FFA - Uncorrectable Error First Failing Address Register - Uncorrectable Error First Failing Address Register - 0x2C0 - 32 - true - read-only - - 0 - - - UE_FFA - Uncorrectable Error First Failing Address - Address of the first occurrence of an uncorrectable error. - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - FI_D - Fault Inject Data Register - Fault Inject Data Register - 0x300 - 32 - true - write-only - - 0 - - - FI_D - Fault Inject Data - Bits set to 1 toggle the bits of next data word written. - 0 - 32 - true - write-only - oneToToggle - - 0 - 0 - - false - - - - - false - - - - - - FI_ECC - Fault Inject ECC Register - Fault Inject ECC Register - 0x380 - 7 - true - write-only - - 0 - - - FI_ECC - Fault Inject ECC - Bits set to 1 toggle the bits of next ECC written. - 0 - 7 - true - write-only - oneToToggle - - 0 - 0 - - false - - - - - false - - - - - - - - - - - LMB_Clk - - in - - - std_logic - dummy_view - - - - 0x0 - - - - - LMB_Rst - - in - - - std_logic - dummy_view - - - - 0x0 - - - - - LMB_ABus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - LMB_WriteDBus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - LMB_AddrStrobe - - in - - - std_logic - dummy_view - - - - - - LMB_ReadStrobe - - in - - - std_logic - dummy_view - - - - - - LMB_WriteStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - LMB_BE - - in - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - Sl_DBus - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - Sl_Ready - - out - - - std_logic - dummy_view - - - - - - Sl_Wait - - out - - - std_logic - dummy_view - - - - - - Sl_UE - - out - - - std_logic - dummy_view - - - - - - Sl_CE - - out - - - std_logic - dummy_view - - - - - - LMB1_ABus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB1_WriteDBus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB1_AddrStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB1_ReadStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB1_WriteStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB1_BE - - in - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - Sl1_DBus - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - Sl1_Ready - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl1_Wait - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl1_UE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl1_CE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB2_ABus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB2_WriteDBus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB2_AddrStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB2_ReadStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB2_WriteStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB2_BE - - in - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - Sl2_DBus - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - Sl2_Ready - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl2_Wait - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl2_UE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl2_CE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB3_ABus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB3_WriteDBus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB3_AddrStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB3_ReadStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB3_WriteStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB3_BE - - in - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - Sl3_DBus - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - Sl3_Ready - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl3_Wait - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl3_UE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl3_CE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - BRAM_Rst_A - - out - - - std_logic - dummy_view - - - - - - BRAM_Clk_A - - out - - - std_logic - dummy_view - - - - - - BRAM_Addr_A - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - BRAM_EN_A - - out - - - std_logic - dummy_view - - - - - - BRAM_WEN_A - - out - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - - - BRAM_Dout_A - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - BRAM_Din_A - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - S_AXI_CTRL_ACLK - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_ARESETN - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_AWADDR - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_AWVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_AWREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_WDATA - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_WSTRB - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_WVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_WREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_BRESP - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_BVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_BREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_ARADDR - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_ARVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_ARREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_RDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_RRESP - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_RVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_RREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - UE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - CE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Interrupt - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - - - C_FAMILY - kintexu - - - C_HIGHADDR - LMB BRAM High Address - 0x0000000000003FFF - - - C_BASEADDR - LMB BRAM Base Address - 0x0000000000000000 - - - C_NUM_LMB - Number of LMB Ports - 1 - - - C_MASK - SLMB Address Decode Mask - 0x0000000040000000 - - - C_MASK1 - SLMB1 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_MASK2 - SLMB2 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_MASK3 - SLMB3 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_LMB_AWIDTH - LMB Address Bus Width - 32 - - - C_LMB_DWIDTH - LMB Data Bus Width - 32 - - - C_LMB_PROTOCOL - LMB Protocol - 0 - - - C_ECC - Error Correction Code - 0 - - - C_INTERCONNECT - Select Interconnect - 0 - - - - false - - - - - - C_FAULT_INJECT - Fault Inject Registers - 0 - - - - false - - - - - - C_CE_FAILING_REGISTERS - Correctable Error First Failing Register - 0 - - - - false - - - - - - C_UE_FAILING_REGISTERS - Uncorrectable Error First Failing Register - 0 - - - - false - - - - - - C_ECC_STATUS_REGISTERS - ECC Status and Control Register - 0 - - - - false - - - - - - C_ECC_ONOFF_REGISTER - ECC On/Off Register - 0 - - - - false - - - - - - C_ECC_ONOFF_RESET_VALUE - ECC On/Off Reset Value - 1 - - - - false - - - - - - C_CE_COUNTER_WIDTH - Correctable Error Counter Register Width - 0 - - - - false - - - - - - C_WRITE_ACCESS - Write Access setting - 2 - - - - false - - - - - - C_BRAM_AWIDTH - BRAM Address Bus Width - 32 - - - C_S_AXI_CTRL_ADDR_WIDTH - S_AXI_CTRL Address Width - 32 - - - - false - - - - - - C_S_AXI_CTRL_DATA_WIDTH - S_AXI_CTRL Data Width - 32 - - - - false - - - - - - - - - choice_list_6fc15197 - 32 - - - choice_pairs_0873e75e - 0 - 1 - - - choice_pairs_449ac0d2 - 0 - 1 - 2 - - - choice_pairs_4873554b - 0 - 1 - - - choice_pairs_8d6e70ff - 0 - 2 - - - Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus - - - C_BASEADDR - LMB BRAM Base Address - 0x0000000000000000 - - - - true - - - - - - C_HIGHADDR - LMB BRAM High Address - 0x0000000000003FFF - - - - true - - - - - - C_MASK - SLMB Address Decode Mask - 0x0000000040000000 - - - - true - - - - - - C_MASK1 - SLMB1 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_MASK2 - SLMB2 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_MASK3 - SLMB3 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_NUM_LMB - Number of LMB Ports - 1 - - - - true - - - - - - C_LMB_AWIDTH - LMB Address Bus Width - 32 - - - - true - - - - - - C_LMB_DWIDTH - LMB Data Bus Width - 32 - - - - true - - - - - - C_LMB_PROTOCOL - LMB Protocol - 0 - - - C_ECC - Error Correction Code - 0 - - - - true - - - - - - C_INTERCONNECT - Select Interconnect - 0 - - - - false - - - - - - C_FAULT_INJECT - Fault Inject Registers - 0 - - - - false - - - - - - C_CE_FAILING_REGISTERS - Correctable Error First Failing Register - 0 - - - - false - - - - - - C_UE_FAILING_REGISTERS - Uncorrectable Error First Failing Register - 0 - - - - false - - - - - - C_ECC_STATUS_REGISTERS - ECC Status and Control Register - 0 - - - - false - - - - - - C_ECC_ONOFF_REGISTER - ECC On/Off Register - 0 - - - - false - - - - - - C_ECC_ONOFF_RESET_VALUE - ECC On/Off Reset Value - 1 - - - - false - - - - - - C_CE_COUNTER_WIDTH - Correctable Error Counter Register Width - 0 - - - - false - - - - - - C_WRITE_ACCESS - Write Access setting - 2 - - - - false - - - - - - C_S_AXI_CTRL_ACLK_FREQ_HZ - S_AXI_CTRL Clock Frequency - 100000000 - - - - false - - - - - - C_S_AXI_CTRL_ADDR_WIDTH - S_AXI_CTRL Address Width - 32 - - - - true - - - - - - C_S_AXI_CTRL_DATA_WIDTH - S_AXI_CTRL Data Width - 32 - - - - true - - - - - - C_S_AXI_CTRL_PROTOCOL - S_AXI_CTRL Protocol - AXI4LITE - - - - false - - - - - - Component_Name - design_1_dlmb_bram_if_cntlr_0 - - - - - LMB BRAM Controller - 18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci b/hub_test/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci deleted file mode 100644 index 746b97c..0000000 --- a/hub_test/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci +++ /dev/null @@ -1,142 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_dlmb_v10_0 - - - design_1_Clk - 100000000 - 0 - 0 - 0.000 - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 0 - 1 - 32 - 32 - 1 - 0 - 1 - 32 - 32 - 1 - 0 - design_1_dlmb_v10_0 - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Integrator - 11 - TRUE - . - - ../../ipshared - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xml b/hub_test/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xml deleted file mode 100644 index 62b9adc..0000000 --- a/hub_test/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xml +++ /dev/null @@ -1,3527 +0,0 @@ - - - xilinx.com - customized_ip - design_1_dlmb_v10_0 - 1.0 - - - LMB_Sl_0 - LMB_Sl_00 - Local Memory Bus Mirrored Slave interface 0 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 0 - 0 - - - - - - READDBUS - - - Sl_DBus - - 0 - 31 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 0 - 0 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 0 - 0 - - - - - - WAIT - - - Sl_Wait - - 0 - 0 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - true - - - - - - LMB_Sl_1 - LMB_Sl_01 - Local Memory Bus Mirrored Slave interface 1 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 1 - 1 - - - - - - READDBUS - - - Sl_DBus - - 32 - 63 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 1 - 1 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 1 - 1 - - - - - - WAIT - - - Sl_Wait - - 1 - 1 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_2 - LMB_Sl_02 - Local Memory Bus Mirrored Slave interface 2 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 2 - 2 - - - - - - READDBUS - - - Sl_DBus - - 64 - 95 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 2 - 2 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 2 - 2 - - - - - - WAIT - - - Sl_Wait - - 2 - 2 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_3 - LMB_Sl_03 - Local Memory Bus Mirrored Slave interface 3 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 3 - 3 - - - - - - READDBUS - - - Sl_DBus - - 96 - 127 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 3 - 3 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 3 - 3 - - - - - - WAIT - - - Sl_Wait - - 3 - 3 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_4 - LMB_Sl_04 - Local Memory Bus Mirrored Slave interface 4 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 4 - 4 - - - - - - READDBUS - - - Sl_DBus - - 128 - 159 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 4 - 4 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 4 - 4 - - - - - - WAIT - - - Sl_Wait - - 4 - 4 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_5 - LMB_Sl_05 - Local Memory Bus Mirrored Slave interface 5 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 5 - 5 - - - - - - READDBUS - - - Sl_DBus - - 160 - 191 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 5 - 5 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 5 - 5 - - - - - - WAIT - - - Sl_Wait - - 5 - 5 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_6 - LMB_Sl_06 - Local Memory Bus Mirrored Slave interface 6 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 6 - 6 - - - - - - READDBUS - - - Sl_DBus - - 192 - 223 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 6 - 6 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 6 - 6 - - - - - - WAIT - - - Sl_Wait - - 6 - 6 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_7 - LMB_Sl_07 - Local Memory Bus Mirrored Slave interface 7 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 7 - 7 - - - - - - READDBUS - - - Sl_DBus - - 224 - 255 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 7 - 7 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 7 - 7 - - - - - - WAIT - - - Sl_Wait - - 7 - 7 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_8 - LMB_Sl_08 - Local Memory Bus Mirrored Slave interface 8 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 8 - 8 - - - - - - READDBUS - - - Sl_DBus - - 256 - 287 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 8 - 8 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 8 - 8 - - - - - - WAIT - - - Sl_Wait - - 8 - 8 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_9 - LMB_Sl_09 - Local Memory Bus Mirrored Slave interface 9 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 9 - 9 - - - - - - READDBUS - - - Sl_DBus - - 288 - 319 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 9 - 9 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 9 - 9 - - - - - - WAIT - - - Sl_Wait - - 9 - 9 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_10 - LMB_Sl_10 - Local Memory Bus Mirrored Slave interface 10 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 10 - 10 - - - - - - READDBUS - - - Sl_DBus - - 320 - 351 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 10 - 10 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 10 - 10 - - - - - - WAIT - - - Sl_Wait - - 10 - 10 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_11 - LMB_Sl_11 - Local Memory Bus Mirrored Slave interface 11 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 11 - 11 - - - - - - READDBUS - - - Sl_DBus - - 352 - 383 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 11 - 11 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 11 - 11 - - - - - - WAIT - - - Sl_Wait - - 11 - 11 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_12 - LMB_Sl_12 - Local Memory Bus Mirrored Slave interface 12 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 12 - 12 - - - - - - READDBUS - - - Sl_DBus - - 384 - 415 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 12 - 12 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 12 - 12 - - - - - - WAIT - - - Sl_Wait - - 12 - 12 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_13 - LMB_Sl_13 - Local Memory Bus Mirrored Slave interface 13 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 13 - 13 - - - - - - READDBUS - - - Sl_DBus - - 416 - 447 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 13 - 13 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 13 - 13 - - - - - - WAIT - - - Sl_Wait - - 13 - 13 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_14 - LMB_Sl_14 - Local Memory Bus Mirrored Slave interface 14 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 14 - 14 - - - - - - READDBUS - - - Sl_DBus - - 448 - 479 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 14 - 14 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 14 - 14 - - - - - - WAIT - - - Sl_Wait - - 14 - 14 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_15 - LMB_Sl_15 - Local Memory Bus Mirrored Slave interface 15 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 15 - 15 - - - - - - READDBUS - - - Sl_DBus - - 480 - 511 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 15 - 15 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 15 - 15 - - - - - - WAIT - - - Sl_Wait - - 15 - 15 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_M - LMB_M - Local Memory Bus Mirrored Master interface - - - - - - - ABUS - - - M_ABus - - - - - ADDRSTROBE - - - M_AddrStrobe - - - - - BE - - - M_BE - - - - - CE - - - LMB_CE - - - - - READDBUS - - - LMB_ReadDBus - - - - - READSTROBE - - - M_ReadStrobe - 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- - TYPE - INTERCONNECT - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - LMB_Channel - LMB_M - LMB_Sl_0 - LMB_Sl_1 - LMB_Sl_2 - LMB_Sl_3 - LMB_Sl_4 - LMB_Sl_5 - LMB_Sl_6 - LMB_Sl_7 - LMB_Sl_8 - LMB_Sl_9 - LMB_Sl_10 - LMB_Sl_11 - LMB_Sl_12 - LMB_Sl_13 - LMB_Sl_14 - LMB_Sl_15 - - - - - - LMB_Clk - - in - - - std_logic - dummy_view - - - - - - SYS_Rst - - in - - - std_logic - dummy_view - - - - - - LMB_Rst - - out - - - std_logic - dummy_view - - - - - - M_ABus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - M_ReadStrobe - - in - - - std_logic - dummy_view - - - - - - M_WriteStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - M_AddrStrobe - - in - - - std_logic - dummy_view - - - - - - M_DBus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - M_BE - - in - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - Sl_DBus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - Sl_Ready - - in - - 0 - 0 - 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TRUE - IP_Integrator - 18 - TRUE - . - - ../../ipshared - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xml b/hub_test/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xml deleted file mode 100644 index c53489f..0000000 --- a/hub_test/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xml +++ /dev/null @@ -1,4012 +0,0 @@ - - - xilinx.com - customized_ip - design_1_ilmb_bram_if_cntlr_0 - 1.0 - - - INTERRUPT.INTERRUPT - Interrupt - Interrupt output - - - - - - - INTERRUPT - - - Interrupt - - - - - - SENSITIVITY - LEVEL_HIGH - - - SUGGESTED_PRIORITY - HIGH - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - SLMB - SLMB - Data Processor Local Bus - - - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - - - - READDBUS - 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1 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 1 - - - none - - - - - HAS_QOS - 1 - - - none - - - - - HAS_REGION - 1 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 1 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 256 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - CLK.LMB_Clk - LMB_Clk - Clock Input - - - - - - - CLK - - - LMB_Clk - - - - - - ASSOCIATED_BUSIF - SLMB:SLMB1:SLMB2:SLMB3 - - - ASSOCIATED_RESET - LMB_Rst - - - FREQ_HZ - LMB_Clk frequency - LMB_Clk frequency - 100000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - RST.LMB_Rst - Reset - Reset - - - - - - - RST - - - LMB_Rst - - - - - - POLARITY - ACTIVE_HIGH - - - TYPE - INTERCONNECT - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - CLK.S_AXI_CTRL_ACLK - S_AXI_CTRL_ACLK - Slave AXI4Lite Control Clock Input - - - - - - - CLK - - - S_AXI_CTRL_ACLK - - - - - - ASSOCIATED_BUSIF - S_AXI_CTRL - - - ASSOCIATED_RESET - S_AXI_CTRL_ARESETN - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - RST.S_AXI_CTRL_ARESETN - S_AXI_CTRL_ARESETN - Slave AXI4Lite Control Reset Input - - - - - - - RST - - - S_AXI_CTRL_ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - SLMB - SLMB memory map - - Mem - 0 - 8192 - 32 - memory - read-write - - - OFFSET_BASE_PARAM - C_BASEADDR - - - OFFSET_HIGH_PARAM - C_HIGHADDR - - - - - - SLMB1 - SLMB1 memory map - - Mem - 0 - 8192 - 32 - memory - read-write - - - OFFSET_BASE_PARAM - C_BASEADDR - - - OFFSET_HIGH_PARAM - C_HIGHADDR - - - - - - SLMB2 - SLMB2 memory map - - Mem - 0 - 8192 - 32 - memory - read-write - - - OFFSET_BASE_PARAM - C_BASEADDR - - - OFFSET_HIGH_PARAM - C_HIGHADDR - - - - - - SLMB3 - SLMB3 memory map - - Mem - 0 - 8192 - 32 - memory - read-write - - - OFFSET_BASE_PARAM - C_BASEADDR - - - OFFSET_HIGH_PARAM - C_HIGHADDR - - - - - - S_AXI_CTRL - S_AXI_CTRL memory map - - Reg - Reg - Register Block - 0 - 4096 - 32 - register - read-write - - ECC_Status - ECC Status Register - ECC Status Register - 0x0 - 2 - true - read-write - - 0x0 - - - UE_Status - UE Status - Indicates if an uncorrectable error has occurred: - 0 - No uncorrectable error occurred. - 1 - Uncorrectable error occurred, cleared when 1 is written. - - 0 - 1 - true - read-write - oneToClear - - 0 - 0 - - false - - - CE_Status - CE Status - Indicates if a correctable error has occurred: - 0 - No correctable error occurred. - 1 - Correctable error occurred, cleared when 1 is written. - - 1 - 1 - true - read-write - oneToClear - - 0 - 0 - - false - - - - - false - - - - - - ECC_EN_IRQ - ECC Interrupt Enable Register - ECC Interrupt Enable Register - 0x4 - 2 - true - read-write - - 0x0 - - - UE_EN_IRQ - UE Enable Interrupt - Determines effect of ECC Status Register UE bit: - 0 - UE bit is not propagated to interrupt signal. - 1 - UE bit is propagated to interrupt signal. - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - CE_EN_IRQ - CE Enable Interrupt - Determines effect of ECC Status Register CE bit: - 0 - CE bit is not propagated to interrupt signal. - 1 - CE bit is propagated to interrupt signal. - - 1 - 1 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - ECC_ONOFF - ECC On/Off Register - ECC On/Off Register - 0x8 - 1 - true - read-write - - 1 - - - ON_OFF - On/Off - Determines if ECC checking is enabled: - 0 - ECC checking is disabled. - 1 - ECC checking is enabled. - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - CE_CNT - Correctable Error Counter Register - Correctable Error Counter Register - 0xC - 1 - true - read-write - - 0 - - - CE_CNT - Correctable Error Count - Holds number of correctable errors encountered. - 0 - 1 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - CE_FFD - Correctable Error First Failing Data Register - Correctable Error First Failing Data Register - 0x100 - 32 - true - read-only - - 0 - - - CE_FFD - Correctable Error First Failing Data - Data of the first occurrence of a correctable error. - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - CE_FFE - Correctable Error First Failing ECC Register - Correctable Error First Failing ECC Register - 0x180 - 7 - true - read-only - - 0 - - - CE_FFE - Correctable Error First Failing ECC - ECC of the first occurrence of a correctable error. - 0 - 7 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - CE_FFA - Correctable Error First Failing Address Register - Correctable Error First Failing Address Register - 0x1C0 - 32 - true - read-only - - 0 - - - CE_FFA - Correctable Error First Failing Address - Address of the first occurrence of a correctable error. - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - UE_FFD - Uncorrectable Error First Failing Data Register - Uncorrectable Error First Failing Data Register - 0x200 - 32 - true - read-only - - 0 - - - UE_FFD - Uncorrectable Error First Failing Data - Data of the first occurrence of an uncorrectable error. - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - UE_FFE - Uncorrectable Error First Failing ECC Register - Uncorrectable Error First Failing ECC Register - 0x280 - 7 - true - read-only - - 0 - - - UE_FFE - Uncorrectable Error First Failing ECC - ECC of the first occurrence of an uncorrectable error. - 0 - 7 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - UE_FFA - Uncorrectable Error First Failing Address Register - Uncorrectable Error First Failing Address Register - 0x2C0 - 32 - true - read-only - - 0 - - - UE_FFA - Uncorrectable Error First Failing Address - Address of the first occurrence of an uncorrectable error. - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - FI_D - Fault Inject Data Register - Fault Inject Data Register - 0x300 - 32 - true - write-only - - 0 - - - FI_D - Fault Inject Data - Bits set to 1 toggle the bits of next data word written. - 0 - 32 - true - write-only - oneToToggle - - 0 - 0 - - false - - - - - false - - - - - - FI_ECC - Fault Inject ECC Register - Fault Inject ECC Register - 0x380 - 7 - true - write-only - - 0 - - - FI_ECC - Fault Inject ECC - Bits set to 1 toggle the bits of next ECC written. - 0 - 7 - true - write-only - oneToToggle - - 0 - 0 - - false - - - - - false - - - - - - - - - - - LMB_Clk - - in - - - std_logic - dummy_view - - - - 0x0 - - - - - LMB_Rst - - in - - - std_logic - dummy_view - - - - 0x0 - - - - - LMB_ABus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - LMB_WriteDBus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - LMB_AddrStrobe - - in - - - std_logic - dummy_view - - - - - - LMB_ReadStrobe - - in - - - std_logic - dummy_view - - - - - - LMB_WriteStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - LMB_BE - - in - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - Sl_DBus - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - Sl_Ready - - out - - - std_logic - dummy_view - - - - - - Sl_Wait - - out - - - std_logic - dummy_view - - - - - - Sl_UE - - out - - - std_logic - dummy_view - - - - - - Sl_CE - - out - - - std_logic - dummy_view - - - - - - LMB1_ABus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB1_WriteDBus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB1_AddrStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB1_ReadStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB1_WriteStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB1_BE - - in - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - Sl1_DBus - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - Sl1_Ready - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl1_Wait - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl1_UE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl1_CE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB2_ABus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB2_WriteDBus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB2_AddrStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB2_ReadStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB2_WriteStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB2_BE - - in - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - Sl2_DBus - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - Sl2_Ready - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl2_Wait - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl2_UE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl2_CE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB3_ABus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB3_WriteDBus - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB3_AddrStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB3_ReadStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB3_WriteStrobe - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB3_BE - - in - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - Sl3_DBus - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - Sl3_Ready - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl3_Wait - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl3_UE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Sl3_CE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - BRAM_Rst_A - - out - - - std_logic - dummy_view - - - - - - BRAM_Clk_A - - out - - - std_logic - dummy_view - - - - - - BRAM_Addr_A - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - BRAM_EN_A - - out - - - std_logic - dummy_view - - - - - - BRAM_WEN_A - - out - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - - - BRAM_Dout_A - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - BRAM_Din_A - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - S_AXI_CTRL_ACLK - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_ARESETN - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_AWADDR - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_AWVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_AWREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_WDATA - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_WSTRB - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_WVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_WREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_BRESP - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_BVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_BREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_ARADDR - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_ARVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_CTRL_ARREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_RDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_RRESP - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_RVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - S_AXI_CTRL_RREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - UE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - CE - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Interrupt - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - - - C_FAMILY - kintexu - - - C_HIGHADDR - LMB BRAM High Address - 0x0000000000003FFF - - - C_BASEADDR - LMB BRAM Base Address - 0x0000000000000000 - - - C_NUM_LMB - Number of LMB Ports - 1 - - - C_MASK - SLMB Address Decode Mask - 0x0000000000000000 - - - C_MASK1 - SLMB1 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_MASK2 - SLMB2 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_MASK3 - SLMB3 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_LMB_AWIDTH - LMB Address Bus Width - 32 - - - C_LMB_DWIDTH - LMB Data Bus Width - 32 - - - C_LMB_PROTOCOL - LMB Protocol - 0 - - - C_ECC - Error Correction Code - 0 - - - C_INTERCONNECT - Select Interconnect - 0 - - - - false - - - - - - C_FAULT_INJECT - Fault Inject Registers - 0 - - - - false - - - - - - C_CE_FAILING_REGISTERS - Correctable Error First Failing Register - 0 - - - - false - - - - - - C_UE_FAILING_REGISTERS - Uncorrectable Error First Failing Register - 0 - - - - false - - - - - - C_ECC_STATUS_REGISTERS - ECC Status and Control Register - 0 - - - - false - - - - - - C_ECC_ONOFF_REGISTER - ECC On/Off Register - 0 - - - - false - - - - - - C_ECC_ONOFF_RESET_VALUE - ECC On/Off Reset Value - 1 - - - - false - - - - - - C_CE_COUNTER_WIDTH - Correctable Error Counter Register Width - 0 - - - - false - - - - - - C_WRITE_ACCESS - Write Access setting - 2 - - - - false - - - - - - C_BRAM_AWIDTH - BRAM Address Bus Width - 32 - - - C_S_AXI_CTRL_ADDR_WIDTH - S_AXI_CTRL Address Width - 32 - - - - false - - - - - - C_S_AXI_CTRL_DATA_WIDTH - S_AXI_CTRL Data Width - 32 - - - - false - - - - - - - - - choice_list_6fc15197 - 32 - - - choice_pairs_0873e75e - 0 - 1 - - - choice_pairs_449ac0d2 - 0 - 1 - 2 - - - choice_pairs_4873554b - 0 - 1 - - - choice_pairs_8d6e70ff - 0 - 2 - - - Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus - - - C_BASEADDR - LMB BRAM Base Address - 0x0000000000000000 - - - - true - - - - - - C_HIGHADDR - LMB BRAM High Address - 0x0000000000003FFF - - - - true - - - - - - C_MASK - SLMB Address Decode Mask - 0x0000000000000000 - - - - true - - - - - - C_MASK1 - SLMB1 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_MASK2 - SLMB2 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_MASK3 - SLMB3 Address Decode Mask - 0x0000000000800000 - - - - false - - - - - - C_NUM_LMB - Number of LMB Ports - 1 - - - - true - - - - - - C_LMB_AWIDTH - LMB Address Bus Width - 32 - - - - true - - - - - - C_LMB_DWIDTH - LMB Data Bus Width - 32 - - - - true - - - - - - C_LMB_PROTOCOL - LMB Protocol - 0 - - - C_ECC - Error Correction Code - 0 - - - - true - - - - - - C_INTERCONNECT - Select Interconnect - 0 - - - - false - - - - - - C_FAULT_INJECT - Fault Inject Registers - 0 - - - - false - - - - - - C_CE_FAILING_REGISTERS - Correctable Error First Failing Register - 0 - - - - false - - - - - - C_UE_FAILING_REGISTERS - Uncorrectable Error First Failing Register - 0 - - - - false - - - - - - C_ECC_STATUS_REGISTERS - ECC Status and Control Register - 0 - - - - false - - - - - - C_ECC_ONOFF_REGISTER - ECC On/Off Register - 0 - - - - false - - - - - - C_ECC_ONOFF_RESET_VALUE - ECC On/Off Reset Value - 1 - - - - false - - - - - - C_CE_COUNTER_WIDTH - Correctable Error Counter Register Width - 0 - - - - false - - - - - - C_WRITE_ACCESS - Write Access setting - 2 - - - - false - - - - - - C_S_AXI_CTRL_ACLK_FREQ_HZ - S_AXI_CTRL Clock Frequency - 100000000 - - - - false - - - - - - C_S_AXI_CTRL_ADDR_WIDTH - S_AXI_CTRL Address Width - 32 - - - - true - - - - - - C_S_AXI_CTRL_DATA_WIDTH - S_AXI_CTRL Data Width - 32 - - - - true - - - - - - C_S_AXI_CTRL_PROTOCOL - S_AXI_CTRL Protocol - AXI4LITE - - - - false - - - - - - Component_Name - design_1_ilmb_bram_if_cntlr_0 - - - - - LMB BRAM Controller - 18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci b/hub_test/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci deleted file mode 100644 index 17beaba..0000000 --- a/hub_test/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci +++ /dev/null @@ -1,142 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_ilmb_v10_0 - - - design_1_Clk - 100000000 - 0 - 0 - 0.000 - 32 - 32 - STANDARD - READ_ONLY - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 32 - 32 - STANDARD - READ_WRITE - 0 - 1 - 32 - 32 - 1 - 0 - 1 - 32 - 32 - 1 - 0 - design_1_ilmb_v10_0 - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Integrator - 11 - TRUE - . - - ../../ipshared - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xml b/hub_test/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xml deleted file mode 100644 index 654d9ba..0000000 --- a/hub_test/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xml +++ /dev/null @@ -1,3527 +0,0 @@ - - - xilinx.com - customized_ip - design_1_ilmb_v10_0 - 1.0 - - - LMB_Sl_0 - LMB_Sl_00 - Local Memory Bus Mirrored Slave interface 0 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 0 - 0 - - - - - - READDBUS - - - Sl_DBus - - 0 - 31 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 0 - 0 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 0 - 0 - - - - - - WAIT - - - Sl_Wait - - 0 - 0 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - true - - - - - - LMB_Sl_1 - LMB_Sl_01 - Local Memory Bus Mirrored Slave interface 1 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 1 - 1 - - - - - - READDBUS - - - Sl_DBus - - 32 - 63 - - - - - - READSTROBE - - - LMB_ReadStrobe - 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- LMB_Sl_11 - LMB_Sl_11 - Local Memory Bus Mirrored Slave interface 11 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 11 - 11 - - - - - - READDBUS - - - Sl_DBus - - 352 - 383 - - - - - - READSTROBE - - - LMB_ReadStrobe - - - - - READY - - - Sl_Ready - - 11 - 11 - - - - - - RST - - - LMB_Rst - - - - - UE - - - Sl_UE - - 11 - 11 - - - - - - WAIT - - - Sl_Wait - - 11 - 11 - - - - - - WRITEDBUS - - - LMB_WriteDBus - - - - - WRITESTROBE - - - LMB_WriteStrobe - - - - - - ADDR_WIDTH - 32 - - - none - - - - - DATA_WIDTH - 32 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - PROTOCOL - STANDARD - - - none - - - - - - - - false - - - - - - LMB_Sl_12 - LMB_Sl_12 - Local Memory Bus Mirrored Slave interface 12 - - - - - - - ABUS - - - LMB_ABus - - - - - ADDRSTROBE - - - LMB_AddrStrobe - - - - - BE - - - LMB_BE - - - - - CE - - - Sl_CE - - 12 - 12 - - - - - - READDBUS - - - Sl_DBus - - 384 - 415 - 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- - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 32 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 1 - - - none - - - - - HAS_LOCK - 1 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 1 - - - none - - - - - HAS_QOS - 1 - - - none - - - - - HAS_REGION - 1 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 1 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 256 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - BRAM_PORTA - BRAM_PORTA - BRAM_PORTA - - - - - - - ADDR - - - addra - - - - - CLK - - - clka - - - - - DIN - - - dina - - - - - DOUT - - - douta - - - - - EN - - - ena - - - - - RST - - - rsta - - - - - WE - - - wea - - - - - - MEM_SIZE - 16384 - - - none - - - - - MEM_WIDTH - 32 - - - none - - - - - MEM_ECC - NONE - - - none - - - - - MASTER_TYPE - BRAM_CTRL - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - READ_LATENCY - 1 - - - none - - - - - - - - true - - - - - - BRAM_PORTB - BRAM_PORTB - BRAM_PORTB - - - - - - - ADDR - - - addrb - - - - - CLK - - - clkb - - - - - DIN - - - dinb - - - - - DOUT - - - doutb - - - - - EN - - - enb - - - - - RST - - - rstb - - - - - WE - - - web - - - - - - MEM_SIZE - 16384 - - - none - - - - - MEM_WIDTH - 32 - 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0 - - - - std_logic_vector - dummy_view - - - - - - - true - - - - - - clkb - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - rstb - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - enb - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - regceb - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - web - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - true - - - - - - addrb - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - true - - - - - - dinb - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - true - - - - - - doutb - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - true - - - - - - injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - eccpipece - - in - - - std_logic - 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- - C_READ_DEPTH_A - 4096 - - - C_ADDRA_WIDTH - 32 - - - C_HAS_RSTB - 1 - - - C_RST_PRIORITY_B - CE - - - C_RSTRAM_B - 0 - - - C_INITB_VAL - 0 - - - C_HAS_ENB - 1 - - - C_HAS_REGCEB - 0 - - - C_USE_BYTE_WEB - 1 - - - C_WEB_WIDTH - 4 - - - C_WRITE_MODE_B - WRITE_FIRST - - - C_WRITE_WIDTH_B - 32 - - - C_READ_WIDTH_B - 32 - - - C_WRITE_DEPTH_B - 4096 - - - C_READ_DEPTH_B - 4096 - - - C_ADDRB_WIDTH - 32 - - - C_HAS_MEM_OUTPUT_REGS_A - 0 - - - C_HAS_MEM_OUTPUT_REGS_B - 0 - - - C_HAS_MUX_OUTPUT_REGS_A - 0 - - - C_HAS_MUX_OUTPUT_REGS_B - 0 - - - C_MUX_PIPELINE_STAGES - 0 - - - C_HAS_SOFTECC_INPUT_REGS_A - 0 - - - C_HAS_SOFTECC_OUTPUT_REGS_B - 0 - - - C_USE_SOFTECC - 0 - - - C_USE_ECC - 0 - - - C_EN_ECC_PIPE - 0 - - - C_READ_LATENCY_A - 1 - - - C_READ_LATENCY_B - 1 - - - C_HAS_INJECTERR - 0 - - - C_SIM_COLLISION_CHECK - ALL - - - C_COMMON_CLK - 0 - - - C_DISABLE_WARN_BHV_COLL - 0 - - - C_EN_SLEEP_PIN - 0 - - - C_USE_URAM - 0 - - - C_EN_RDADDRA_CHG - 0 - - - C_EN_RDADDRB_CHG - 0 - - - C_EN_DEEPSLEEP_PIN - 0 - - - C_EN_SHUTDOWN_PIN - 0 - - - C_EN_SAFETY_CKT - 1 - - - C_DISABLE_WARN_BHV_RANGE - 0 - - - C_COUNT_36K_BRAM - 4 - - - C_COUNT_18K_BRAM - 0 - - - C_EST_POWER_SUMMARY - Estimated Power for IP : 1.75104 mW - - - - - - choice_list_0132492a - 32 - 64 - 128 - - - choice_list_302d3091 - 16kx1 - 8kx2 - 4kx4 - 2kx9 - 1kx18 - 512x36 - - - choice_list_6e3ded9c - 0 - 1 - 2 - 3 - - - choice_list_6fc15197 - 32 - - - choice_list_89a27b2f - 8 - 9 - - - choice_list_bdf7387e - BRAM - URAM - AUTO - - - choice_list_c8df20f0 - NONE - ECCH32-7 - ECCH64-8 - ECCHSIAO32-7 - ECCHSIAO64-8 - ECCHSIAO128-9 - - - choice_list_f9a6a28b - Native - - - choice_pairs_1f270a52 - BRAM_Controller - Stand_Alone - - - choice_pairs_246d8066 - WRITE_FIRST - READ_FIRST - - - choice_pairs_2adcaf32 - SYNC - ASYNC - - - choice_pairs_2d73cdeb - Always_Enabled - Use_ENB_Pin - - - choice_pairs_3949ecbf - Always_Enabled - Use_ENA_Pin - - - choice_pairs_3e9ce7ae - Minimum_Area - Low_Power - Fixed_Primitives - - - choice_pairs_44b9b2d1 - ALL - NONE - WARNING_ONLY - GENERATE_X_ONLY - - - choice_pairs_63de7f78 - CE - SR - - - choice_pairs_716d2fba - Single_Bit_Error_Injection - Double_Bit_Error_Injection - Single_and_Double_Bit_Error_Injection - - - choice_pairs_a6697bba - Single_Port_RAM - True_Dual_Port_RAM - Single_Port_ROM - Dual_Port_ROM - - - choice_pairs_b91edaa2 - Memory_Slave - Peripheral_Slave - - - choice_pairs_c1013cbe - No_ECC - Soft_ECC - BuiltIn_ECC - - - choice_pairs_e4c322cb - AXI4_Full - AXI4_Lite - - - The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. - - - Component_Name - design_1_lmb_bram_0 - - - - true - - - - - - Interface_Type - Native - - - - true - - - - - - AXI_Type - AXI4_Full - - - - true - - - - - - AXI_Slave_Type - Memory_Slave - - - - true - - - - - - Use_AXI_ID - false - - - - false - - - - - - AXI_ID_Width - 4 - - - - false - - - - - - Memory_Type - True_Dual_Port_RAM - - - - true - - - - - - PRIM_type_to_Implement - BRAM - - - - true - - - - - - Enable_32bit_Address - true - - - - true - - - - - - ecctype - No_ECC - - - - false - - - - - - ECC - false - - - - false - - - - - - softecc - false - - - - false - - - - - - EN_SLEEP_PIN - false - - - - true - - - - - - EN_DEEPSLEEP_PIN - false - - - - false - - - - - - EN_SHUTDOWN_PIN - false - - - - false - - - - - - EN_ECC_PIPE - false - - - - false - - - - - - RD_ADDR_CHNG_A - false - - - - false - - - - - - RD_ADDR_CHNG_B - false - - - - false - - - - - - Use_Error_Injection_Pins - false - - - - false - - - - - - Error_Injection_Type - Single_Bit_Error_Injection - - - - false - - - - - - Use_Byte_Write_Enable - true - - - - false - - - - - - Byte_Size - 8 - - - - false - - - - - - Algorithm - Minimum_Area - - - - false - - - - - - Primitive - 8kx2 - - - - false - - - - - - Assume_Synchronous_Clk - false - - - - true - - - - - - Write_Width_A - 32 - - - - true - - - - - - Write_Depth_A - 4096 - - - - true - - - - - - Read_Width_A - 32 - - - - true - - - - - - Operating_Mode_A - WRITE_FIRST - - - - true - - - - - - Enable_A - Use_ENA_Pin - - - - false - - - - - - Write_Width_B - 32 - - - - true - - - - - - Read_Width_B - 32 - - - - true - - - - - - Operating_Mode_B - WRITE_FIRST - - - - true - - - - - - Enable_B - Use_ENB_Pin - - - - true - - - - - - Register_PortA_Output_of_Memory_Primitives - false - - - - true - - - - - - Register_PortA_Output_of_Memory_Core - false - - - - true - - - - - - Use_REGCEA_Pin - false - - - - false - - - - - - Register_PortB_Output_of_Memory_Primitives - false - - - - true - - - - - - Register_PortB_Output_of_Memory_Core - false - - - - true - - - - - - Use_REGCEB_Pin - false - - - - false - - - - - - register_porta_input_of_softecc - false - - - - false - - - - - - register_portb_output_of_softecc - false - - - - false - - - - - - Pipeline_Stages - 0 - - - - false - - - - - - Load_Init_File - false - - - - false - - - - - - Coe_File - no_coe_file_loaded - - - - false - - - - - - Fill_Remaining_Memory_Locations - false - - - - false - - - - - - Remaining_Memory_Locations - 0 - - - - false - - - - - - Use_RSTA_Pin - true - - - - true - - - - - - Reset_Memory_Latch_A - false - - - - false - - - - - - Reset_Priority_A - CE - - - - false - - - - - - Output_Reset_Value_A - 0 - - - - true - - - - - - Use_RSTB_Pin - true - - - - true - - - - - - Reset_Memory_Latch_B - false - - - - false - - - - - - Reset_Priority_B - CE - - - - true - - - - - - Output_Reset_Value_B - 0 - - - - true - - - - - - Reset_Type - SYNC - - - - false - - - - - - Additional_Inputs_for_Power_Estimation - false - - - - true - - - - - - Port_A_Clock - 100 - - - - true - - - - - - Port_A_Write_Rate - 50 - - - - true - - - - - - Port_B_Clock - 100 - - - - true - - - - - - Port_B_Write_Rate - 50 - - - - true - - - - - - Port_A_Enable_Rate - 100 - - - - true - - - - - - Port_B_Enable_Rate - 100 - - - - true - - - - - - Collision_Warnings - ALL - - - - false - - - - - - Disable_Collision_Warnings - false - - - - false - - - - - - Disable_Out_of_Range_Warnings - false - - - - false - - - - - - use_bram_block - BRAM_Controller - - - - true - - - - - - MEM_FILE - design_1_lmb_bram_0.mem - - - - true - - - - - - CTRL_ECC_ALGO - NONE - - - - true - - - - - - EN_SAFETY_CKT - true - - - - true - - - - - - READ_LATENCY_A - 1 - - - - false - - - - - - READ_LATENCY_B - 1 - - - - false - - - - - - - - Block Memory Generator - - XPM_MEMORY - - 4 - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xci b/hub_test/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xci deleted file mode 100644 index a9e2f91..0000000 --- a/hub_test/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xci +++ /dev/null @@ -1,1187 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_mdm_1_0 - - - - 100000000 - 0 - 0 - 0.000 - - 100000000 - 0 - 0 - 0.000 - design_1_Clk - 100000000 - 0 - 0 - 0.000 - 1 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 256 - 1 - 1 - 1 - 1 - 0.000 - AXI4 - READ_WRITE - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 256 - 1 - 1 - 1 - 1 - 0.000 - AXI4 - READ_WRITE - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 256 - 1 - 1 - 1 - 1 - 0.000 - AXI4 - READ_WRITE - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - - 32 - 100000000 - 1 - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xml b/hub_test/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xml deleted file mode 100644 index 66a925f..0000000 --- a/hub_test/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xml +++ /dev/null @@ -1,64308 +0,0 @@ - - - xilinx.com - customized_ip - design_1_mdm_1_0 - 1.0 - - - S_AXI - S_AXI - AXI4-Lite Interconnect - - - - - - - - - ARADDR - - - S_AXI_ARADDR - - - - - ARREADY - - - S_AXI_ARREADY - - - - - ARVALID - - - S_AXI_ARVALID - - - - - AWADDR - - - S_AXI_AWADDR - - - - - AWREADY - - - S_AXI_AWREADY - - - - - AWVALID - - - S_AXI_AWVALID - - - - - BREADY - - - S_AXI_BREADY - - - - - BRESP - - - S_AXI_BRESP - - - - - BVALID - - - S_AXI_BVALID - - - - - RDATA - - - S_AXI_RDATA - - - - - RREADY - - - S_AXI_RREADY - - - - - RRESP - - - S_AXI_RRESP - - - - - RVALID - - - S_AXI_RVALID - - - - - WDATA - - - S_AXI_WDATA - - - - - WREADY - - - S_AXI_WREADY - - - - - WSTRB - - - S_AXI_WSTRB - - - - - WVALID - - - S_AXI_WVALID - - - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 4 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 2 - - - none - - - - - NUM_WRITE_OUTSTANDING - 2 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - M_AXI - M_AXI - Master AXI4 Interface - - - - - - - - - ARADDR - - - M_AXI_ARADDR - - - - - ARBURST - - - M_AXI_ARBURST - - - - - ARCACHE - - - M_AXI_ARCACHE - - - - - ARID - - - M_AXI_ARID - - - - - ARLEN - - - M_AXI_ARLEN - - - - - ARLOCK - - - M_AXI_ARLOCK - - - - - ARPROT - - - M_AXI_ARPROT - - - - - ARQOS - - - M_AXI_ARQOS - - - - - ARREADY - - - M_AXI_ARREADY - - - - - ARSIZE - - - M_AXI_ARSIZE - - - - - ARVALID - - - M_AXI_ARVALID - - - - - AWADDR - - - M_AXI_AWADDR - - - - - AWBURST - - - M_AXI_AWBURST - - - - - AWCACHE - - - M_AXI_AWCACHE - - - - - AWID - - - M_AXI_AWID - - - - - AWLEN - - - M_AXI_AWLEN - - - - - AWLOCK - - - M_AXI_AWLOCK - - - - - AWPROT - - - M_AXI_AWPROT - - - - - AWQOS - - - M_AXI_AWQOS - - - - - AWREADY - - - M_AXI_AWREADY - - - - - AWSIZE - - - M_AXI_AWSIZE - - - - - AWVALID - - - M_AXI_AWVALID - - - - - BID - - - M_AXI_BID - - - - - BREADY - - - M_AXI_BREADY - - - - - BRESP - - - M_AXI_BRESP - - - - - BVALID - - - M_AXI_BVALID - - - - - RDATA - - - M_AXI_RDATA - - - - - RID - - - M_AXI_RID - - - - - RLAST - - - M_AXI_RLAST - - - - - RREADY - - - M_AXI_RREADY - - - - - RRESP - - - M_AXI_RRESP - - - - - RVALID - - - M_AXI_RVALID - - - - - WDATA - - - M_AXI_WDATA - - - - - WLAST - - - M_AXI_WLAST - - - - - WREADY - - - M_AXI_WREADY - - - - - WSTRB - - - M_AXI_WSTRB - - - - - WVALID - - - M_AXI_WVALID - - - - - - ID_WIDTH - 0 - - - READ_WRITE_MODE - READ_WRITE - - - SUPPORTS_NARROW_BURST - 0 - - - ADDR_WIDTH - 32 - - - PROTOCOL - AXI4 - - - AWUSER_WIDTH - 0 - - - ARUSER_WIDTH - 0 - - - WUSER_WIDTH - 0 - - - WUSER_BITS_PER_BYTE - 0 - - - RUSER_WIDTH - 0 - - - RUSER_BITS_PER_BYTE - 0 - - - BUSER_WIDTH - 0 - - - NUM_READ_OUTSTANDING - 1 - - - NUM_WRITE_OUTSTANDING - 1 - - - NUM_READ_THREADS - 1 - - - NUM_WRITE_THREADS - 1 - - - DATA_WIDTH - 32 - - - MAX_BURST_LENGTH - 32 - - - HAS_BURST - 1 - - - FREQ_HZ - 100000000 - - - none - - - - - HAS_LOCK - 1 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 1 - - - none - - - - - HAS_QOS - 1 - - - none - - - - - HAS_REGION - 1 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - LMB_0 - LMB_0 - Local Memory Bus 0 - - - - - - - - - ABUS - - - LMB_Data_Addr_0 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_0 - - - - - BE - - - LMB_Byte_Enable_0 - - - - - CE - - - LMB_CE_0 - - - - - READDBUS - - - LMB_Data_Read_0 - - - - - READSTROBE - - - LMB_Read_Strobe_0 - - - - - READY - - - LMB_Ready_0 - - - - - UE - - - LMB_UE_0 - - - - - WAIT - - - LMB_Wait_0 - - - - - WRITEDBUS - - - LMB_Data_Write_0 - - - - - WRITESTROBE - - - LMB_Write_Strobe_0 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_1 - LMB_1 - Local Memory Bus 1 - - - - - - - - - ABUS - - - LMB_Data_Addr_1 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_1 - - - - - BE - - - LMB_Byte_Enable_1 - - - - - CE - - - LMB_CE_1 - - - - - READDBUS - - - LMB_Data_Read_1 - - - - - READSTROBE - - - LMB_Read_Strobe_1 - - - - - READY - - - LMB_Ready_1 - - - - - UE - - - LMB_UE_1 - - - - - WAIT - - - LMB_Wait_1 - - - - - WRITEDBUS - - - LMB_Data_Write_1 - - - - - WRITESTROBE - - - LMB_Write_Strobe_1 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_2 - LMB_2 - Local Memory Bus 2 - - - - - - - - - ABUS - - - LMB_Data_Addr_2 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_2 - - - - - BE - - - LMB_Byte_Enable_2 - - - - - CE - - - LMB_CE_2 - - - - - READDBUS - - - LMB_Data_Read_2 - - - - - READSTROBE - - - LMB_Read_Strobe_2 - - - - - READY - - - LMB_Ready_2 - - - - - UE - - - LMB_UE_2 - - - - - WAIT - - - LMB_Wait_2 - - - - - WRITEDBUS - - - LMB_Data_Write_2 - - - - - WRITESTROBE - - - LMB_Write_Strobe_2 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_3 - LMB_3 - Local Memory Bus 3 - - - - - - - - - ABUS - - - LMB_Data_Addr_3 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_3 - - - - - BE - - - LMB_Byte_Enable_3 - - - - - CE - - - LMB_CE_3 - - - - - READDBUS - - - LMB_Data_Read_3 - - - - - READSTROBE - - - LMB_Read_Strobe_3 - - - - - READY - - - LMB_Ready_3 - - - - - UE - - - LMB_UE_3 - - - - - WAIT - - - LMB_Wait_3 - - - - - WRITEDBUS - - - LMB_Data_Write_3 - - - - - WRITESTROBE - - - LMB_Write_Strobe_3 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_4 - LMB_4 - Local Memory Bus 4 - - - - - - - - - ABUS - - - LMB_Data_Addr_4 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_4 - - - - - BE - - - LMB_Byte_Enable_4 - - - - - CE - - - LMB_CE_4 - - - - - READDBUS - - - LMB_Data_Read_4 - - - - - READSTROBE - - - LMB_Read_Strobe_4 - - - - - READY - - - LMB_Ready_4 - - - - - UE - - - LMB_UE_4 - - - - - WAIT - - - LMB_Wait_4 - - - - - WRITEDBUS - - - LMB_Data_Write_4 - - - - - WRITESTROBE - - - LMB_Write_Strobe_4 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_5 - LMB_5 - Local Memory Bus 5 - - - - - - - - - ABUS - - - LMB_Data_Addr_5 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_5 - - - - - BE - - - LMB_Byte_Enable_5 - - - - - CE - - - LMB_CE_5 - - - - - READDBUS - - - LMB_Data_Read_5 - - - - - READSTROBE - - - LMB_Read_Strobe_5 - - - - - READY - - - LMB_Ready_5 - - - - - UE - - - LMB_UE_5 - - - - - WAIT - - - LMB_Wait_5 - - - - - WRITEDBUS - - - LMB_Data_Write_5 - - - - - WRITESTROBE - - - LMB_Write_Strobe_5 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_6 - LMB_6 - Local Memory Bus 6 - - - - - - - - - ABUS - - - LMB_Data_Addr_6 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_6 - - - - - BE - - - LMB_Byte_Enable_6 - - - - - CE - - - LMB_CE_6 - - - - - READDBUS - - - LMB_Data_Read_6 - - - - - READSTROBE - - - LMB_Read_Strobe_6 - - - - - READY - - - LMB_Ready_6 - - - - - UE - - - LMB_UE_6 - - - - - WAIT - - - LMB_Wait_6 - - - - - WRITEDBUS - - - LMB_Data_Write_6 - - - - - WRITESTROBE - - - LMB_Write_Strobe_6 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_7 - LMB_7 - Local Memory Bus 7 - - - - - - - - - ABUS - - - LMB_Data_Addr_7 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_7 - - - - - BE - - - LMB_Byte_Enable_7 - - - - - CE - - - LMB_CE_7 - - - - - READDBUS - - - LMB_Data_Read_7 - - - - - READSTROBE - - - LMB_Read_Strobe_7 - - - - - READY - - - LMB_Ready_7 - - - - - UE - - - LMB_UE_7 - - - - - WAIT - - - LMB_Wait_7 - - - - - WRITEDBUS - - - LMB_Data_Write_7 - - - - - WRITESTROBE - - - LMB_Write_Strobe_7 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_8 - LMB_8 - Local Memory Bus 8 - - - - - - - - - ABUS - - - LMB_Data_Addr_8 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_8 - - - - - BE - - - LMB_Byte_Enable_8 - - - - - CE - - - LMB_CE_8 - - - - - READDBUS - - - LMB_Data_Read_8 - - - - - READSTROBE - - - LMB_Read_Strobe_8 - - - - - READY - - - LMB_Ready_8 - - - - - UE - - - LMB_UE_8 - - - - - WAIT - - - LMB_Wait_8 - - - - - WRITEDBUS - - - LMB_Data_Write_8 - - - - - WRITESTROBE - - - LMB_Write_Strobe_8 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_9 - LMB_9 - Local Memory Bus 9 - - - - - - - - - ABUS - - - LMB_Data_Addr_9 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_9 - - - - - BE - - - LMB_Byte_Enable_9 - - - - - CE - - - LMB_CE_9 - - - - - READDBUS - - - LMB_Data_Read_9 - - - - - READSTROBE - - - LMB_Read_Strobe_9 - - - - - READY - - - LMB_Ready_9 - - - - - UE - - - LMB_UE_9 - - - - - WAIT - - - LMB_Wait_9 - - - - - WRITEDBUS - - - LMB_Data_Write_9 - - - - - WRITESTROBE - - - LMB_Write_Strobe_9 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_10 - LMB_10 - Local Memory Bus 10 - - - - - - - - - ABUS - - - LMB_Data_Addr_10 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_10 - - - - - BE - - - LMB_Byte_Enable_10 - - - - - CE - - - LMB_CE_10 - - - - - READDBUS - - - LMB_Data_Read_10 - - - - - READSTROBE - - - LMB_Read_Strobe_10 - - - - - READY - - - LMB_Ready_10 - - - - - UE - - - LMB_UE_10 - - - - - WAIT - - - LMB_Wait_10 - - - - - WRITEDBUS - - - LMB_Data_Write_10 - - - - - WRITESTROBE - - - LMB_Write_Strobe_10 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_11 - LMB_11 - Local Memory Bus 11 - - - - - - - - - ABUS - - - LMB_Data_Addr_11 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_11 - - - - - BE - - - LMB_Byte_Enable_11 - - - - - CE - - - LMB_CE_11 - - - - - READDBUS - - - LMB_Data_Read_11 - - - - - READSTROBE - - - LMB_Read_Strobe_11 - - - - - READY - - - LMB_Ready_11 - - - - - UE - - - LMB_UE_11 - - - - - WAIT - - - LMB_Wait_11 - - - - - WRITEDBUS - - - LMB_Data_Write_11 - - - - - WRITESTROBE - - - LMB_Write_Strobe_11 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_12 - LMB_12 - Local Memory Bus 12 - - - - - - - - - ABUS - - - LMB_Data_Addr_12 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_12 - - - - - BE - - - LMB_Byte_Enable_12 - - - - - CE - - - LMB_CE_12 - - - - - READDBUS - - - LMB_Data_Read_12 - - - - - READSTROBE - - - LMB_Read_Strobe_12 - - - - - READY - - - LMB_Ready_12 - - - - - UE - - - LMB_UE_12 - - - - - WAIT - - - LMB_Wait_12 - - - - - WRITEDBUS - - - LMB_Data_Write_12 - - - - - WRITESTROBE - - - LMB_Write_Strobe_12 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_13 - LMB_13 - Local Memory Bus 13 - - - - - - - - - ABUS - - - LMB_Data_Addr_13 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_13 - - - - - BE - - - LMB_Byte_Enable_13 - - - - - CE - - - LMB_CE_13 - - - - - READDBUS - - - LMB_Data_Read_13 - - - - - READSTROBE - - - LMB_Read_Strobe_13 - - - - - READY - - - LMB_Ready_13 - - - - - UE - - - LMB_UE_13 - - - - - WAIT - - - LMB_Wait_13 - - - - - WRITEDBUS - - - LMB_Data_Write_13 - - - - - WRITESTROBE - - - LMB_Write_Strobe_13 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_14 - LMB_14 - Local Memory Bus 14 - - - - - - - - - ABUS - - - LMB_Data_Addr_14 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_14 - - - - - BE - - - LMB_Byte_Enable_14 - - - - - CE - - - LMB_CE_14 - - - - - READDBUS - - - LMB_Data_Read_14 - - - - - READSTROBE - - - LMB_Read_Strobe_14 - - - - - READY - - - LMB_Ready_14 - - - - - UE - - - LMB_UE_14 - - - - - WAIT - - - LMB_Wait_14 - - - - - WRITEDBUS - - - LMB_Data_Write_14 - - - - - WRITESTROBE - - - LMB_Write_Strobe_14 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_15 - LMB_15 - Local Memory Bus 15 - - - - - - - - - ABUS - - - LMB_Data_Addr_15 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_15 - - - - - BE - - - LMB_Byte_Enable_15 - - - - - CE - - - LMB_CE_15 - - - - - READDBUS - - - LMB_Data_Read_15 - - - - - READSTROBE - - - LMB_Read_Strobe_15 - - - - - READY - - - LMB_Ready_15 - - - - - UE - - - LMB_UE_15 - - - - - WAIT - - - LMB_Wait_15 - - - - - WRITEDBUS - - - LMB_Data_Write_15 - - - - - WRITESTROBE - - - LMB_Write_Strobe_15 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_16 - LMB_16 - Local Memory Bus 16 - - - - - - - - - ABUS - - - LMB_Data_Addr_16 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_16 - - - - - BE - - - LMB_Byte_Enable_16 - - - - - CE - - - LMB_CE_16 - - - - - READDBUS - - - LMB_Data_Read_16 - - - - - READSTROBE - - - LMB_Read_Strobe_16 - - - - - READY - - - LMB_Ready_16 - - - - - UE - - - LMB_UE_16 - - - - - WAIT - - - LMB_Wait_16 - - - - - WRITEDBUS - - - LMB_Data_Write_16 - - - - - WRITESTROBE - - - LMB_Write_Strobe_16 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_17 - LMB_17 - Local Memory Bus 17 - - - - - - - - - ABUS - - - LMB_Data_Addr_17 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_17 - - - - - BE - - - LMB_Byte_Enable_17 - - - - - CE - - - LMB_CE_17 - - - - - READDBUS - - - LMB_Data_Read_17 - - - - - READSTROBE - - - LMB_Read_Strobe_17 - - - - - READY - - - LMB_Ready_17 - - - - - UE - - - LMB_UE_17 - - - - - WAIT - - - LMB_Wait_17 - - - - - WRITEDBUS - - - LMB_Data_Write_17 - - - - - WRITESTROBE - - - LMB_Write_Strobe_17 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_18 - LMB_18 - Local Memory Bus 18 - - - - - - - - - ABUS - - - LMB_Data_Addr_18 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_18 - - - - - BE - - - LMB_Byte_Enable_18 - - - - - CE - - - LMB_CE_18 - - - - - READDBUS - - - LMB_Data_Read_18 - - - - - READSTROBE - - - LMB_Read_Strobe_18 - - - - - READY - - - LMB_Ready_18 - - - - - UE - - - LMB_UE_18 - - - - - WAIT - - - LMB_Wait_18 - - - - - WRITEDBUS - - - LMB_Data_Write_18 - - - - - WRITESTROBE - - - LMB_Write_Strobe_18 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_19 - LMB_19 - Local Memory Bus 19 - - - - - - - - - ABUS - - - LMB_Data_Addr_19 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_19 - - - - - BE - - - LMB_Byte_Enable_19 - - - - - CE - - - LMB_CE_19 - - - - - READDBUS - - - LMB_Data_Read_19 - - - - - READSTROBE - - - LMB_Read_Strobe_19 - - - - - READY - - - LMB_Ready_19 - - - - - UE - - - LMB_UE_19 - - - - - WAIT - - - LMB_Wait_19 - - - - - WRITEDBUS - - - LMB_Data_Write_19 - - - - - WRITESTROBE - - - LMB_Write_Strobe_19 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_20 - LMB_20 - Local Memory Bus 20 - - - - - - - - - ABUS - - - LMB_Data_Addr_20 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_20 - - - - - BE - - - LMB_Byte_Enable_20 - - - - - CE - - - LMB_CE_20 - - - - - READDBUS - - - LMB_Data_Read_20 - - - - - READSTROBE - - - LMB_Read_Strobe_20 - - - - - READY - - - LMB_Ready_20 - - - - - UE - - - LMB_UE_20 - - - - - WAIT - - - LMB_Wait_20 - - - - - WRITEDBUS - - - LMB_Data_Write_20 - - - - - WRITESTROBE - - - LMB_Write_Strobe_20 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_21 - LMB_21 - Local Memory Bus 21 - - - - - - - - - ABUS - - - LMB_Data_Addr_21 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_21 - - - - - BE - - - LMB_Byte_Enable_21 - - - - - CE - - - LMB_CE_21 - - - - - READDBUS - - - LMB_Data_Read_21 - - - - - READSTROBE - - - LMB_Read_Strobe_21 - - - - - READY - - - LMB_Ready_21 - - - - - UE - - - LMB_UE_21 - - - - - WAIT - - - LMB_Wait_21 - - - - - WRITEDBUS - - - LMB_Data_Write_21 - - - - - WRITESTROBE - - - LMB_Write_Strobe_21 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_22 - LMB_22 - Local Memory Bus 22 - - - - - - - - - ABUS - - - LMB_Data_Addr_22 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_22 - - - - - BE - - - LMB_Byte_Enable_22 - - - - - CE - - - LMB_CE_22 - - - - - READDBUS - - - LMB_Data_Read_22 - - - - - READSTROBE - - - LMB_Read_Strobe_22 - - - - - READY - - - LMB_Ready_22 - - - - - UE - - - LMB_UE_22 - - - - - WAIT - - - LMB_Wait_22 - - - - - WRITEDBUS - - - LMB_Data_Write_22 - - - - - WRITESTROBE - - - LMB_Write_Strobe_22 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_23 - LMB_23 - Local Memory Bus 23 - - - - - - - - - ABUS - - - LMB_Data_Addr_23 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_23 - - - - - BE - - - LMB_Byte_Enable_23 - - - - - CE - - - LMB_CE_23 - - - - - READDBUS - - - LMB_Data_Read_23 - - - - - READSTROBE - - - LMB_Read_Strobe_23 - - - - - READY - - - LMB_Ready_23 - - - - - UE - - - LMB_UE_23 - - - - - WAIT - - - LMB_Wait_23 - - - - - WRITEDBUS - - - LMB_Data_Write_23 - - - - - WRITESTROBE - - - LMB_Write_Strobe_23 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_24 - LMB_24 - Local Memory Bus 24 - - - - - - - - - ABUS - - - LMB_Data_Addr_24 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_24 - - - - - BE - - - LMB_Byte_Enable_24 - - - - - CE - - - LMB_CE_24 - - - - - READDBUS - - - LMB_Data_Read_24 - - - - - READSTROBE - - - LMB_Read_Strobe_24 - - - - - READY - - - LMB_Ready_24 - - - - - UE - - - LMB_UE_24 - - - - - WAIT - - - LMB_Wait_24 - - - - - WRITEDBUS - - - LMB_Data_Write_24 - - - - - WRITESTROBE - - - LMB_Write_Strobe_24 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_25 - LMB_25 - Local Memory Bus 25 - - - - - - - - - ABUS - - - LMB_Data_Addr_25 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_25 - - - - - BE - - - LMB_Byte_Enable_25 - - - - - CE - - - LMB_CE_25 - - - - - READDBUS - - - LMB_Data_Read_25 - - - - - READSTROBE - - - LMB_Read_Strobe_25 - - - - - READY - - - LMB_Ready_25 - - - - - UE - - - LMB_UE_25 - - - - - WAIT - - - LMB_Wait_25 - - - - - WRITEDBUS - - - LMB_Data_Write_25 - - - - - WRITESTROBE - - - LMB_Write_Strobe_25 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_26 - LMB_26 - Local Memory Bus 26 - - - - - - - - - ABUS - - - LMB_Data_Addr_26 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_26 - - - - - BE - - - LMB_Byte_Enable_26 - - - - - CE - - - LMB_CE_26 - - - - - READDBUS - - - LMB_Data_Read_26 - - - - - READSTROBE - - - LMB_Read_Strobe_26 - - - - - READY - - - LMB_Ready_26 - - - - - UE - - - LMB_UE_26 - - - - - WAIT - - - LMB_Wait_26 - - - - - WRITEDBUS - - - LMB_Data_Write_26 - - - - - WRITESTROBE - - - LMB_Write_Strobe_26 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_27 - LMB_27 - Local Memory Bus 27 - - - - - - - - - ABUS - - - LMB_Data_Addr_27 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_27 - - - - - BE - - - LMB_Byte_Enable_27 - - - - - CE - - - LMB_CE_27 - - - - - READDBUS - - - LMB_Data_Read_27 - - - - - READSTROBE - - - LMB_Read_Strobe_27 - - - - - READY - - - LMB_Ready_27 - - - - - UE - - - LMB_UE_27 - - - - - WAIT - - - LMB_Wait_27 - - - - - WRITEDBUS - - - LMB_Data_Write_27 - - - - - WRITESTROBE - - - LMB_Write_Strobe_27 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_28 - LMB_28 - Local Memory Bus 28 - - - - - - - - - ABUS - - - LMB_Data_Addr_28 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_28 - - - - - BE - - - LMB_Byte_Enable_28 - - - - - CE - - - LMB_CE_28 - - - - - READDBUS - - - LMB_Data_Read_28 - - - - - READSTROBE - - - LMB_Read_Strobe_28 - - - - - READY - - - LMB_Ready_28 - - - - - UE - - - LMB_UE_28 - - - - - WAIT - - - LMB_Wait_28 - - - - - WRITEDBUS - - - LMB_Data_Write_28 - - - - - WRITESTROBE - - - LMB_Write_Strobe_28 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_29 - LMB_29 - Local Memory Bus 29 - - - - - - - - - ABUS - - - LMB_Data_Addr_29 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_29 - - - - - BE - - - LMB_Byte_Enable_29 - - - - - CE - - - LMB_CE_29 - - - - - READDBUS - - - LMB_Data_Read_29 - - - - - READSTROBE - - - LMB_Read_Strobe_29 - - - - - READY - - - LMB_Ready_29 - - - - - UE - - - LMB_UE_29 - - - - - WAIT - - - LMB_Wait_29 - - - - - WRITEDBUS - - - LMB_Data_Write_29 - - - - - WRITESTROBE - - - LMB_Write_Strobe_29 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_30 - LMB_30 - Local Memory Bus 30 - - - - - - - - - ABUS - - - LMB_Data_Addr_30 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_30 - - - - - BE - - - LMB_Byte_Enable_30 - - - - - CE - - - LMB_CE_30 - - - - - READDBUS - - - LMB_Data_Read_30 - - - - - READSTROBE - - - LMB_Read_Strobe_30 - - - - - READY - - - LMB_Ready_30 - - - - - UE - - - LMB_UE_30 - - - - - WAIT - - - LMB_Wait_30 - - - - - WRITEDBUS - - - LMB_Data_Write_30 - - - - - WRITESTROBE - - - LMB_Write_Strobe_30 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - LMB_31 - LMB_31 - Local Memory Bus 31 - - - - - - - - - ABUS - - - LMB_Data_Addr_31 - - - - - ADDRSTROBE - - - LMB_Addr_Strobe_31 - - - - - BE - - - LMB_Byte_Enable_31 - - - - - CE - - - LMB_CE_31 - - - - - READDBUS - - - LMB_Data_Read_31 - - - - - READSTROBE - - - LMB_Read_Strobe_31 - - - - - READY - - - LMB_Ready_31 - - - - - UE - - - LMB_UE_31 - - - - - WAIT - - - LMB_Wait_31 - - - - - WRITEDBUS - - - LMB_Data_Write_31 - - - - - WRITESTROBE - - - LMB_Write_Strobe_31 - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_WRITE - - - - - - false - - - - - - M_AXIS - M_AXIS - External Trace AXI4 Stream Interface - - - - - - - TDATA - - - M_AXIS_TDATA - - - - - TID - - - M_AXIS_TID - - - - - TREADY - - - M_AXIS_TREADY - - - - - TVALID - - - M_AXIS_TVALID - - - - - - TDATA_NUM_BYTES - 1 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - TRACE - TRACE - External Trace Interface - - - - - - - CLK_I - - - TRACE_CLK - - - - - CLK_O - - - TRACE_CLK_OUT - - - - - CTL - - - TRACE_CTL - - - - - DATA - - - TRACE_DATA - - - - - - - false - - - - - - CLK.S_AXI_ACLK - S_AXI_ACLK - AXI4-Lite Interconnect Clock Input - - - - - - - CLK - - - S_AXI_ACLK - - - - - - ASSOCIATED_BUSIF - S_AXI:MBDEBUG_AXI_0:MBDEBUG_AXI_1:MBDEBUG_AXI_2:MBDEBUG_AXI_3:MBDEBUG_AXI_4:MBDEBUG_AXI_5:MBDEBUG_AXI_6:MBDEBUG_AXI_7:MBDEBUG_AXI_8:MBDEBUG_AXI_9:MBDEBUG_AXI_10:MBDEBUG_AXI_11:MBDEBUG_AXI_12:MBDEBUG_AXI_13:MBDEBUG_AXI_14:MBDEBUG_AXI_15:MBDEBUG_AXI_16:MBDEBUG_AXI_17:MBDEBUG_AXI_18:MBDEBUG_AXI_19:MBDEBUG_AXI_20:MBDEBUG_AXI_21:MBDEBUG_AXI_22:MBDEBUG_AXI_23:MBDEBUG_AXI_24:MBDEBUG_AXI_25:MBDEBUG_AXI_26:MBDEBUG_AXI_27:MBDEBUG_AXI_28:MBDEBUG_AXI_29:MBDEBUG_AXI_30:MBDEBUG_AXI_31 - - - ASSOCIATED_RESET - S_AXI_ARESETN - - - FREQ_HZ - S_AXI_ACLK frequency - S_AXI_ACLK frequency - 100000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - RST.S_AXI_ARESETN - S_AXI_ARESETN - AXI4-Lite Interconnect Reset Input - - - - - - - RST - - - S_AXI_ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - CLK.M_AXI_ACLK - M_AXI_ACLK - AXI4 Interconnect Clock Input - - - - - - - CLK - - - M_AXI_ACLK - - - - - - ASSOCIATED_BUSIF - M_AXI:LMB_0:LMB_1:LMB_2:LMB_3:LMB_4:LMB_5:LMB_6:LMB_7:LMB_8:LMB_9:LMB_10:LMB_11:LMB_12:LMB_13:LMB_14:LMB_15:LMB_16:LMB_17:LMB_18:LMB_19:LMB_20:LMB_21:LMB_22:LMB_23:LMB_24:LMB_25:LMB_26:LMB_27:LMB_28:LMB_29:LMB_30:LMB_31 - - - ASSOCIATED_RESET - M_AXI_ARESETN - - - FREQ_HZ - M_AXI_ACLK frequency - M_AXI_ACLK frequency - 100000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - RST.M_AXI_ARESETN - M_AXI_ARESETN - AXI4 Interconnect Reset Input - - - - - - - RST - - - M_AXI_ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - CLK.M_AXIS_ACLK - M_AXIS_ACLK - AXI4 Stream Clock Input - - - - - - - CLK - - - M_AXIS_ACLK - - - - - - ASSOCIATED_BUSIF - M_AXIS - - - ASSOCIATED_RESET - M_AXIS_ARESETN - - - FREQ_HZ - M_AXIS_ACLK frequency - M_AXIS_ACLK frequency - 100000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - RST.M_AXIS_ARESETN - M_AXIS_ARESETN - AXI4 Stream Reset Input - - - - - - - RST - - - M_AXIS_ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - RST.Debug_SYS_Rst - Debug_SYS_Rst - Debug System Reset Output - - - - - - - RST - - - Debug_SYS_Rst - - - - - - POLARITY - ACTIVE_HIGH - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - MBDEBUG_0 - MBDEBUG_0 - MicroBlaze Debug Interface 0 - - - - - - - ARADDR - - - Dbg_ARADDR_0 - - - - - ARREADY - - - Dbg_ARREADY_0 - - - - - ARVALID - - - Dbg_ARVALID_0 - - - - - AWADDR - - - Dbg_AWADDR_0 - - - - - AWREADY - - - Dbg_AWREADY_0 - - - - - AWVALID - - - Dbg_AWVALID_0 - - - - - BREADY - - - Dbg_BREADY_0 - - - - - BRESP - - - Dbg_BRESP_0 - - - - - BVALID - - - Dbg_BVALID_0 - - - - - CAPTURE - - - Dbg_Capture_0 - - - - - CLK - - - Dbg_Clk_0 - - - - - DISABLE - - - Dbg_Disable_0 - - - - - RDATA - - - Dbg_RDATA_0 - - - - - REG_EN - - - Dbg_Reg_En_0 - - - - - RREADY - - - Dbg_RREADY_0 - - - - - RRESP - - - Dbg_RRESP_0 - - - - - RST - - - Dbg_Rst_0 - - - - - RVALID - - - Dbg_RVALID_0 - - - - - SHIFT - - - Dbg_Shift_0 - - - - - TDI - - - Dbg_TDI_0 - - - - - TDO - - - Dbg_TDO_0 - - - - - TRCLK - - - Dbg_TrClk_0 - - - - - TRDATA - - - Dbg_TrData_0 - - - - - TRIG_ACK_IN - - - Dbg_Trig_Ack_In_0 - - - - - TRIG_ACK_OUT - - - Dbg_Trig_Ack_Out_0 - - - - - TRIG_IN - - - Dbg_Trig_In_0 - - - - - TRIG_OUT - - - Dbg_Trig_Out_0 - - - - - TRREADY - - - Dbg_TrReady_0 - - - - - TRVALID - - - Dbg_TrValid_0 - - - - - UPDATE - - - Dbg_Update_0 - - - - - WDATA - - - Dbg_WDATA_0 - - - - - WREADY - - - Dbg_WREADY_0 - - - - - WVALID - - - Dbg_WVALID_0 - - - - - - - true - - - - - - MBDEBUG_1 - MBDEBUG_1 - MicroBlaze Debug Interface 1 - - - - - - - ARADDR - - - Dbg_ARADDR_1 - - - - - ARREADY - - - Dbg_ARREADY_1 - - - - - ARVALID - - - Dbg_ARVALID_1 - - - - - AWADDR - - - Dbg_AWADDR_1 - - - - - AWREADY - - - Dbg_AWREADY_1 - - - - - AWVALID - - - Dbg_AWVALID_1 - - - - - BREADY - - - Dbg_BREADY_1 - - - - - BRESP - - - Dbg_BRESP_1 - - - - - BVALID - - - Dbg_BVALID_1 - - - - - CAPTURE - - - Dbg_Capture_1 - - - - - CLK - - - Dbg_Clk_1 - - - - - DISABLE - - - Dbg_Disable_1 - - - - - RDATA - - - Dbg_RDATA_1 - - - - - REG_EN - - - Dbg_Reg_En_1 - - - - - RREADY - - - Dbg_RREADY_1 - - - - - RRESP - - - Dbg_RRESP_1 - - - - - RST - - - Dbg_Rst_1 - - - - - RVALID - - - Dbg_RVALID_1 - - - - - SHIFT - - - Dbg_Shift_1 - - - - - TDI - - - Dbg_TDI_1 - - - - - TDO - - - Dbg_TDO_1 - - - - - TRCLK - - - Dbg_TrClk_1 - - - - - TRDATA - - - Dbg_TrData_1 - - - - - TRIG_ACK_IN - - - Dbg_Trig_Ack_In_1 - - - - - TRIG_ACK_OUT - - - Dbg_Trig_Ack_Out_1 - - - - - TRIG_IN - - - Dbg_Trig_In_1 - - - - - TRIG_OUT - - - Dbg_Trig_Out_1 - - - - - TRREADY - - - Dbg_TrReady_1 - - - - - TRVALID - - - Dbg_TrValid_1 - - - - - UPDATE - - - Dbg_Update_1 - - - - - WDATA - - - Dbg_WDATA_1 - - - - - WREADY - - - Dbg_WREADY_1 - - - - - WVALID - - - Dbg_WVALID_1 - - - - - - - false - - - - - - MBDEBUG_2 - MBDEBUG_2 - MicroBlaze Debug Interface 2 - - - - - - - ARADDR - - - Dbg_ARADDR_2 - - - - - ARREADY - - - Dbg_ARREADY_2 - - - - - ARVALID - - - Dbg_ARVALID_2 - - - - - AWADDR - - - Dbg_AWADDR_2 - - - - - AWREADY - - - Dbg_AWREADY_2 - - - - - AWVALID - - - Dbg_AWVALID_2 - - - - - BREADY - - - Dbg_BREADY_2 - - - - - BRESP - - - Dbg_BRESP_2 - - - - - BVALID - - - Dbg_BVALID_2 - - - - - CAPTURE - - - Dbg_Capture_2 - - - - - CLK - - - Dbg_Clk_2 - - - - - DISABLE - - - Dbg_Disable_2 - - - - - RDATA - - - Dbg_RDATA_2 - - - - - REG_EN - - - Dbg_Reg_En_2 - - - - - RREADY - - - Dbg_RREADY_2 - - - - - RRESP - - - Dbg_RRESP_2 - - - - - RST - - - Dbg_Rst_2 - - - - - RVALID - - - Dbg_RVALID_2 - - - - - SHIFT - - - Dbg_Shift_2 - - - - - TDI - - - Dbg_TDI_2 - - - - - TDO - - - Dbg_TDO_2 - - - - - TRCLK - - - Dbg_TrClk_2 - - - - - TRDATA - - - Dbg_TrData_2 - - - - - TRIG_ACK_IN - - - Dbg_Trig_Ack_In_2 - - - - - TRIG_ACK_OUT - - - Dbg_Trig_Ack_Out_2 - - - - - TRIG_IN - - - Dbg_Trig_In_2 - - - - - TRIG_OUT - - - Dbg_Trig_Out_2 - - - - - TRREADY - - - Dbg_TrReady_2 - - - - - TRVALID - - - Dbg_TrValid_2 - - - - - UPDATE - - - Dbg_Update_2 - - - - - WDATA - - - Dbg_WDATA_2 - - - - - WREADY - - - Dbg_WREADY_2 - - - - - WVALID - - - Dbg_WVALID_2 - - - - - - - false - - - - - - MBDEBUG_3 - MBDEBUG_3 - MicroBlaze Debug Interface 3 - - - - - - - ARADDR - - - Dbg_ARADDR_3 - - - - - ARREADY - - - Dbg_ARREADY_3 - - - - - ARVALID - - - Dbg_ARVALID_3 - - - - - AWADDR - - - Dbg_AWADDR_3 - - - - - AWREADY - - - Dbg_AWREADY_3 - - - - - AWVALID - - - Dbg_AWVALID_3 - - - - - BREADY - - - Dbg_BREADY_3 - - - - - BRESP - - - Dbg_BRESP_3 - - - - - BVALID - - - Dbg_BVALID_3 - - - - - CAPTURE - - - Dbg_Capture_3 - - - - - CLK - - - Dbg_Clk_3 - - - - - DISABLE - - - Dbg_Disable_3 - - - - - RDATA - - - Dbg_RDATA_3 - - - - - REG_EN - - - Dbg_Reg_En_3 - - - - - RREADY - - - Dbg_RREADY_3 - - - - - RRESP - - - Dbg_RRESP_3 - - - - - RST - - - Dbg_Rst_3 - - - - - RVALID - - - Dbg_RVALID_3 - - - - - SHIFT - - - Dbg_Shift_3 - - - - - TDI - - - Dbg_TDI_3 - - - - - TDO - - - Dbg_TDO_3 - - - - - TRCLK - - - Dbg_TrClk_3 - - - - - TRDATA - - - Dbg_TrData_3 - - - - - TRIG_ACK_IN - - - Dbg_Trig_Ack_In_3 - - - - - TRIG_ACK_OUT - - - Dbg_Trig_Ack_Out_3 - - - - - TRIG_IN - - - Dbg_Trig_In_3 - - - - - TRIG_OUT - - - Dbg_Trig_Out_3 - - - - - TRREADY - - - Dbg_TrReady_3 - - - - - TRVALID - - - Dbg_TrValid_3 - - - - - UPDATE - - - Dbg_Update_3 - - - - - WDATA - - - Dbg_WDATA_3 - - - - - WREADY - - - Dbg_WREADY_3 - - - - - WVALID - - - Dbg_WVALID_3 - - - - - - - false - - - - - - MBDEBUG_4 - MBDEBUG_4 - MicroBlaze Debug Interface 4 - - - - - - - ARADDR - - - Dbg_ARADDR_4 - - - - - ARREADY - - - Dbg_ARREADY_4 - - - - - ARVALID - - - Dbg_ARVALID_4 - - - - - AWADDR - - - Dbg_AWADDR_4 - - - - - AWREADY - - - Dbg_AWREADY_4 - - - - - AWVALID - - - Dbg_AWVALID_4 - - - - - BREADY - - - Dbg_BREADY_4 - - - - - BRESP - - - Dbg_BRESP_4 - - - - - BVALID - - - Dbg_BVALID_4 - - - - - CAPTURE - - - Dbg_Capture_4 - - - - - CLK - - - Dbg_Clk_4 - - - - - DISABLE - - - Dbg_Disable_4 - - - - - RDATA - - - Dbg_RDATA_4 - - - - - REG_EN - - - Dbg_Reg_En_4 - - - - - RREADY - - - Dbg_RREADY_4 - - - - - RRESP - - - Dbg_RRESP_4 - - - - - RST - - - Dbg_Rst_4 - - - - - RVALID - - - Dbg_RVALID_4 - - - - - SHIFT - - - Dbg_Shift_4 - - - - - TDI - - - Dbg_TDI_4 - - - - - TDO - - - Dbg_TDO_4 - - - - - TRCLK - - - Dbg_TrClk_4 - - - - - TRDATA - - - Dbg_TrData_4 - - - - - TRIG_ACK_IN - - - Dbg_Trig_Ack_In_4 - - - - - TRIG_ACK_OUT - - - Dbg_Trig_Ack_Out_4 - - - - - TRIG_IN - - - Dbg_Trig_In_4 - - - - - TRIG_OUT - - - Dbg_Trig_Out_4 - - - - - TRREADY - - - Dbg_TrReady_4 - - - - - TRVALID - - - Dbg_TrValid_4 - - - - - UPDATE - - - Dbg_Update_4 - - - - - WDATA - - - Dbg_WDATA_4 - - - - - WREADY - - - Dbg_WREADY_4 - - - - - WVALID - - - Dbg_WVALID_4 - - - - - - - false - - - - - - MBDEBUG_5 - MBDEBUG_5 - MicroBlaze Debug Interface 5 - - - - - - - ARADDR - - - Dbg_ARADDR_5 - - - - - ARREADY - - - Dbg_ARREADY_5 - - - - - ARVALID - - - Dbg_ARVALID_5 - - - - - AWADDR - - - Dbg_AWADDR_5 - - - - - AWREADY - - - Dbg_AWREADY_5 - - - - - AWVALID - - - Dbg_AWVALID_5 - - - - - BREADY - - - Dbg_BREADY_5 - - - - - BRESP - - - Dbg_BRESP_5 - - - - - BVALID - - - Dbg_BVALID_5 - - - - - CAPTURE - - - Dbg_Capture_5 - - - - - CLK - - - Dbg_Clk_5 - - - - - DISABLE - - - Dbg_Disable_5 - - - - - RDATA - - - Dbg_RDATA_5 - - - - - REG_EN - - - Dbg_Reg_En_5 - - - - - RREADY - - - Dbg_RREADY_5 - - - - - RRESP - - - Dbg_RRESP_5 - - - - - RST - - - Dbg_Rst_5 - - - - - RVALID - - - Dbg_RVALID_5 - - - - - SHIFT - - - Dbg_Shift_5 - - - - - TDI - - - Dbg_TDI_5 - - - - - TDO - - - Dbg_TDO_5 - - - - - TRCLK - - - Dbg_TrClk_5 - - - - - TRDATA - - - Dbg_TrData_5 - - - - - TRIG_ACK_IN - - - Dbg_Trig_Ack_In_5 - - - - - TRIG_ACK_OUT - - - Dbg_Trig_Ack_Out_5 - - - - - TRIG_IN - - - Dbg_Trig_In_5 - - - - - TRIG_OUT - - - Dbg_Trig_Out_5 - - - - - TRREADY - - - Dbg_TrReady_5 - - - - - TRVALID - - - Dbg_TrValid_5 - - - - - UPDATE - - - Dbg_Update_5 - - - - - WDATA - - - Dbg_WDATA_5 - - - - - WREADY - - - Dbg_WREADY_5 - - - - - WVALID - - - Dbg_WVALID_5 - - - - - - - false - - - - - - MBDEBUG_6 - MBDEBUG_6 - MicroBlaze Debug Interface 6 - - - - - - - ARADDR - - - Dbg_ARADDR_6 - - - - - ARREADY - - - Dbg_ARREADY_6 - - - - - ARVALID - - - Dbg_ARVALID_6 - - - - - AWADDR - - - Dbg_AWADDR_6 - - - - - AWREADY - - - Dbg_AWREADY_6 - - - - - AWVALID - - - Dbg_AWVALID_6 - - - - - BREADY - - - Dbg_BREADY_6 - - - - - BRESP - - - Dbg_BRESP_6 - - - - - BVALID - - - Dbg_BVALID_6 - - - - - CAPTURE - - - Dbg_Capture_6 - - - - - CLK - - - Dbg_Clk_6 - - - - - DISABLE - - - Dbg_Disable_6 - - - - - RDATA - - - Dbg_RDATA_6 - - - - - REG_EN - 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Dbg_Trig_In_8 - - - - - TRIG_OUT - - - Dbg_Trig_Out_8 - - - - - TRREADY - - - Dbg_TrReady_8 - - - - - TRVALID - - - Dbg_TrValid_8 - - - - - UPDATE - - - Dbg_Update_8 - - - - - WDATA - - - Dbg_WDATA_8 - - - - - WREADY - - - Dbg_WREADY_8 - - - - - WVALID - - - Dbg_WVALID_8 - - - - - - - false - - - - - - MBDEBUG_9 - MBDEBUG_9 - MicroBlaze Debug Interface 9 - - - - - - - ARADDR - - - Dbg_ARADDR_9 - - - - - ARREADY - - - Dbg_ARREADY_9 - - - - - ARVALID - - - Dbg_ARVALID_9 - - - - - AWADDR - - - Dbg_AWADDR_9 - - - - - AWREADY - - - Dbg_AWREADY_9 - - - - - AWVALID - - - Dbg_AWVALID_9 - - - - - BREADY - - - Dbg_BREADY_9 - - - - - BRESP - - - Dbg_BRESP_9 - - - - - BVALID - - - Dbg_BVALID_9 - - - - - CAPTURE - - - Dbg_Capture_9 - - - - - CLK - - - Dbg_Clk_9 - - - - - DISABLE - - - Dbg_Disable_9 - - - - - RDATA - - - Dbg_RDATA_9 - - - - - REG_EN - - - Dbg_Reg_En_9 - - - - - RREADY - - - Dbg_RREADY_9 - - - - - RRESP - - - Dbg_RRESP_9 - - - - - RST - - - Dbg_Rst_9 - - - - - RVALID - - - Dbg_RVALID_9 - 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- - - - false - - - - - - MBDEBUG_21 - MBDEBUG_21 - MicroBlaze Debug Interface 21 - - - - - - - ARADDR - - - Dbg_ARADDR_21 - - - - - ARREADY - - - Dbg_ARREADY_21 - - - - - ARVALID - - - Dbg_ARVALID_21 - - - - - AWADDR - - - Dbg_AWADDR_21 - - - - - AWREADY - - - Dbg_AWREADY_21 - - - - - AWVALID - - - Dbg_AWVALID_21 - - - - - BREADY - - - Dbg_BREADY_21 - - - - - BRESP - - - Dbg_BRESP_21 - - - - - BVALID - - - Dbg_BVALID_21 - - - - - CAPTURE - - - Dbg_Capture_21 - - - - - CLK - - - Dbg_Clk_21 - - - - - DISABLE - - - Dbg_Disable_21 - - - - - RDATA - - - Dbg_RDATA_21 - - - - - REG_EN - - - Dbg_Reg_En_21 - - - - - RREADY - - - Dbg_RREADY_21 - - - - - RRESP - - - Dbg_RRESP_21 - - - - - RST - - - Dbg_Rst_21 - - - - - RVALID - - - Dbg_RVALID_21 - - - - - SHIFT - - - Dbg_Shift_21 - - - - - TDI - - - Dbg_TDI_21 - - - - - TDO - - - Dbg_TDO_21 - - - - - TRCLK - - - Dbg_TrClk_21 - - - - - TRDATA - - - Dbg_TrData_21 - - - - - TRIG_ACK_IN - - - Dbg_Trig_Ack_In_21 - - - - - TRIG_ACK_OUT - - - Dbg_Trig_Ack_Out_21 - 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Dbg_BRESP_23 - - - - - BVALID - - - Dbg_BVALID_23 - - - - - CAPTURE - - - Dbg_Capture_23 - - - - - CLK - - - Dbg_Clk_23 - - - - - DISABLE - - - Dbg_Disable_23 - - - - - RDATA - - - Dbg_RDATA_23 - - - - - REG_EN - - - Dbg_Reg_En_23 - - - - - RREADY - - - Dbg_RREADY_23 - - - - - RRESP - - - Dbg_RRESP_23 - - - - - RST - - - Dbg_Rst_23 - - - - - RVALID - - - Dbg_RVALID_23 - - - - - SHIFT - - - Dbg_Shift_23 - - - - - TDI - - - Dbg_TDI_23 - - - - - TDO - - - Dbg_TDO_23 - - - - - TRCLK - - - Dbg_TrClk_23 - - - - - TRDATA - - - Dbg_TrData_23 - - - - - TRIG_ACK_IN - - - Dbg_Trig_Ack_In_23 - - - - - TRIG_ACK_OUT - - - Dbg_Trig_Ack_Out_23 - - - - - TRIG_IN - - - Dbg_Trig_In_23 - - - - - TRIG_OUT - - - Dbg_Trig_Out_23 - - - - - TRREADY - - - Dbg_TrReady_23 - - - - - TRVALID - - - Dbg_TrValid_23 - - - - - UPDATE - - - Dbg_Update_23 - - - - - WDATA - - - Dbg_WDATA_23 - - - - - WREADY - - - Dbg_WREADY_23 - - - - - WVALID - - - Dbg_WVALID_23 - - - - - - - false - - - - - - MBDEBUG_24 - MBDEBUG_24 - MicroBlaze Debug Interface 24 - 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- - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - MBDEBUG_AXI_31 - MBDEBUG_31 - AXI4-Lite Debug - - - - - - - - - ARADDR - - - Dbg_ARADDR_31 - - - - - ARREADY - - - Dbg_ARREADY_31 - - - - - ARVALID - - - Dbg_ARVALID_31 - - - - - AWADDR - - - Dbg_AWADDR_31 - - - - - AWREADY - - - Dbg_AWREADY_31 - - - - - AWVALID - - - Dbg_AWVALID_31 - - - - - BREADY - - - Dbg_BREADY_31 - - - - - BRESP - - - Dbg_BRESP_31 - - - - - BVALID - - - Dbg_BVALID_31 - - - - - RDATA - - - Dbg_RDATA_31 - - - - - RREADY - - - Dbg_RREADY_31 - - - - - RRESP - - - Dbg_RRESP_31 - - - - - RVALID - - - Dbg_RVALID_31 - - - - - WDATA - - - Dbg_WDATA_31 - - - - - WREADY - - - Dbg_WREADY_31 - - - - - WVALID - - - Dbg_WVALID_31 - - - - - - ADDR_WIDTH - 15 - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 1 - - - none - - - - - HAS_LOCK - 1 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 1 - - - none - - - - - HAS_QOS - 1 - - - none - - - - - HAS_REGION - 1 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 1 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 256 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - XMTC - XMTC - XMTC Interface - - - - - - - CAPTURE - - - Ext_JTAG_CAPTURE - - - - - DRCK - - - Ext_JTAG_DRCK - - - - - RESET - - - Ext_JTAG_RESET - - - - - SEL - - - Ext_JTAG_SEL - - - - - SHIFT - - - Ext_JTAG_SHIFT - - - - - TDI - - - Ext_JTAG_TDI - - - - - TDO - - - Ext_JTAG_TDO - - - - - UPDATE - - - Ext_JTAG_UPDATE - - - - - - - false - - - - - - INTERRUPT.INTERRUPT - Interrupt - Interrupt output - - - - - - - INTERRUPT - - - Interrupt - - - - - - SENSITIVITY - EDGE_RISING - - - SUGGESTED_PRIORITY - HIGH - - - PortWidth - 1 - - - none - - - - - - - - true - - - - - - TRIG_IN_0 - Trig_In_0 - External Trigger Input 0 - - - - - - - ACK - - - Trig_Ack_In_0 - - - - - TRIG - - - Trig_In_0 - - - - - - - false - - - - - - TRIG_OUT_0 - Trig_Out_0 - External Trigger Output 0 - - - - - - - ACK - - - Trig_Ack_Out_0 - - - - - TRIG - - - Trig_Out_0 - - - - - - - false - - - - - - TRIG_IN_1 - Trig_In_1 - External Trigger Input 1 - - - - - - - ACK - - - Trig_Ack_In_1 - - - - - TRIG - - - Trig_In_1 - - - - - - - false - - - - - - TRIG_OUT_1 - Trig_Out_1 - External Trigger Output 1 - - - - - - - ACK - - - Trig_Ack_Out_1 - - - - - TRIG - - - Trig_Out_1 - - - - - - - false - - - - - - TRIG_IN_2 - Trig_In_2 - External Trigger Input 2 - - - - - - - ACK - - - Trig_Ack_In_2 - - - - - TRIG - - - Trig_In_2 - - - - - - - false - - - - - - TRIG_OUT_2 - Trig_Out_2 - External Trigger Output 2 - - - - - - - ACK - - - Trig_Ack_Out_2 - - - - - TRIG - - - Trig_Out_2 - - - - - - - false - - - - - - TRIG_IN_3 - Trig_In_3 - External Trigger Input 3 - - - - - - - ACK - - - Trig_Ack_In_3 - - - - - TRIG - - - Trig_In_3 - - - - - - - false - - - - - - TRIG_OUT_3 - Trig_Out_3 - External Trigger Output 3 - - - - - - - ACK - - - Trig_Ack_Out_3 - - - - - TRIG - - - Trig_Out_3 - - - - - - - false - - - - - - BSCAN - BSCAN - External BSCAN Interface - - - - - - - BSCANID_EN - - - bscan_ext_bscanid_en - - - - - CAPTURE - - - bscan_ext_capture - - - - - DRCK - - - bscan_ext_drck - - - - - RESET - - - bscan_ext_reset - - - - - SEL - - - bscan_ext_sel - - - - - SHIFT - - - bscan_ext_shift - - - - - TCK - - - bscan_ext_tck - - - - - TDI - - - bscan_ext_tdi - - - - - TDO - - - bscan_ext_tdo - - - - - TMS - - - bscan_ext_tms - - - - - UPDATE - - - bscan_ext_update - - - - - - - false - - - - - - - - Data - 4294967296 - 32 - - - - false - - - - - - Data_LMB_1 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_2 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_3 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_4 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_5 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_6 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_7 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_8 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_9 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_10 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_11 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_12 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_13 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_14 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_15 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_16 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_17 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_18 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_19 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_20 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_21 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_22 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_23 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_24 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_25 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_26 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_27 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_28 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_29 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_30 - 4294967296 - 32 - - - - false - - - - - - Data_LMB_31 - 4294967296 - 32 - - - - false - - - - - - Debug_0 - 32768 - 14 - - - - false - - - - - - Debug_1 - 32768 - 14 - - - - false - - - - - - Debug_2 - 32768 - 14 - - - - false - - - - - - Debug_3 - 32768 - 14 - - - - false - - - - - - Debug_4 - 32768 - 14 - - - - false - - - - - - Debug_5 - 32768 - 14 - - - - false - - - - - - Debug_6 - 32768 - 14 - - - - false - - - - - - Debug_7 - 32768 - 14 - - - - false - - - - - - Debug_8 - 32768 - 14 - - - - false - - - - - - Debug_9 - 32768 - 14 - - - - false - - - - - - Debug_10 - 32768 - 14 - - - - false - - - - - - Debug_11 - 32768 - 14 - - - - false - - - - - - Debug_12 - 32768 - 14 - - - - false - - - - - - Debug_13 - 32768 - 14 - - - - false - - - - - - Debug_14 - 32768 - 14 - - - - false - - - - - - Debug_15 - 32768 - 14 - - - - false - - - - - - Debug_16 - 32768 - 14 - - - - false - - - - - - Debug_17 - 32768 - 14 - - - - false - - - - - - Debug_18 - 32768 - 14 - - - - false - - - - - - Debug_19 - 32768 - 14 - - - - false - - - - - - Debug_20 - 32768 - 14 - - - - false - - - - - - Debug_21 - 32768 - 14 - - - - false - - - - - - Debug_22 - 32768 - 14 - - - - false - - - - - - Debug_23 - 32768 - 14 - - - - false - - - - - - Debug_24 - 32768 - 14 - - - - false - - - - - - Debug_25 - 32768 - 14 - - - - false - - - - - - Debug_26 - 32768 - 14 - - - - false - - - - - - Debug_27 - 32768 - 14 - - - - false - - - - - - Debug_28 - 32768 - 14 - - - - false - - - - - - Debug_29 - 32768 - 14 - - - - false - - - - - - Debug_30 - 32768 - 14 - - - - false - - - - - - Debug_31 - 32768 - 14 - - - - false - - - - - - - - S_AXI - S_AXI memory map - - Reg - Reg - Register Block - 0 - 4096 - 32 - register - read-write - - UART_Receive - JTAG UART Receive Data - JTAG UART Receive Data - 0x0 - 8 - true - read-only - - 0 - - - UART_RX - UART_RX - UART Receive Data. - 0 - 8 - true - read-only - - 0 - 0 - - modify - false - - - - - true - - - - - - UART_Transmit - JTAG UART Transmit Data - JTAG UART Transmit Data - 0x4 - 8 - true - write-only - - 0 - - - UART_TX - UART_TX - UART Transmit Data. - 0 - 8 - true - write-only - - 0 - 0 - - false - - - - - true - - - - - - UART_Status - JTAG UART Status Register - JTAG UART Status Register - 0x8 - 5 - true - read-only - - 0x0 - - - RX_FIFO_Valid_Data - RX FIFO Valid Data - Indicates if the receive FIFO has valid data: - 0 - Receive FIFO is empty. - 1 - Receive FIFO has valid data. - - 0 - 1 - true - read-only - - 0 - 0 - - false - - - RX_FIFO_Full - RX FIFO Full - Indicates if the receive FIFO is full: - 0 - Receive FIFO is not full. - 1 - Receive FIFO is full. - - 1 - 1 - true - read-only - - 0 - 0 - - false - - - TX_FIFO_Empty - TX FIFO Empty - Indicates if the transmit FIFO is empty: - 0 - Transmit FIFO is not empty. - 1 - Transmit FIFO is empty. - - 2 - 1 - true - read-only - - 0 - 0 - - false - - - TX_FIFO_Full - TX FIFO Full - Indicates if the transmit FIFO is full: - 0 - Transmit FIFO is not full. - 1 - Transmit FIFO is full. - - 3 - 1 - true - read-only - - 0 - 0 - - false - - - Interrupt_Enabled - Interrupt Enabled - Indicates that interrupt is enabled: - 0 - Interrupt is disabled. - 1 - Interrupt is enabled. - - 4 - 1 - true - read-only - - 0 - 0 - - false - - - - - true - - - - - - UART_Control - JTAG UART Control Register - JTAG UART Control Register - 0xC - 5 - true - write-only - - 0x0 - - - Reset_TX_FIFO - Reset TX FIFO - Reset/clear the transmit FIFO: - 0 - Do nothing. - 1 - Clear the transmit FIFO. - - 0 - 1 - true - write-only - - 0 - 0 - - false - - - Reset_RX_FIFO - Reset RX FIFO - Reset/clear the receive FIFO: - 0 - Do nothing. - 1 - Clear the receive FIFO. - - 1 - 1 - true - write-only - - 0 - 0 - - false - - - Clear_EXT_BRK - Clear EXT_BRK - Clear the EXT_BRK signal set by JTAG: - 0 - Do nothing. - 1 - Clear the signal. - - 2 - 1 - true - write-only - - 0 - 0 - - false - - - Interrupt_Enabled - Interrupt Enabled - Indicates interrupt for the MDM JTAG UART: - 0 - Disable interrupt interrupt. - 1 - Enable interrupt signal. - - 4 - 1 - true - write-only - - 0 - 0 - - false - - - - - true - - - - - - Debug_Status - Debug Register Access Status Register - Debug Register Access Status Register - 0x10 - 1 - true - read-only - - 0x0 - - - LOCK - Access Lock - Indicates the access lock status: - 0 - The lock is not acquired. - 1 - The lock has been acquired by the JTAG interface. - - 0 - 1 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - Debug_Control - Debug Register Access Control Register - Debug Register Access Control Register - 0x10 - 20 - true - write-only - - 0x0 - - - Bit_Size - Bit Size - Number of bits in the accessed debug register - 1 - 0 - 9 - true - write-only - - 0 - 0 - - false - - - MDM_Command - MDM Command - MDM command. - 9 - 8 - true - write-only - - 0 - 0 - - false - - - Access_MDM - Access MDM - Access MDM or MicroBlaze Debug register: - 0 - MicroBlaze debug register access. - 1 - MDM debug register access. - - 17 - 1 - true - write-only - - 0 - 0 - - false - - - Access_Lock_Type - Access Lock Type - Access lock type write: - 0 - Release access lock to abort atomic sequence. - 1 - Lock before first access and unlock after last. - 2 - Lock before first access, otherwise keep lock. - 3 - Force lock acquisition, even if aquired by JTAG. - - 18 - 2 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - Debug_Data - Debug Register Access Data Register - Debug Register Access Data Register - 0x14 - 32 - true - read-write - - 0x0 - - - DBG_Data - DBG Data - Read or write debug register data indicated by DBG_CTRL. - 0 - 32 - true - read-write - - 0 - 0 - - modify - false - - - - - false - - - - - - Debug_Lock - Debug Register Access Locking Register - Debug Register Access Locking Register - 0x18 - 16 - true - write-only - - 0x0 - - - DBG_LOCK - DBG Lock - Unlock access to registers DBG_CTLR and DBG_DATA when writing 0xEBAB. - 0 - 16 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - Performance_Counter_Control - Debug Register Performance Counter Control Register - Debug Register Performance Counter Control Register - 0x5440 - 8 - true - write-only - - 0x0 - - - Event - Event - Performance counter event - 0 - 8 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - Performance_Counter_Command - Debug Register Performance Counter Command Register - Debug Register Performance Counter Command Register - 0x5480 - 8 - true - write-only - - 0x0 - - - RES - Reset - Reset accessed counter to the first event counter - 0 - 1 - true - write-only - - 0 - 0 - - false - - - SAM - Sample - Sample status and values in all counters for reading - 1 - 1 - true - write-only - - 0 - 0 - - false - - - STOP - Stop - Stop counting all counters - 2 - 1 - true - write-only - - 0 - 0 - - false - - - STA - Start - Start counting configured events for all counters - 3 - 1 - true - write-only - - 0 - 0 - - false - - - CLR - Clear - Clear all counters to zero - 4 - 1 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - Performance_Counter_Status - Debug Register Performance Counter Status Register - Debug Register Performance Counter Status Register - 0x54C0 - 2 - true - read-only - - 0x0 - - - FULL - Full - Set when a new latency counter event is started before previous event has finished - 0 - 1 - true - read-only - - 0 - 0 - - modify - false - - - OF - Overflow - Set when the counter has counted past its maximum value - 1 - 1 - true - read-only - - 0 - 0 - - modify - false - - - - - false - - - - - - Performance_Counter_Data_Read - Performance Counter Data Read Register - Performance Counter Data Read Register - 0x5580 - 32 - true - read-only - - 0x0 - - - Item - Item - Sampled counter value item - 0 - 32 - true - read-only - - 0 - 0 - - modify - false - - - - - false - - - - - - Performance_Counter_Data_Write - Performance Counter Data Write Register - Performance Counter Data Write Register - 0x55C0 - 32 - true - write-only - - 0x0 - - - Item - Item - Counter value item to write into a counter - 0 - 32 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - Trace_Control - Debug Register Trace Control Register - Debug Register Trace Control Register - 0x5840 - 22 - true - write-only - - 0x0 - - - SR - Save Return - Save new program counter for return instructions - 0 - 1 - true - write-only - - 0 - 0 - - false - - - SL - Save Load - Save load and get instructions for new data value - 1 - 1 - true - write-only - - 0 - 0 - - false - - - SPC - Save PC - Save new program counter for all taken branches - 2 - 1 - true - write-only - - 0 - 0 - - false - - - FH - Full Halt - Debug Halt on full trace buffer or cycle count overflow - 3 - 1 - true - write-only - - 0 - 0 - - false - - - LEVEL - Level - Trace compression level: - 00 - Complete trace - 01 - Program flow - 11 - Program flow and cycle count - - 4 - 2 - true - write-only - - 0 - 0 - - false - - - TP - Tracepoint - Change corresponding breakpoint or watchpoint to a tracepoint - 6 - 16 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - Trace_Command - Debug Register Trace Command Register - Debug Register Trace Command Register - 0x5880 - 4 - true - write-only - - 0x0 - - - SAM - Sample - Sample number of current items in the trace buffer - 0 - 1 - true - write-only - - 0 - 0 - - false - - - STOP - Stop - Stop trace immediately - 1 - 1 - true - write-only - - 0 - 0 - - false - - - STA - Start - Start trace immediately - 2 - 1 - true - write-only - - 0 - 0 - - false - - - CLR - Clear - Clear trace status and empty the trace buffer - 3 - 1 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - Trace_Status - Debug Register Trace Status Register - Debug Register Trace Status Register - 0x58C0 - 18 - true - read-only - - 0x0 - - - IC - Item Count - Sampled trace buffer item count - 0 - 16 - true - read-only - - 0 - 0 - - false - - - OF - Overflow - Cycle count overflow - 16 - 1 - true - read-only - - 0 - 0 - - false - - - STA - Started - Trace started - 17 - 1 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - Trace_Data_Read - Trace Data Read Register - Trace Data Read Register - 0x5980 - 18 - true - read-only - - 0x0 - - - Item - Item - Embedded Trace Buffer item - 0 - 18 - true - read-only - - 0 - 0 - - modify - false - - - - - false - - - - - - Profiling_Control - Debug Register Profiling Control Register - Debug Register Profiling Control Register - 0x5C40 - 8 - true - write-only - - 0x0 - - - BIN - Bin Control - Number of addresses counted by each bin - 0 - 5 - true - write-only - - 0 - 0 - - false - - - CC - Cycle Count - Enable cycle count to count cycles of executed instructions - 5 - 1 - true - write-only - - 0 - 0 - - false - - - DIS - Disable - Disable and stop profiling - 6 - 1 - true - write-only - - 0 - 0 - - false - - - ENA - Enable - Enable and start profiling - 7 - 1 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - Profiling_Low_Address - Profiling Low Address Register - Profiling Low Address Register - 0x5C80 - 30 - true - write-only - - 0x0 - - - Low_word_address - Low word address - Low word address of the profiled area - 0 - 30 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - Profiling_High_Address - Profiling High Address Register - Profiling High Address Register - 0x5CC0 - 30 - true - write-only - - 0x0 - - - High_word_address - High word address - High word address of the profiled area - 0 - 30 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - Profiling_Buffer_Address - Profiling Buffer Address Register - Profiling Buffer Address Register - 0x5D00 - 15 - true - write-only - - 0x0 - - - Buffer_word_address - Buffer word address - Buffer word address of the profiled area - 0 - 15 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - Profiling_Data_Read_0 - Profiling Data Read Register 0 - Profiling Data Read Register, 32 LSB - 0x5D80 - 32 - true - read-only - - 0x0 - - - Read_Data - Read Data - Number of executed instructions or clock cycles in the bin, 32 LSB - 0 - 32 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - Profiling_Data_Read_1 - Profiling Data Read Register 1 - Profiling Data Read Register, 4 MSB - 0x5D84 - 4 - true - read-only - - 0x0 - - - Read_Data - Read Data - Number of executed instructions or clock cycles in the bin, 4 MSB - 0 - 4 - true - read-only - - 0 - 0 - - false - - - - - false - - - - - - Profiling_Data_Write - Profiling Data Write Register - Profiling Data Write Register - 0x5DC0 - 32 - true - write-only - - 0x0 - - - Write_Data - Write Data - Data to write to a bin - 0 - 32 - true - write-only - - 0 - 0 - - false - - - - - false - - - - - - - - - - - Config_Reset - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Scan_Reset - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Scan_Reset_Sel - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Scan_En - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_ACLK - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - S_AXI_ARESETN - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - M_AXI_ACLK - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_ARESETN - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXIS_ACLK - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXIS_ARESETN - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Interrupt - - out - - - std_logic - dummy_view - - - - - - - true - - - - - - Ext_BRK - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Ext_NM_BRK - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Debug_SYS_Rst - - out - - - std_logic - dummy_view - - - - - - Trig_In_0 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Trig_Ack_In_0 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Trig_Out_0 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Trig_Ack_Out_0 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Trig_In_1 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Trig_Ack_In_1 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Trig_Out_1 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Trig_Ack_Out_1 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Trig_In_2 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Trig_Ack_In_2 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Trig_Out_2 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Trig_Ack_Out_2 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Trig_In_3 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - Trig_Ack_In_3 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Trig_Out_3 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - Trig_Ack_Out_3 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - S_AXI_AWADDR - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - true - - - - - - S_AXI_AWVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - S_AXI_AWREADY - - out - - - std_logic - dummy_view - - - - - - - true - - - - - - S_AXI_WDATA - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - true - - - - - - S_AXI_WSTRB - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - true - - - - - - S_AXI_WVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - S_AXI_WREADY - - out - - - std_logic - dummy_view - - - - - - - true - - - - - - S_AXI_BRESP - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - true - - - - - - S_AXI_BVALID - - out - - - std_logic - dummy_view - - - - - - - true - - - - - - S_AXI_BREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - S_AXI_ARADDR - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - true - - - - - - S_AXI_ARVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - S_AXI_ARREADY - - out - - - std_logic - dummy_view - - - - - - - true - - - - - - S_AXI_RDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - true - - - - - - S_AXI_RRESP - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - true - - - - - - S_AXI_RVALID - - out - - - std_logic - dummy_view - - - - - - - true - - - - - - S_AXI_RREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - M_AXI_AWID - - out - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_AWADDR - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_AWLEN - - out - - 7 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_AWSIZE - - out - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_AWBURST - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_AWLOCK - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_AWCACHE - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_AWPROT - - out - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_AWQOS - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_AWVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_AWREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_WDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_WSTRB - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_WLAST - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_WVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_WREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_BRESP - - in - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_BID - - in - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_BVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_BREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_ARID - - out - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_ARADDR - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_ARLEN - - out - - 7 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_ARSIZE - - out - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_ARBURST - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_ARLOCK - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_ARCACHE - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_ARPROT - - out - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_ARQOS - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_ARVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_ARREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_RID - - in - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_RDATA - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_RRESP - - in - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_RLAST - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_RVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_RREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Data_Addr_0 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Addr_Strobe_0 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Ready_0 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Byte_Enable_0 - - out - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Data_Read_0 - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Write_0 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Read_Strobe_0 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Write_Strobe_0 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_CE_0 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_UE_0 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Wait_0 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Addr_1 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Addr_Strobe_1 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Ready_1 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Byte_Enable_1 - - out - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Data_Read_1 - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Write_1 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Read_Strobe_1 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Write_Strobe_1 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_CE_1 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_UE_1 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Wait_1 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Addr_2 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Addr_Strobe_2 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Ready_2 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Byte_Enable_2 - - out - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Data_Read_2 - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Write_2 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Read_Strobe_2 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Write_Strobe_2 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_CE_2 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_UE_2 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Wait_2 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Addr_3 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Addr_Strobe_3 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Ready_3 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Byte_Enable_3 - - out - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Data_Read_3 - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Write_3 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Read_Strobe_3 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Write_Strobe_3 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_CE_3 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_UE_3 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Wait_3 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Addr_4 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Addr_Strobe_4 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Ready_4 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Byte_Enable_4 - - out - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Data_Read_4 - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Write_4 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Read_Strobe_4 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Write_Strobe_4 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_CE_4 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_UE_4 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Wait_4 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Addr_5 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Addr_Strobe_5 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Ready_5 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Byte_Enable_5 - - out - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Data_Read_5 - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Write_5 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Read_Strobe_5 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Write_Strobe_5 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_CE_5 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_UE_5 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Wait_5 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Addr_6 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Addr_Strobe_6 - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - LMB_Ready_6 - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Byte_Enable_6 - - out - - 0 - 3 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Data_Read_6 - - in - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - LMB_Data_Write_6 - - out - - 0 - 31 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - LMB_Read_Strobe_6 - - out - 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- - - - - MON_ILMB - ILMB - Instruction Local Memory Bus Monitor - - - - - - - ABUS - - - Instr_Addr - - - - - ADDRSTROBE - - - I_AS - - - - - CE - - - ICE - - - - - READDBUS - - - Instr - - - - - READSTROBE - - - IFetch - - - - - READY - - - IReady - - - - - UE - - - IUE - - - - - WAIT - - - IWAIT - - - - - - ADDR_WIDTH - 32 - - - DATA_WIDTH - 32 - - - PROTOCOL - STANDARD - - - READ_WRITE_MODE - READ_ONLY - - - - - - false - - - - - - M_AXI_DP - M_AXI_DP - Master AXI4 Data Peripheral Interface - - - - - 0x00000000 - - - - - - ARADDR - - - M_AXI_DP_ARADDR - - - - - ARBURST - - - M_AXI_DP_ARBURST - - - - - ARCACHE - - - M_AXI_DP_ARCACHE - - - - - ARID - - - M_AXI_DP_ARID - - - - - ARLEN - - - M_AXI_DP_ARLEN - - - - - ARLOCK - - - M_AXI_DP_ARLOCK - - - - - ARPROT - - - M_AXI_DP_ARPROT - - - - - ARQOS - - - M_AXI_DP_ARQOS - - - - - ARREADY - - - M_AXI_DP_ARREADY - - - - - ARSIZE - - - M_AXI_DP_ARSIZE - - - - - ARVALID - - - M_AXI_DP_ARVALID - - - - - AWADDR - - - M_AXI_DP_AWADDR - - - - - AWBURST - - - M_AXI_DP_AWBURST - - - - - AWCACHE - - - M_AXI_DP_AWCACHE - - - - - AWID - - - M_AXI_DP_AWID - - - - - AWLEN - - - M_AXI_DP_AWLEN - - - - - AWLOCK - - - M_AXI_DP_AWLOCK - - - - - AWPROT - - - M_AXI_DP_AWPROT - - - - - AWQOS - - - M_AXI_DP_AWQOS - - - - - AWREADY - - - M_AXI_DP_AWREADY - - - - - AWSIZE - - - M_AXI_DP_AWSIZE - - - - - AWVALID - - - M_AXI_DP_AWVALID - - - - - BID - - - M_AXI_DP_BID - - - - - BREADY - - - M_AXI_DP_BREADY - - - - - BRESP - - - M_AXI_DP_BRESP - - - - - BVALID - - - M_AXI_DP_BVALID - - - - - RDATA - - - M_AXI_DP_RDATA - - - - - RID - - - M_AXI_DP_RID - - - - - RLAST - - - M_AXI_DP_RLAST - - - - - RREADY - - - M_AXI_DP_RREADY - - - - - RRESP - - - M_AXI_DP_RRESP - - - - - RVALID - - - M_AXI_DP_RVALID - - - - - WDATA - - - M_AXI_DP_WDATA - - - - - WLAST - - - M_AXI_DP_WLAST - - - - - WREADY - - - M_AXI_DP_WREADY - - - - - WSTRB - - - M_AXI_DP_WSTRB - - - - - WVALID - - - M_AXI_DP_WVALID - - - - - - ID_WIDTH - 0 - - - READ_WRITE_MODE - READ_WRITE - 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- - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - - - - false - - - - - - M_AXI_IC - M_AXI_IC - Master AXI4 Instruction Cache Interface - - - - - - - - - ARADDR - - - M_AXI_IC_ARADDR - - - - - ARBURST - - - M_AXI_IC_ARBURST - - - - - ARCACHE - - - M_AXI_IC_ARCACHE - - - - - ARID - - - M_AXI_IC_ARID - - - - - ARLEN - - - M_AXI_IC_ARLEN - - - - - ARLOCK - - - M_AXI_IC_ARLOCK - - - - - ARPROT - - - M_AXI_IC_ARPROT - - - - - ARQOS - - - M_AXI_IC_ARQOS - - - - - ARREADY - - - M_AXI_IC_ARREADY - - - - - ARSIZE - - - M_AXI_IC_ARSIZE - - - - - ARUSER - - - M_AXI_IC_ARUSER - - - - - ARVALID - - - M_AXI_IC_ARVALID - - - - - AWADDR - - - M_AXI_IC_AWADDR - - - - - AWBURST - - - M_AXI_IC_AWBURST - - - - - AWCACHE - - - M_AXI_IC_AWCACHE - - - - - AWID - - - M_AXI_IC_AWID - - - - - AWLEN - - - M_AXI_IC_AWLEN - - - - - AWLOCK - - - M_AXI_IC_AWLOCK - - - - - AWPROT - - - M_AXI_IC_AWPROT - - - - - AWQOS - - - M_AXI_IC_AWQOS - - - - - AWREADY - - - M_AXI_IC_AWREADY - - - - - AWSIZE - - - M_AXI_IC_AWSIZE - - - - - AWUSER - - - M_AXI_IC_AWUSER - - - - - AWVALID - - - M_AXI_IC_AWVALID - - - - - BID - - - M_AXI_IC_BID - - - - - BREADY - - - M_AXI_IC_BREADY - - - - - BRESP - - - M_AXI_IC_BRESP - - - - - BUSER - - - M_AXI_IC_BUSER - - - - - BVALID - - - M_AXI_IC_BVALID - - - - - RDATA - - - M_AXI_IC_RDATA - - - - - RID - - - M_AXI_IC_RID - - - - - RLAST - - - M_AXI_IC_RLAST - - - - - RREADY - - - M_AXI_IC_RREADY - - - - - RRESP - - - M_AXI_IC_RRESP - - - - - RUSER - - - M_AXI_IC_RUSER - - - - - RVALID - - - M_AXI_IC_RVALID - - - - - WDATA - - - M_AXI_IC_WDATA - - - - - WLAST - - - M_AXI_IC_WLAST - - - - - WREADY - - - M_AXI_IC_WREADY - - - - - WSTRB - - - M_AXI_IC_WSTRB - - - - - WUSER - - - M_AXI_IC_WUSER - - - - - WVALID - - - M_AXI_IC_WVALID - - - - - - ID_WIDTH - 0 - - - READ_WRITE_MODE - READ_ONLY - - - SUPPORTS_NARROW_BURST - 0 - - - HAS_BURST - 1 - - - HAS_LOCK - 0 - - - ADDR_WIDTH - 32 - - - PROTOCOL - AXI4 - - - AWUSER_WIDTH - 0 - - - ARUSER_WIDTH - 0 - - - WUSER_WIDTH - 0 - - - WUSER_BITS_PER_BYTE - 0 - - - RUSER_WIDTH - 0 - - - RUSER_BITS_PER_BYTE - 0 - - - BUSER_WIDTH - 0 - - - DATA_WIDTH - 32 - - - NUM_READ_OUTSTANDING - 2 - - - NUM_READ_THREADS - 1 - - - MAX_BURST_LENGTH - 4 - - - HAS_WSTRB - 0 - - - HAS_BRESP - 0 - - - FREQ_HZ - 100000000 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 1 - - - none - - - - - HAS_QOS - 1 - - - none - - - - - HAS_REGION - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - MON_AXI_IC - M_AXI_IC - Master AXI4 Instruction Cache Interface Monitor - - - - - - - ARADDR - - - M_AXI_IC_ARADDR - - - - - ARBURST - - - M_AXI_IC_ARBURST - - - - - ARCACHE - - - M_AXI_IC_ARCACHE - - - - - ARID - - - M_AXI_IC_ARID - - - - - ARLEN - - - M_AXI_IC_ARLEN - - - - - ARLOCK - - - M_AXI_IC_ARLOCK - - - - - ARPROT - - - M_AXI_IC_ARPROT - - - - - ARQOS - - - M_AXI_IC_ARQOS - - - - - ARREADY - - - M_AXI_IC_ARREADY - - - - - ARSIZE - - - M_AXI_IC_ARSIZE - - - - - ARUSER - - - M_AXI_IC_ARUSER - - - - - ARVALID - - - M_AXI_IC_ARVALID - - - - - AWADDR - - - M_AXI_IC_AWADDR - - - - - AWBURST - - - M_AXI_IC_AWBURST - - - - - AWCACHE - - - M_AXI_IC_AWCACHE - - - - - AWID - - - M_AXI_IC_AWID - - - - - AWLEN - - - M_AXI_IC_AWLEN - - - - - AWLOCK - - - M_AXI_IC_AWLOCK - - - - - AWPROT - - - M_AXI_IC_AWPROT - - - - - AWQOS - - - M_AXI_IC_AWQOS - - - - - AWREADY - - - M_AXI_IC_AWREADY - - - - - AWSIZE - - - M_AXI_IC_AWSIZE - - - - - AWUSER - - - M_AXI_IC_AWUSER - - - - - AWVALID - - - M_AXI_IC_AWVALID - - - - - BID - - - M_AXI_IC_BID - - - - - BREADY - - - M_AXI_IC_BREADY - - - - - BRESP - - - M_AXI_IC_BRESP - - - - - BUSER - - - M_AXI_IC_BUSER - - - - - BVALID - - - M_AXI_IC_BVALID - - - - - RDATA - - - M_AXI_IC_RDATA - - - - - RID - - - M_AXI_IC_RID - - - - - RLAST - - - M_AXI_IC_RLAST - - - - - RREADY - - - M_AXI_IC_RREADY - - - - - RRESP - - - M_AXI_IC_RRESP - - - - - RUSER - - - M_AXI_IC_RUSER - - - - - RVALID - - - M_AXI_IC_RVALID - - - - - WDATA - - - M_AXI_IC_WDATA - - - - - WLAST - - - M_AXI_IC_WLAST - - - - - WREADY - - - M_AXI_IC_WREADY - - - - - WSTRB - - - M_AXI_IC_WSTRB - - - - - WUSER - - - M_AXI_IC_WUSER - - - - - WVALID - - - M_AXI_IC_WVALID - - - - - - ID_WIDTH - 0 - - - READ_WRITE_MODE - READ_ONLY - - - SUPPORTS_NARROW_BURST - 0 - - - HAS_BURST - 1 - - - HAS_LOCK - 0 - - - ADDR_WIDTH - 32 - - - PROTOCOL - AXI4 - - - AWUSER_WIDTH - 0 - - - ARUSER_WIDTH - 0 - - - WUSER_WIDTH - 0 - - - WUSER_BITS_PER_BYTE - 0 - - - RUSER_WIDTH - 0 - - - RUSER_BITS_PER_BYTE - 0 - - - BUSER_WIDTH - 0 - - - DATA_WIDTH - 32 - - - NUM_READ_OUTSTANDING - 2 - - - NUM_READ_THREADS - 1 - - - MAX_BURST_LENGTH - 4 - - - HAS_WSTRB - 0 - - - HAS_BRESP - 0 - - - FREQ_HZ - 100000000 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 1 - - - none - - - - - HAS_QOS - 1 - - - none - - - - - HAS_REGION - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - M_ACE_IC - M_ACE_IC - Master ACE Instruction Cache Interface - - - - - - - - - ACADDR - - - M_AXI_IC_ACADDR - - - - - ACPROT - - - M_AXI_IC_ACPROT - - - - - ACREADY - - - M_AXI_IC_ACREADY - - - - - ACSNOOP - - - M_AXI_IC_ACSNOOP - - - - - ACVALID - - - M_AXI_IC_ACVALID - - - - - ARADDR - - - M_AXI_IC_ARADDR - - - - - ARBAR - - - M_AXI_IC_ARBAR - - - - - ARBURST - - - M_AXI_IC_ARBURST - - - - - ARCACHE - - - M_AXI_IC_ARCACHE - - - - - ARDOMAIN - - - M_AXI_IC_ARDOMAIN - - - - - ARID - - - M_AXI_IC_ARID - - - - - ARLEN - - - M_AXI_IC_ARLEN - - - - - ARLOCK - - - M_AXI_IC_ARLOCK - - - - - ARPROT - - - M_AXI_IC_ARPROT - - - - - ARQOS - - - M_AXI_IC_ARQOS - - - - - ARREADY - - - M_AXI_IC_ARREADY - - - - - ARSIZE - - - M_AXI_IC_ARSIZE - - - - - ARSNOOP - - - M_AXI_IC_ARSNOOP - - - - - ARUSER - - - M_AXI_IC_ARUSER - - - - - ARVALID - - - M_AXI_IC_ARVALID - - - - - AWADDR - - - M_AXI_IC_AWADDR - - - - - AWBAR - - - M_AXI_IC_AWBAR - - - - - AWBURST - - - M_AXI_IC_AWBURST - - - - - AWCACHE - - - M_AXI_IC_AWCACHE - - - - - AWDOMAIN - - - M_AXI_IC_AWDOMAIN - - - - - AWID - - - M_AXI_IC_AWID - - - - - AWLEN - - - M_AXI_IC_AWLEN - - - - - AWLOCK - - - M_AXI_IC_AWLOCK - - - - - AWPROT - - - M_AXI_IC_AWPROT - - - - - AWQOS - - - M_AXI_IC_AWQOS - - - - - AWREADY - - - M_AXI_IC_AWREADY - - - - - AWSIZE - - - M_AXI_IC_AWSIZE - - - - - AWSNOOP - - - M_AXI_IC_AWSNOOP - - - - - AWUSER - - - M_AXI_IC_AWUSER - - - - - AWVALID - - - M_AXI_IC_AWVALID - - - - - BID - - - M_AXI_IC_BID - - - - - BREADY - - - M_AXI_IC_BREADY - - - - - BRESP - - - M_AXI_IC_BRESP - - - - - BUSER - - - M_AXI_IC_BUSER - - - - - BVALID - - - M_AXI_IC_BVALID - - - - - CDDATA - - - M_AXI_IC_CDDATA - - - - - CDLAST - - - M_AXI_IC_CDLAST - - - - - CDREADY - - - M_AXI_IC_CDREADY - - - - - CDVALID - - - M_AXI_IC_CDVALID - - - - - CRREADY - - - M_AXI_IC_CRREADY - - - - - CRRESP - - - M_AXI_IC_CRRESP - - - - - CRVALID - - - M_AXI_IC_CRVALID - - - - - RACK - - - M_AXI_IC_RACK - - - - - RDATA - - - M_AXI_IC_RDATA - - - - - RID - - - M_AXI_IC_RID - - - - - RLAST - - - M_AXI_IC_RLAST - - - - - RREADY - - - M_AXI_IC_RREADY - - - - - RRESP - - - M_AXI_IC_RRESP - - - - - RUSER - - - M_AXI_IC_RUSER - - - - - RVALID - - - M_AXI_IC_RVALID - - - - - WACK - - - M_AXI_IC_WACK - - - - - WDATA - - - M_AXI_IC_WDATA - - - - - WLAST - - - M_AXI_IC_WLAST - - - - - WREADY - - - M_AXI_IC_WREADY - - - - - WSTRB - - - M_AXI_IC_WSTRB - - - - - WUSER - - - M_AXI_IC_WUSER - - - - - WVALID - - - M_AXI_IC_WVALID - - - - - - ID_WIDTH - 1 - - - READ_WRITE_MODE - READ_ONLY - - - SUPPORTS_NARROW_BURST - 0 - - - ADDR_WIDTH - 32 - - - PROTOCOL - ACE - - - DATA_WIDTH - 32 - - - NUM_READ_OUTSTANDING - 2 - - - MAX_BURST_LENGTH - 4 - - - FREQ_HZ - 100000000 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - - - - false - - - - - - MON_ACE_IC - M_ACE_IC - Master ACE Instruction Cache Interface Monitor - - - - - - - ACADDR - - - M_AXI_IC_ACADDR - - - - - ACPROT - - - M_AXI_IC_ACPROT - - - - - ACREADY - - - M_AXI_IC_ACREADY - - - - - ACSNOOP - - - M_AXI_IC_ACSNOOP - - - - - ACVALID - - - M_AXI_IC_ACVALID - - - - - ARADDR - - - M_AXI_IC_ARADDR - - - - - ARBAR - - - M_AXI_IC_ARBAR - - - - - ARBURST - - - M_AXI_IC_ARBURST - - - - - ARCACHE - - - M_AXI_IC_ARCACHE - - - - - ARDOMAIN - - - M_AXI_IC_ARDOMAIN - - - - - ARID - - - M_AXI_IC_ARID - - - - - ARLEN - - - M_AXI_IC_ARLEN - - - - - ARLOCK - - - M_AXI_IC_ARLOCK - - - - - ARPROT - - - M_AXI_IC_ARPROT - - - - - ARQOS - - - M_AXI_IC_ARQOS - - - - - ARREADY - - - M_AXI_IC_ARREADY - - - - - ARSIZE - - - M_AXI_IC_ARSIZE - - - - - ARSNOOP - - - M_AXI_IC_ARSNOOP - - - - - ARUSER - - - M_AXI_IC_ARUSER - - - - - ARVALID - - - M_AXI_IC_ARVALID - - - - - AWADDR - - - M_AXI_IC_AWADDR - - - - - AWBAR - - - M_AXI_IC_AWBAR - - - - - AWBURST - - - M_AXI_IC_AWBURST - - - - - AWCACHE - - - M_AXI_IC_AWCACHE - - - - - AWDOMAIN - - - M_AXI_IC_AWDOMAIN - - - - - AWID - - - M_AXI_IC_AWID - - - - - AWLEN - - - M_AXI_IC_AWLEN - - - - - AWLOCK - - - M_AXI_IC_AWLOCK - - - - - AWPROT - - - M_AXI_IC_AWPROT - - - - - AWQOS - - - M_AXI_IC_AWQOS - - - - - AWREADY - - - M_AXI_IC_AWREADY - - - - - AWSIZE - - - M_AXI_IC_AWSIZE - - - - - AWSNOOP - - - M_AXI_IC_AWSNOOP - - - - - AWUSER - - - M_AXI_IC_AWUSER - - - - - AWVALID - - - M_AXI_IC_AWVALID - - - - - BID - - - M_AXI_IC_BID - - - - - BREADY - - - M_AXI_IC_BREADY - - - - - BRESP - - - M_AXI_IC_BRESP - - - - - BUSER - - - M_AXI_IC_BUSER - - - - - BVALID - - - M_AXI_IC_BVALID - - - - - CDDATA - - - M_AXI_IC_CDDATA - - - - - CDLAST - - - M_AXI_IC_CDLAST - - - - - CDREADY - - - M_AXI_IC_CDREADY - - - - - CDVALID - - - M_AXI_IC_CDVALID - - - - - CRREADY - - - M_AXI_IC_CRREADY - - - - - CRRESP - - - M_AXI_IC_CRRESP - - - - - CRVALID - - - M_AXI_IC_CRVALID - - - - - RACK - - - M_AXI_IC_RACK - - - - - RDATA - - - M_AXI_IC_RDATA - - - - - RID - - - M_AXI_IC_RID - - - - - RLAST - - - M_AXI_IC_RLAST - - - - - RREADY - - - M_AXI_IC_RREADY - - - - - RRESP - - - M_AXI_IC_RRESP - - - - - RUSER - - - M_AXI_IC_RUSER - - - - - RVALID - - - M_AXI_IC_RVALID - - - - - WACK - - - M_AXI_IC_WACK - - - - - WDATA - - - M_AXI_IC_WDATA - - - - - WLAST - - - M_AXI_IC_WLAST - - - - - WREADY - - - M_AXI_IC_WREADY - - - - - WSTRB - - - M_AXI_IC_WSTRB - - - - - WUSER - - - M_AXI_IC_WUSER - - - - - WVALID - - - M_AXI_IC_WVALID - - - - - - ID_WIDTH - 1 - - - READ_WRITE_MODE - READ_ONLY - - - SUPPORTS_NARROW_BURST - 0 - - - ADDR_WIDTH - 32 - - - PROTOCOL - ACE - - - DATA_WIDTH - 32 - - - NUM_READ_OUTSTANDING - 2 - - - MAX_BURST_LENGTH - 4 - - - FREQ_HZ - 100000000 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - - - - false - - - - - - DEBUG - DEBUG - MicroBlaze Debug Interface - - - - - - - ARADDR - - - Dbg_ARADDR - - - - - ARREADY - - - Dbg_ARREADY - - - - - ARVALID - - - Dbg_ARVALID - - - - - AWADDR - - - Dbg_AWADDR - - - - - AWREADY - - - Dbg_AWREADY - - - - - AWVALID - - - Dbg_AWVALID - - - - - BREADY - - - Dbg_BREADY - - - - - BRESP - - - Dbg_BRESP - - - - - BVALID - - - Dbg_BVALID - - - - - CAPTURE - - - Dbg_Capture - - - - - CLK - - - Dbg_Clk - - - - - DISABLE - - - Dbg_Disable - - - - - RDATA - - - Dbg_RDATA - - - - - REG_EN - - - Dbg_Reg_En - - - - - RREADY - - - Dbg_RREADY - - - - - RRESP - - - Dbg_RRESP - - - - - RST - - - Debug_Rst - - - - - RVALID - - - Dbg_RVALID - - - - - SHIFT - - - Dbg_Shift - - - - - TDI - - - Dbg_TDI - - - - - TDO - - - Dbg_TDO - - - - - TRCLK - - - Dbg_Trace_Clk - - - - - TRDATA - - - Dbg_Trace_Data - - - - - TRIG_ACK_IN - - - Dbg_Trig_Ack_In - - - - - TRIG_ACK_OUT - - - Dbg_Trig_Ack_Out - - - - - TRIG_IN - - - Dbg_Trig_In - - - - - TRIG_OUT - - - Dbg_Trig_Out - - - - - TRREADY - - - Dbg_Trace_Ready - - - - - TRVALID - - - Dbg_Trace_Valid - - - - - UPDATE - - - Dbg_Update - - - - - WDATA - - - Dbg_WDATA - - - - - WREADY - - - Dbg_WREADY - - - - - WVALID - - - Dbg_WVALID - - - - - - - true - - - - - - S_AXI_DEBUG - DEBUG - AXI4-Lite Debug - - - - - - - - - ARADDR - - - Dbg_ARADDR - - - - - ARREADY - - - Dbg_ARREADY - - - - - ARVALID - - - Dbg_ARVALID - - - - - AWADDR - - - Dbg_AWADDR - - - - - AWREADY - - - Dbg_AWREADY - - - - - AWVALID - - - Dbg_AWVALID - - - - - BREADY - - - Dbg_BREADY - - - - - BRESP - - - Dbg_BRESP - - - - - BVALID - - - Dbg_BVALID - - - - - RDATA - - - Dbg_RDATA - - - - - RREADY - - - Dbg_RREADY - - - - - RRESP - - - Dbg_RRESP - - - - - RVALID - - - Dbg_RVALID - - - - - WDATA - - - Dbg_WDATA - - - - - WREADY - - - Dbg_WREADY - - - - - WVALID - - - Dbg_WVALID - - - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 32 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 1 - - - none - - - - - HAS_LOCK - 1 - - - none - - - - - HAS_PROT - 1 - - - none - - - - - HAS_CACHE - 1 - - - none - - - - - HAS_QOS - 1 - - - none - - - - - HAS_REGION - 1 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 1 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 256 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - CLK.DEBUG_ACLK - DEBUG_ACLK - Parallel Debug Clock Input - - - - - - - CLK - - - DEBUG_ACLK - - - - - - ASSOCIATED_BUSIF - DEBUG:S_AXI_DEBUG - - - ASSOCIATED_RESET - DEBUG_ARESETN - - - FREQ_HZ - DEBUG_ACLK frequency - DEBUG_ACLK frequency - 30000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - RST.DEBUG_ARESETN - DEBUG_ARESETN - Parallel Debug Reset Input - - - - - - - RST - - - DEBUG_ARESETN - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - DBG_INTR - Dbg_Intr - Debug Interrupt Output - - - - - - - INTERRUPT - - - Dbg_Intr - - - - - - SENSITIVITY - LEVEL_HIGH - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - TRACE - TRACE - MicroBlaze Trace Interface - - - - - - - DATA_ACCESS - - - Trace_Data_Access - - - - - DATA_ADDRESS - - - Trace_Data_Address - - - - - DATA_BYTE_ENABLE - - - Trace_Data_Byte_Enable - - - - - DATA_READ - - - Trace_Data_Read - - - - - DATA_WRITE - - - Trace_Data_Write - - - - - DATA_WRITE_VALUE - - - Trace_Data_Write_Value - - - - - DCACHE_HIT - - - Trace_DCache_Hit - - - - - DCACHE_RDY - - - Trace_DCache_Rdy - - - - - DCACHE_READ - - - Trace_DCache_Read - - - - - DCACHE_REQ - - - Trace_DCache_Req - - - - - DELAY_SLOT - - - Trace_Delay_Slot - - - - - EX_PIPERUN - - - Trace_EX_PipeRun - - - - - EXCEPTION_KIND - - - Trace_Exception_Kind - - - - - EXCEPTION_TAKEN - - - Trace_Exception_Taken - - - - - ICACHE_HIT - - - Trace_ICache_Hit - - - - - ICACHE_RDY - - - Trace_ICache_Rdy - - - - - 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- out - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_IC_ARQOS - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_IC_ARVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_IC_ARREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_ARUSER - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_IC_ARDOMAIN - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_IC_ARSNOOP - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_IC_ARBAR - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_IC_RID - - in - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_RDATA - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_RRESP - - in - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_RLAST - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_RVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_RREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_IC_RUSER - - in - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_RACK - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_IC_ACVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_ACADDR - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_ACSNOOP - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_ACPROT - - in - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_ACREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_IC_CRVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_IC_CRRESP - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_IC_CRREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_IC_CDVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_IC_CDDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_IC_CDLAST - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_IC_CDREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_AWID - - out - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWADDR - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWLEN - - out - - 7 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWSIZE - - out - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWBURST - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWLOCK - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWCACHE - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWPROT - - out - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWQOS - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_AWUSER - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWDOMAIN - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWSNOOP - - out - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_AWBAR - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_WDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_WSTRB - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_WLAST - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_WVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_WREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_WUSER - - out - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_BRESP - - in - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_BID - - in - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_BVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_BREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_BUSER - - in - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_WACK - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARID - - out - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARADDR - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARLEN - - out - - 7 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARSIZE - - out - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARBURST - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARLOCK - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARCACHE - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARPROT - - out - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARQOS - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_ARUSER - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARDOMAIN - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARSNOOP - - out - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ARBAR - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_RID - - in - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_RDATA - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_RRESP - - in - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_RLAST - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_RVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_RREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_RUSER - - in - - 0 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_RACK - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_ACVALID - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_ACADDR - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_ACSNOOP - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_ACPROT - - in - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_ACREADY - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_CRVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_CRRESP - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_CRREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - M_AXI_DC_CDVALID - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_CDDATA - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - M_AXI_DC_CDLAST - - out - - - std_logic - dummy_view - - - - - - - false - - - - - - M_AXI_DC_CDREADY - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - - - C_SCO - 0 - - - C_FREQ - 100000000 - - - C_USE_CONFIG_RESET - 0 - - - C_NUM_SYNC_FF_CLK - Synchronizing FFs to Clk region - 2 - - - C_NUM_SYNC_FF_CLK_IRQ - Synchronizing FFs to Clk region for interrupt input - 1 - - - C_NUM_SYNC_FF_CLK_DEBUG - Synchronizing FFs to Clk region in debug module - 2 - - - C_NUM_SYNC_FF_DBG_CLK - Synchronizing FFs to Dbg_Clk region - 1 - - - C_NUM_SYNC_FF_DBG_TRACE_CLK - Synchronizing FFs to Dbg_Trace_Clk region - 2 - - - C_FAULT_TOLERANT - Enable Fault Tolerance Support - 0 - - - C_ECC_USE_CE_EXCEPTION - Correctable Error Exception - 0 - - - C_LOCKSTEP_SLAVE - Lockstep Slave - 0 - - - C_LOCKSTEP_MASTER - Lockstep Master - 0 - - - C_ENDIANNESS - 1 - - - C_FAMILY - kintexu - - - C_DATA_SIZE - 32 - - - C_LMB_DATA_SIZE - 32 - - - C_INSTR_SIZE - 32 - - - C_IADDR_SIZE - 32 - - - C_PIADDR_SIZE - 32 - - - C_DADDR_SIZE - 32 - - - C_INSTANCE - design_1_microblaze_0_0 - - - C_AVOID_PRIMITIVES - 0 - - - C_AREA_OPTIMIZED - Select implementation optimization - 1 - - - C_OPTIMIZATION - 0 - - - C_INTERCONNECT - Select Bus Interface - 2 - - - C_BASE_VECTORS - Vector Base Address - 0x0000000000000000 - - - C_M_AXI_DP_THREAD_ID_WIDTH - 1 - - - - true - - - - - - C_M_AXI_DP_DATA_WIDTH - 32 - - - - true - - - - - - C_M_AXI_DP_ADDR_WIDTH - 32 - - - - true - - - - - - C_M_AXI_DP_EXCLUSIVE_ACCESS - 0 - - - - true - - - - - - C_M_AXI_D_BUS_EXCEPTION - Enable Data-side AXI Exception - 0 - - - - true - - - - - - C_M_AXI_IP_THREAD_ID_WIDTH - 1 - - - - true - - - - - - C_M_AXI_IP_DATA_WIDTH - 32 - - - - true - - - - - - C_M_AXI_IP_ADDR_WIDTH - 32 - - - - true - - - - - - C_M_AXI_I_BUS_EXCEPTION - Enable Instruction-side AXI Exception - 0 - - - - true - - - - - - C_D_LMB - Enable Local Memory Bus Data Interface - 1 - - - C_D_LMB_PROTOCOL - Local Memory Bus Data Protocol - 0 - - - C_D_AXI - Enable Peripheral AXI Data Interface - 1 - - - C_I_LMB - Enable Local Memory Bus Instruction Interface - 1 - - - C_I_LMB_PROTOCOL - Local Memory Bus Instruction Protocol - 0 - - - C_I_AXI - Enable Peripheral AXI Instruction Interface - 0 - - - G_TEMPLATE_LIST - Select Configuration - 8 - - - C_USE_MSR_INSTR - Enable Additional Machine Status Register Instructions - 1 - - - C_USE_PCMP_INSTR - Enable Pattern Comparator - 1 - - - C_USE_BARREL - Enable Barrel Shifter - 1 - - - C_USE_DIV - Enable Integer Divider - 0 - - - C_USE_HW_MUL - Enable Integer Multiplier - 1 - - - C_USE_FPU - Enable Floating Point Unit - 0 - - - C_USE_REORDER_INSTR - Enable Reversed Load/Store and Swap Instructions - 0 - - - C_UNALIGNED_EXCEPTIONS - Enable Unaligned Data Exception - 0 - - - C_ILL_OPCODE_EXCEPTION - Enable Illegal Instruction Exception - 0 - - - C_DIV_ZERO_EXCEPTION - Enable Integer Divide Exception - 0 - - - - false - - - - - - C_FPU_EXCEPTION - Enable Floating Point Unit Exceptions - 0 - - - - false - - - - - - C_FSL_LINKS - Number of Stream Links - 0 - - - C_USE_EXTENDED_FSL_INSTR - Enable Additional Stream Instructions - 0 - - - C_FSL_EXCEPTION - Enable Stream Exception - 0 - - - - false - - - - - - C_USE_STACK_PROTECTION - Enable stack protection - 0 - - - - true - - - - - - C_IMPRECISE_EXCEPTIONS - Allow Imprecise Exceptions - 0 - - - C_USE_INTERRUPT - 2 - - - C_USE_EXT_BRK - 0 - - - C_USE_EXT_NM_BRK - 0 - - - C_USE_NON_SECURE - 0 - - - C_USE_MMU - Memory Management - 0 - - - - false - - - - - - C_MMU_DTLB_SIZE - Data Shadow Translation Look-Aside Buffer Size - 2 - - - - false - - - - - - C_MMU_ITLB_SIZE - Instruction Shadow Translation Look-Aside Buffer Size - 1 - - - - false - - - - - - C_MMU_TLB_ACCESS - Enable Access to Memory Management Special Registers - 3 - - - - false - - - - - - C_MMU_ZONES - Number of Memory Protection Zones - 2 - - - - false - - - - - - C_MMU_PRIVILEGED_INSTR - Privileged Instructions - 0 - - - - false - - - - - - C_USE_BRANCH_TARGET_CACHE - Enable Branch Target Cache - 0 - - - - false - - - - - - C_BRANCH_TARGET_CACHE_SIZE - Branch Target Cache Size - 0 - - - - false - - - - - - C_PC_WIDTH - 32 - - - C_PVR - Specifies Processor Version Register - 0 - - - C_PVR_USER1 - Specify USER1 Bits in Processor Version Register - 0x00 - - - C_PVR_USER2 - Specify USER2 Bits in Processor Version Register - 0x00000000 - - - C_DYNAMIC_BUS_SIZING - 0 - - - C_RESET_MSR - Specify Reset Value for Select MSR Bits - 0x00000000 - - - C_OPCODE_0x0_ILLEGAL - Generate Illegal Instruction Exception for NULL Instruction - 0 - - - C_DEBUG_ENABLED - MicroBlaze Debug Module Interface - 1 - - - C_DEBUG_INTERFACE - MicroBlaze Debug Connection - 0 - - - C_NUMBER_OF_PC_BRK - Number of PC Breakpoints - 1 - - - C_NUMBER_OF_RD_ADDR_BRK - Number of Read Address Watchpoints - 0 - - - C_NUMBER_OF_WR_ADDR_BRK - Number of Write Address Watchpoints - 0 - - - C_DEBUG_EVENT_COUNTERS - Number of Performance Monitor Event Counters - 5 - - - C_DEBUG_LATENCY_COUNTERS - Number of Performance Monitor Latency Counters - 1 - - - C_DEBUG_COUNTER_WIDTH - Performance Monitor Counter Width - 32 - - - C_DEBUG_TRACE_SIZE - Trace Buffer Size - 8192 - - - C_DEBUG_EXTERNAL_TRACE - External Trace - 0 - - - C_DEBUG_TRACE_ASYNC_RESET - Use Asynchrnous Reset for External Trace - 0 - - - C_DEBUG_PROFILE_SIZE - Profile Buffer Size - 0 - - - C_INTERRUPT_IS_EDGE - Sense Interrupt on Edge vs. Level - 0 - - - C_EDGE_IS_POSITIVE - Sense Interrupt on Rising vs. Falling Edge - 1 - - - C_ASYNC_INTERRUPT - 1 - - - C_ASYNC_WAKEUP - 3 - - - C_M0_AXIS_DATA_WIDTH - 32 - - - C_S0_AXIS_DATA_WIDTH - 32 - - - C_M1_AXIS_DATA_WIDTH - 32 - - - C_S1_AXIS_DATA_WIDTH - 32 - - - C_M2_AXIS_DATA_WIDTH - 32 - - - C_S2_AXIS_DATA_WIDTH - 32 - - - C_M3_AXIS_DATA_WIDTH - 32 - - - C_S3_AXIS_DATA_WIDTH - 32 - - - C_M4_AXIS_DATA_WIDTH - 32 - - - C_S4_AXIS_DATA_WIDTH - 32 - - - C_M5_AXIS_DATA_WIDTH - 32 - - - C_S5_AXIS_DATA_WIDTH - 32 - - - C_M6_AXIS_DATA_WIDTH - 32 - - - C_S6_AXIS_DATA_WIDTH - 32 - - - C_M7_AXIS_DATA_WIDTH - 32 - - - C_S7_AXIS_DATA_WIDTH - 32 - - - C_M8_AXIS_DATA_WIDTH - 32 - - - C_S8_AXIS_DATA_WIDTH - 32 - - - C_M9_AXIS_DATA_WIDTH - 32 - - - C_S9_AXIS_DATA_WIDTH - 32 - - - C_M10_AXIS_DATA_WIDTH - 32 - - - C_S10_AXIS_DATA_WIDTH - 32 - - - C_M11_AXIS_DATA_WIDTH - 32 - - - C_S11_AXIS_DATA_WIDTH - 32 - - - C_M12_AXIS_DATA_WIDTH - 32 - - - C_S12_AXIS_DATA_WIDTH - 32 - - - C_M13_AXIS_DATA_WIDTH - 32 - - - C_S13_AXIS_DATA_WIDTH - 32 - - - C_M14_AXIS_DATA_WIDTH - 32 - - - C_S14_AXIS_DATA_WIDTH - 32 - - - C_M15_AXIS_DATA_WIDTH - 32 - - - C_S15_AXIS_DATA_WIDTH - 32 - - - C_ICACHE_BASEADDR - Base Address - 0x0000000000000000 - - - C_ICACHE_HIGHADDR - High Address - 0x000000003fffffff - - - C_USE_ICACHE - Enable Instruction Cache - 0 - - - C_ALLOW_ICACHE_WR - Enable Writes - 1 - - - C_ADDR_TAG_BITS - 0 - - - C_CACHE_BYTE_SIZE - Size in Bytes - 4096 - - - C_ICACHE_LINE_LEN - Line Length - 4 - - - C_ICACHE_ALWAYS_USED - Use Cache for All Memory Accesses - 1 - - - C_ICACHE_STREAMS - Number of Streams - 0 - - - - false - - - - - - C_ICACHE_VICTIMS - Number of Victims - 0 - - - - false - - - - - - C_ICACHE_FORCE_TAG_LUTRAM - Use Distributed RAM for Tags - 0 - - - - true - - - - - - C_ICACHE_DATA_WIDTH - Data Width - 0 - - - - false - - - - - - C_M_AXI_IC_THREAD_ID_WIDTH - 1 - - - - true - - - - - - C_M_AXI_IC_DATA_WIDTH - 32 - - - C_M_AXI_IC_ADDR_WIDTH - 32 - - - - true - - - - - - C_M_AXI_IC_USER_VALUE - 31 - - - - true - - - - - - C_M_AXI_IC_AWUSER_WIDTH - 5 - - - - true - - - - - - C_M_AXI_IC_ARUSER_WIDTH - 5 - - - - true - - - - - - C_M_AXI_IC_WUSER_WIDTH - 1 - - - - true - - - - - - C_M_AXI_IC_RUSER_WIDTH - 1 - - - - true - - - - - - C_M_AXI_IC_BUSER_WIDTH - 1 - - - - true - - - - - - C_DCACHE_BASEADDR - Base Address - 0x0000000000000000 - - - C_DCACHE_HIGHADDR - High Address - 0x000000003fffffff - - - C_USE_DCACHE - Enable Data Cache - 0 - - - C_ALLOW_DCACHE_WR - Enable Writes - 1 - - - C_DCACHE_ADDR_TAG - 0 - - - C_DCACHE_BYTE_SIZE - Size in Bytes - 4096 - - - C_DCACHE_LINE_LEN - Line Length - 4 - - - C_DCACHE_ALWAYS_USED - Use Cache for All Memory Accesses - 1 - - - C_DCACHE_USE_WRITEBACK - Enable Write-back Storage Policy - 0 - - - - true - - - - - - C_DCACHE_VICTIMS - Number of Victims - 0 - - - - false - - - - - - C_DCACHE_FORCE_TAG_LUTRAM - Use Distributed RAM for Tags - 0 - - - C_DCACHE_DATA_WIDTH - Data Width - 0 - - - - false - - - - - - C_M_AXI_DC_THREAD_ID_WIDTH - 1 - - - - true - - - - - - C_M_AXI_DC_DATA_WIDTH - 32 - - - C_M_AXI_DC_ADDR_WIDTH - 32 - - - - true - - - - - - C_M_AXI_DC_EXCLUSIVE_ACCESS - 0 - - - - true - - - - - - C_M_AXI_DC_USER_VALUE - 31 - - - - true - - - - - - C_M_AXI_DC_AWUSER_WIDTH - 5 - - - - true - - - - - - C_M_AXI_DC_ARUSER_WIDTH - 5 - - - - true - - - - - - C_M_AXI_DC_WUSER_WIDTH - 1 - - - - true - - - - - - C_M_AXI_DC_RUSER_WIDTH - 1 - - - - true - - - - - - C_M_AXI_DC_BUSER_WIDTH - 1 - - - - true - - - - - - - - - choice_list_29910ba8 - GENERIC - - - choice_list_6e3ded9c - 0 - 1 - 2 - 3 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_99ba8646 - 32 - 64 - - - choice_list_b1aff63c - 32 - 48 - 64 - - - choice_list_b94541ab - 0 - 2 - 4 - 8 - - - choice_list_dd2843c6 - 1 - 2 - 4 - 8 - - - choice_list_f86403bf - 4 - 8 - 16 - - - choice_pairs_0000a26c - 0 - 1 - 2 - 3 - - - choice_pairs_0873e75e - 0 - 1 - - - choice_pairs_1075faf2 - 0 - 1 - 2 - - - choice_pairs_126baff7 - 0 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_pairs_13d40c7c - 0 - 32 - 64 - 128 - 256 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_pairs_2018827a - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - - - choice_pairs_2058dc69 - 0 - 1 - - - choice_pairs_22d9f392 - 0 - 1 - 2 - 3 - - - choice_pairs_3eb333f8 - 0 - 1 - 2 - - - choice_pairs_443ae6cc - 0 - 1 - 2 - 3 - - - choice_pairs_4873554b - 0 - 1 - - - choice_pairs_56d5ba32 - 0 - 1 - 2 - - - choice_pairs_5ab38e91 - 0 - 1 - 2 - - - choice_pairs_5b1842a1 - 0 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_pairs_75c71b2b - 0 - 1 - 2 - 3 - - - choice_pairs_7ad6afc0 - 0 - 1 - 2 - 3 - - - choice_pairs_7bfd418d - 0 - 1 - 2 - - - choice_pairs_7dd2834f - 0 - 8 - 9 - 10 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - - - choice_pairs_8b498448 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - - - choice_pairs_b1fa18d9 - 0 - 1 - 2 - - - choice_pairs_c471ed24 - 32 - 36 - 40 - 44 - 48 - 52 - 64 - - - choice_pairs_db57ca32 - 0 - 1 - 2 - - - choice_pairs_e7a1eb81 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - - - choice_pairs_f05e9ea4 - 0 - 1 - - - choice_pairs_ff364cce - 2 - 3 - - - - - microblaze - - - - endian - little - - - elf_class - 32-bit - - - instance_path - - - - bootloop_file - data/mb_bootloop_le.elf - - - processor_type - MICROBLAZE_LE - - - is_visible - true - - - - - The MicroBlaze 32 and 64 bit soft processor core, providing an instruction set optimized for embedded applications with many user-configurable options. MicroBlaze has many advanced architecture features like Instruction and Data-side cache with AXI interfaces, Floating-Point unit (FPU), Memory Management Unit (MMU), and fault tolerance support. -It is highly recommended to create MicroBlaze systems within Vivado IP Integrator, to enable export to the Xilinx Software Development Kit (SDK) for software development. - - - - C_SCO - 0 - - - - true - - - - - - C_FREQ - 100000000 - - - - true - - - - - - C_DATA_SIZE - Select Processor Implementation - 32 - - - - true - - - - - - C_ADDR_SIZE - Select Extended Addressing - 32 - - - - true - - - - - - C_DYNAMIC_BUS_SIZING - 0 - - - - true - - - - - - C_PC_WIDTH - 32 - - - - true - - - - - - C_INSTANCE - microblaze - - - - true - - - - - - C_AVOID_PRIMITIVES - 0 - - - - true - - - - - - C_FAULT_TOLERANT - Enable Fault Tolerance Support - 0 - - - - true - - - - - - C_ECC_USE_CE_EXCEPTION - Correctable Error Exception - 0 - - - - true - - - - - - C_LOCKSTEP_SLAVE - Lockstep Slave - 0 - - - - true - - - - - - C_ENDIANNESS - Endianness - 1 - - - - true - - - - - - C_AREA_OPTIMIZED - Select implementation optimization - 1 - - - - true - - - - - - C_OPTIMIZATION - 0 - - - - true - - - - - - C_INTERCONNECT - Select Bus Interface - 2 - - - - false - - - - - - C_BASE_VECTORS - Vector Base Address - 0x0000000000000000 - - - - true - - - - - - C_USE_CONFIG_RESET - 0 - - - - true - - - - - - C_NUM_SYNC_FF_CLK - Synchronizing FFs to Clk region - 2 - - - - true - - - - - - C_NUM_SYNC_FF_CLK_IRQ - Synchronizing FFs to Clk region for interrupt input - 1 - - - - true - - - - - - C_NUM_SYNC_FF_CLK_DEBUG - Synchronizing FFs to Clk region in debug module - 2 - - - - true - - - - - - C_NUM_SYNC_FF_DBG_CLK - Synchronizing FFs to Dbg_Clk region - 1 - - - - true - - - - - - C_NUM_SYNC_FF_DBG_TRACE_CLK - Synchronizing FFs to Dbg_Trace_Clk region - 2 - - - - true - - - - - - C_M_AXI_DP_THREAD_ID_WIDTH - 1 - - - - true - - - - - - C_M_AXI_DP_DATA_WIDTH - 32 - - - - true - - - - - - C_M_AXI_DP_ADDR_WIDTH - 32 - - - - true - - - - - - C_M_AXI_DP_EXCLUSIVE_ACCESS - 0 - - - - true - - - - - - C_D_AXI - Enable Peripheral AXI Data Interface - 1 - - - - true - - - - - - C_DP_AXI_MON - Use Monitor Interface for Peripheral AXI Data Interface - 0 - - - - true - - - - - - C_DC_AXI_MON - Use Monitor Interface for Cache AXI Data Interface - 0 - - - - true - - - - - - C_D_LMB - Enable Local Memory Bus Data Interface - 1 - - - - true - - - - - - C_D_LMB_PROTOCOL - Local Memory Bus Data Protocol - 0 - - - - true - - - - - - C_D_LMB_MON - Use Monitor Interface for Local Memory Bus Data Interface - 0 - - - - true - - - - - - C_M_AXI_IP_THREAD_ID_WIDTH - 1 - - - - true - - - - - - C_M_AXI_IP_DATA_WIDTH - 32 - - - - true - - - - - - C_M_AXI_IP_ADDR_WIDTH - 32 - - - - true - - - - - - C_I_AXI - Enable Peripheral AXI Instruction Interface - 0 - - - - true - - - - - - C_IP_AXI_MON - Use Monitor Interface for Peripheral AXI Instruction Interface - 0 - - - - true - - - - - - C_IC_AXI_MON - Use Monitor Interface for Cache AXI Instruction Interface - 0 - - - - true - - - - - - C_I_LMB - Enable Local Memory Bus Instruction Interface - 1 - - - - true - - - - - - C_I_LMB_PROTOCOL - Local Memory Bus Instruction Protocol - 0 - - - - true - - - - - - C_I_LMB_MON - Use Monitor Interface for Local Memory Bus Instruction Interface - 0 - - - - true - - - - - - C_TRACE - Enable Trace Bus Interface - 0 - - - - true - - - - - - C_LOCKSTEP_SELECT - Lockstep Interface - 0 - - - - true - - - - - - C_ENABLE_DISCRETE_PORTS - Enable Discrete Ports - 0 - - - - true - - - - - - C_M_AXI_DC_USER_SIGNALS - Enable M_AXI_DC User Signals - 0 - - - - true - - - - - - C_M_AXI_IC_USER_SIGNALS - Enable M_AXI_IC User Signals - 0 - - - - true - - - - - - G_TEMPLATE_LIST - Select Configuration - 8 - - - - true - - - - - - G_USE_EXCEPTIONS - Enable Exceptions - 0 - - - - true - - - - - - C_USE_MSR_INSTR - Enable Additional Machine Status Register Instructions - 1 - - - - true - - - - - - C_USE_PCMP_INSTR - Enable Pattern Comparator - 1 - - - - true - - - - - - C_USE_REORDER_INSTR - Enable Reversed Load/Store and Swap Instructions - 0 - - - - true - - - - - - C_USE_BARREL - Enable Barrel Shifter - 1 - - - - true - - - - - - C_USE_DIV - Enable Integer Divider - 0 - - - - true - - - - - - C_USE_HW_MUL - Enable Integer Multiplier - 1 - - - - true - - - - - - C_USE_FPU - Enable Floating Point Unit - 0 - - - - true - - - - - - C_UNALIGNED_EXCEPTIONS - Enable Unaligned Data Exception - 0 - - - - true - - - - - - C_ILL_OPCODE_EXCEPTION - Enable Illegal Instruction Exception - 0 - - - - true - - - - - - C_M_AXI_I_BUS_EXCEPTION - Enable Instruction-side AXI Exception - 0 - - - - false - - - - - - C_M_AXI_D_BUS_EXCEPTION - Enable Data-side AXI Exception - 0 - - - - true - - - - - - C_DIV_ZERO_EXCEPTION - Enable Integer Divide Exception - 0 - - - - false - - - - - - C_FPU_EXCEPTION - Enable Floating Point Unit Exceptions - 0 - - - - false - - - - - - C_FSL_EXCEPTION - Enable Stream Exception - 0 - - - - false - - - - - - C_USE_STACK_PROTECTION - Enable stack protection - 0 - - - - true - - - - - - C_IMPRECISE_EXCEPTIONS - Allow Imprecise Exceptions - 0 - - - - false - - - - - - C_PVR - Specifies Processor Version Register - 0 - - - - true - - - - - - C_PVR_USER1 - Specify USER1 Bits in Processor Version Register - 0x00 - - - - false - - - - - - C_PVR_USER2 - Specify USER2 Bits in Processor Version Register - 0x00000000 - - - - false - - - - - - C_DEBUG_ENABLED - MicroBlaze Debug Module Interface - 1 - - - - true - - - - - - C_DEBUG_INTERFACE - MicroBlaze Debug Connection - 0 - - - - true - - - - - - C_NUMBER_OF_PC_BRK - Number of PC Breakpoints - 1 - - - - true - - - - - - C_NUMBER_OF_RD_ADDR_BRK - Number of Read Address Watchpoints - 0 - - - - true - - - - - - C_NUMBER_OF_WR_ADDR_BRK - Number of Write Address Watchpoints - 0 - - - - true - - - - - - C_DEBUG_EVENT_COUNTERS - Number of Performance Monitor Event Counters - 5 - - - - false - - - - - - C_DEBUG_LATENCY_COUNTERS - Number of Performance Monitor Latency Counters - 1 - - - - false - - - - - - C_DEBUG_COUNTER_WIDTH - Performance Monitor Counter Width - 32 - - - - false - - - - - - C_DEBUG_TRACE_SIZE - Trace Buffer Size - 8192 - - - - false - - - - - - C_DEBUG_EXTERNAL_TRACE - External Trace - 0 - - - - false - - - - - - C_DEBUG_TRACE_ASYNC_RESET - Use Asynchrnous Reset for External Trace - 0 - - - - true - - - - - - C_DEBUG_PROFILE_SIZE - Profile Buffer Size - 0 - - - - false - - - - - - C_INTERRUPT_IS_EDGE - Sense Interrupt on Edge vs. Level - 0 - - - - true - - - - - - C_EDGE_IS_POSITIVE - Sense Interrupt on Rising vs. Falling Edge - 1 - - - - true - - - - - - C_ASYNC_INTERRUPT - 1 - - - - true - - - - - - C_ASYNC_WAKEUP - 3 - - - - true - - - - - - C_RESET_MSR_IE - IE - 0 - - - - true - - - - - - C_RESET_MSR_BIP - BIP - 0 - - - - true - - - - - - C_RESET_MSR_ICE - ICE - 0 - - - - true - - - - - - C_RESET_MSR_DCE - DCE - 0 - - - - true - - - - - - C_RESET_MSR_EE - EE - 0 - - - - true - - - - - - C_RESET_MSR_EIP - EIP - 0 - - - - true - - - - - - C_OPCODE_0x0_ILLEGAL - Generate Illegal Instruction Exception for NULL Instruction - 0 - - - - false - - - - - - C_FSL_LINKS - Number of Stream Links - 0 - - - - true - - - - - - C_USE_EXTENDED_FSL_INSTR - Enable Additional Stream Instructions - 0 - - - - false - - - - - - C_M0_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S0_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M1_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S1_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M2_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S2_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M3_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S3_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M4_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S4_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M5_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S5_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M6_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S6_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M7_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S7_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M8_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S8_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M9_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S9_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M10_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S10_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M11_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S11_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M12_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S12_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M13_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S13_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M14_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S14_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M15_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_S15_AXIS_PROTOCOL - GENERIC - - - - true - - - - - - C_M0_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S0_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M1_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S1_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M2_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S2_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M3_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S3_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M4_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S4_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M5_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S5_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M6_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S6_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M7_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S7_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M8_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S8_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M9_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S9_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M10_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S10_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M11_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S11_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M12_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S12_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M13_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S13_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M14_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S14_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_M15_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_S15_AXIS_DATA_WIDTH - 32 - - - - true - - - - - - C_ICACHE_BASEADDR - Base Address - 0x0000000000000000 - - - - false - - - - - - C_ICACHE_HIGHADDR - High Address - 0x000000003FFFFFFF - - - - false - - - - - - C_USE_ICACHE - Enable Instruction Cache - 0 - - - - true - - - - - - C_ALLOW_ICACHE_WR - Enable Writes - 1 - - - - false - - - - - - C_ADDR_TAG_BITS - Set number of I-cache address tag bits - 0 - - - - true - - - - - - C_CACHE_BYTE_SIZE - Size in Bytes - 4096 - - - - false - - - - - - C_ICACHE_LINE_LEN - Line Length - 4 - - - - false - - - - - - C_ICACHE_ALWAYS_USED - Use Cache for All Memory Accesses - 1 - - - - false - - - - - - C_ICACHE_VICTIMS - Number of Victims - 0 - - - - false - - - - - - C_ICACHE_STREAMS - Number of Streams - 0 - - - - false - - - - - - C_ICACHE_FORCE_TAG_LUTRAM - Use Distributed RAM for Tags - 0 - - - - false - - - - - - C_ICACHE_DATA_WIDTH - Data Width - 0 - - - - false - - - - - - C_M_AXI_IC_THREAD_ID_WIDTH - 1 - - - - true - - - - - - C_M_AXI_IC_ADDR_WIDTH - 32 - - - - true - - - - - - C_M_AXI_IC_AWUSER_WIDTH - 5 - - - - true - - - - - - C_M_AXI_IC_ARUSER_WIDTH - 5 - - - - true - - - - - - C_M_AXI_IC_WUSER_WIDTH - 1 - - - - true - - - - - - C_M_AXI_IC_RUSER_WIDTH - 1 - - - - true - - - - - - C_M_AXI_IC_BUSER_WIDTH - 1 - - - - true - - - - - - C_M_AXI_IC_USER_VALUE - 31 - - - - true - - - - - - C_DCACHE_BASEADDR - Base Address - 0x0000000000000000 - - - - false - - - - - - C_DCACHE_HIGHADDR - High Address - 0x000000003FFFFFFF - - - - false - - - - - - C_USE_DCACHE - Enable Data Cache - 0 - - - - true - - - - - - C_ALLOW_DCACHE_WR - Enable Writes - 1 - - - - false - - - - - - C_DCACHE_ADDR_TAG - Set number of D-cache address tag bits - 0 - - - - true - - - - - - C_DCACHE_BYTE_SIZE - Size in Bytes - 4096 - - - - false - - - - - - C_DCACHE_LINE_LEN - Line Length - 4 - - - - false - - - - - - C_DCACHE_ALWAYS_USED - Use Cache for All Memory Accesses - 1 - - - - false - - - - - - C_DCACHE_USE_WRITEBACK - Enable Write-back Storage Policy - 0 - - - - false - - - - - - C_DCACHE_VICTIMS - Number of Victims - 0 - - - - false - - - - - - C_DCACHE_FORCE_TAG_LUTRAM - Use Distributed RAM for Tags - 0 - - - - false - - - - - - C_DCACHE_DATA_WIDTH - Data Width - 0 - - - - false - - - - - - C_M_AXI_DC_THREAD_ID_WIDTH - 1 - - - - true - - - - - - C_M_AXI_DC_ADDR_WIDTH - 32 - - - - true - - - - - - C_M_AXI_DC_AWUSER_WIDTH - 5 - - - - true - - - - - - C_M_AXI_DC_ARUSER_WIDTH - 5 - - - - true - - - - - - C_M_AXI_DC_WUSER_WIDTH - 1 - - - - true - - - - - - C_M_AXI_DC_RUSER_WIDTH - 1 - - - - true - - - - - - C_M_AXI_DC_BUSER_WIDTH - 1 - - - - true - - - - - - C_M_AXI_DC_EXCLUSIVE_ACCESS - 0 - - - - true - - - - - - C_M_AXI_DC_USER_VALUE - 31 - - - - true - - - - - - C_USE_MMU - Memory Management - 0 - - - - false - - - - - - C_MMU_DTLB_SIZE - Data Shadow Translation Look-Aside Buffer Size - 2 - - - - false - - - - - - C_MMU_ITLB_SIZE - Instruction Shadow Translation Look-Aside Buffer Size - 1 - - - - false - - - - - - C_MMU_TLB_ACCESS - Enable Access to Memory Management Special Registers - 3 - - - - false - - - - - - C_MMU_ZONES - Number of Memory Protection Zones - 2 - - - - false - - - - - - C_MMU_PRIVILEGED_INSTR - Privileged Instructions - 0 - - - - false - - - - - - C_USE_INTERRUPT - Use Interrupt - 2 - - - - true - - - - - - C_INTERRUPT_MON - Use Monitor Interface for Interrupt - 0 - - - - true - - - - - - C_USE_EXT_BRK - Use Ext_Brk - 0 - - - - true - - - - - - C_USE_EXT_NM_BRK - Use Ext_Nm_Brk - 0 - - - - true - - - - - - C_USE_NON_SECURE - Use Non-Secure AXI access permission - 0 - - - - true - - - - - - C_USE_BRANCH_TARGET_CACHE - Enable Branch Target Cache - 0 - - - - false - - - - - - C_BRANCH_TARGET_CACHE_SIZE - Branch Target Cache Size - 0 - - - - false - - - - - - Component_Name - design_1_microblaze_0_0 - - - - - MicroBlaze - - XPM_MEMORY - - 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci b/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci deleted file mode 100644 index f1a01a2..0000000 --- a/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci +++ /dev/null @@ -1,199 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_microblaze_0_axi_intc_0 - - - 0 - LEVEL_HIGH - 1 - 1 - LEVEL_HIGH - 3 - LEVEL_HIGH:LEVEL_HIGH:EDGE_RISING - design_1_Clk - 100000000 - 0 - 0 - 0.000 - 0 - 9 - 0 - 0 - 0 - design_1_Clk - 32 - 100000000 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 1 - 2 - 1 - 2 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - design_1_Clk - 100000000 - 0 - 0 - 0.000 - 0 - 32 - 0xFFFFFFF9 - 0 - 1 - 0 - 0 - kintexu - 1 - 1 - 0 - 1 - 1 - 1 - design_1_microblaze_0_axi_intc_0 - 0x1 - 1 - 0x0000000000000010 - 0xFFFFFFFF - 0xfffffff9 - 0xFFFFFFFF - 1 - 3 - 0 - 2 - 32 - 0xFFFFFFF9 - 0 - 1 - 0 - 0 - 1 - 1 - 0 - 1 - 1 - 1 - 0x1 - 0 - 1 - 0x0000000000000010 - 0xFFFFFFFF - 0xFFFFFFF9 - 0xFFFFFFFF - 0 - 3 - 0 - 2 - 100.0 - 100.0 - design_1_microblaze_0_axi_intc_0 - Rising - Active_High - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Integrator - 14 - TRUE - . - - ../../ipshared - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xml b/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xml deleted file mode 100644 index 423dcf4..0000000 --- a/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xml +++ /dev/null @@ -1,4292 +0,0 @@ - - - xilinx.com - customized_ip - design_1_microblaze_0_axi_intc_0 - 1.0 - - - s_axi - S_AXI - - - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 32 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 9 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 1 - - - none - - - - - HAS_BRESP - 1 - - - none - - - - - HAS_RRESP - 1 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 2 - - - none - - - - - NUM_WRITE_OUTSTANDING - 2 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - s_resetn - S_RESETn - - - - - - - RST - - - s_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - proc_clock - Proc_clock - - - - - - - CLK - - - processor_clk - - - - - - ASSOCIATED_BUSIF - interrupt - - - ASSOCIATED_RESET - processor_rst - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - design_1_Clk - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - proc_reset - Proc_RESET - - - - - - - RST - - - processor_rst - - - - - - POLARITY - ACTIVE_HIGH - - - TYPE - PROCESSOR - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - interrupt.irq - INTERRUPT - Interrupt to other target than MicroBlaze - - - - - - - INTERRUPT - - - irq - - - - - - SENSITIVITY - LEVEL_HIGH - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - interrupt - INTERRUPT - Interrupt to MicroBlaze or to cascaded INTC - - - - - - - ACK - - - processor_ack - - - - - ADDRESS - - - interrupt_address - - - - - INTERRUPT - - - irq - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - LOW_LATENCY - 1 - - - none - - - - - - - - true - - - - - - interrupt_input - interrupt_input - - - - - - - INTERRUPT - - - intr - - - - - - SENSITIVITY - LEVEL_HIGH:LEVEL_HIGH:EDGE_RISING - - - none - - - - - PortWidth - 3 - - - none - - - - - - - cascade_interrupt - CASCADE_INTERRUPT - Interrupt from cascaded INTC - - - - - - - ACK - - - processor_ack_out - - - - - ADDRESS - - - interrupt_address_in - - - - - INTERRUPT - - - irq_in - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - LOW_LATENCY - 0 - - - none - - - - - - - - false - - - - - - - - S_AXI - S_AXI_MEM - Memory Map for S_AXI - - Reg - Reg - Register Block - 0 - 4096 - 32 - register - read-write - - ISR - Interrupt Status Register - Interrupt Status Register - 0x0 - 3 - true - read-write - - 0x0 - - - INT - Active Interrupt Signal - Interrupt Status Register. -For each bit up to number of periperhal interrupts: - R - Reads active interrupt signal. - W - No effect after MER HIE bit has been set, otherwise writes active interrupt signal. -For remaining bits defined by number of software interrupts: - R - Reads software interrupt value. - W - Writes software interrupt value. - - 0 - 3 - true - read-write - - 0 - 0 - - false - - - - IPR - Interrupt Pending Register - Interrupt Pending Register - 0x4 - 3 - true - read-only - - 0x0 - - - INT - Pending Interrupt Signal - Interrupt Pending Register. -For each bit: - R - Reads logical AND of bits in ISR and IER. - W - No effect. - - 0 - 3 - true - read-only - - 0 - 0 - - false - - - - - true - - - - - - IER - Interrupt Enable Register - Interrupt Enable Register - 0x8 - 3 - true - read-write - - 0x0 - - - INT - Interrupt Enable - Interrupt Enable Register. -For each bit: - R - Reads interrupt enable value. - W - Writes interrupt enable value. - - 0 - 3 - true - read-write - - 0 - 0 - - false - - - - IAR - Interrupt Acknowledge Register - Interrupt Acknowledge Register - 0xC - 3 - true - write-only - - 0x0 - - - INT - Interrupt Acknowledge - Interrupt Acknowledge Register. -For each bit: - W - Acknowledge interrupt. - - 0 - 3 - true - write-only - oneToClear - - 0 - 0 - - false - - - - SIE - Set Interrupt Enables - Set Interrupt Enables - 0x10 - 3 - true - read-write - - 0x0 - - - INT - Set Interrupt Enable - Set Interrupt Enables -For each bit: - R - Reads active interrupt. - W - Writing 1 enables the interrupt, writing 0 has no effect. - - 0 - 3 - true - read-write - oneToSet - - 0 - 0 - - false - - - - - true - - - - - - CIE - Clear Interrupt Enables - Clear Interrupt Enables - 0x14 - 3 - true - read-write - - 0x0 - - - INT - Clear Interrupt Enable - Clear Interrupt Enables -For each bit: - R - Reads active interrupt. - W - Writing 1 disables the interrupt, writing 0 has no effect. - - 0 - 3 - true - read-write - oneToClear - - 0 - 0 - - false - - - - - true - - - - - - IVR - Interrupt Vector Register - Interrupt Vector Register - 0x18 - 5 - true - read-only - - 0x0 - - - IVN - Interrupt Vector Number - Interrupt Vector Number. - R - Reads ordinal of highest priority, enabled, active interrupt. - - 0 - 5 - true - read-only - - 0 - 0 - - false - - - - - true - - - - - - MER - Master Enable Register - Master Enable Register - 0x1C - 2 - true - read-write - - 0x0 - - - ME - Master IRQ Enable - Master IRQ Enable. - 0 - All interrupts disabled. - 1 - All interrupts can be enabled. - - 0 - 1 - true - read-write - - 0 - 0 - - false - - - HIE - Hardware Interrupt Enable - Hardware Interrupt Enable. - 0 - HW interrupts disabled. - 1 - HW interrupts enabled. - - 1 - 1 - true - read-write - - 0 - 0 - - false - - - - IMR - Interrupt Mode Register - Interrupt Mode Register - 0x20 - 3 - true - read-write - - 0x0 - - - INT - Interrupt Mode - Interrupt Mode Register. -For each bit: - R - Reads interrupt mode. - W - Sets interrupt mode, where 0 is normal mode and 1 is fast mode. - - 0 - 3 - true - read-write - - 0 - 0 - - false - - - - - true - - - - - - ILR - Interrupt Level Register - Interrupt Level Register - 0x24 - 5 - true - read-write - - 0x0 - - - ILN - Interrupt Level Number - Interrupt Level Number. - R - Reads ordinal of highest priority interrupt not allowed to generate IRQ. - W - Writes ordinal of highest priority interrupt not allowed to generate IRQ. - - 0 - 5 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[0] - Interrupt Vector Address Register 0 - Interrupt Vector Address Register 0 - 0x100 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 0 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - true - - - - - - IVAR[1] - Interrupt Vector Address Register 1 - Interrupt Vector Address Register 1 - 0x104 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 1 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - true - - - - - - IVAR[2] - Interrupt Vector Address Register 2 - Interrupt Vector Address Register 2 - 0x108 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 2 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - true - - - - - - IVAR[3] - Interrupt Vector Address Register 3 - Interrupt Vector Address Register 3 - 0x10C - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 3 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[4] - Interrupt Vector Address Register 4 - Interrupt Vector Address Register 4 - 0x110 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 4 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[5] - Interrupt Vector Address Register 5 - Interrupt Vector Address Register 5 - 0x114 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 5 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[6] - Interrupt Vector Address Register 6 - Interrupt Vector Address Register 6 - 0x118 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 6 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[7] - Interrupt Vector Address Register 7 - Interrupt Vector Address Register 7 - 0x11C - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 7 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[8] - Interrupt Vector Address Register 8 - Interrupt Vector Address Register 8 - 0x120 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 8 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[9] - Interrupt Vector Address Register 9 - Interrupt Vector Address Register 9 - 0x124 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 9 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[10] - Interrupt Vector Address Register 10 - Interrupt Vector Address Register 10 - 0x128 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 10 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[11] - Interrupt Vector Address Register 11 - Interrupt Vector Address Register 11 - 0x12C - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 11 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[12] - Interrupt Vector Address Register 12 - Interrupt Vector Address Register 12 - 0x130 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 12 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[13] - Interrupt Vector Address Register 13 - Interrupt Vector Address Register 13 - 0x134 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 13 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[14] - Interrupt Vector Address Register 14 - Interrupt Vector Address Register 14 - 0x138 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 14 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[15] - Interrupt Vector Address Register 15 - Interrupt Vector Address Register 15 - 0x13C - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 15 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[16] - Interrupt Vector Address Register 16 - Interrupt Vector Address Register 16 - 0x140 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 16 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[17] - Interrupt Vector Address Register 17 - Interrupt Vector Address Register 17 - 0x144 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 17 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[18] - Interrupt Vector Address Register 18 - Interrupt Vector Address Register 18 - 0x148 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 18 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[19] - Interrupt Vector Address Register 19 - Interrupt Vector Address Register 19 - 0x14C - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 19 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[20] - Interrupt Vector Address Register 20 - Interrupt Vector Address Register 20 - 0x150 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 20 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[21] - Interrupt Vector Address Register 21 - Interrupt Vector Address Register 21 - 0x154 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 21 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[22] - Interrupt Vector Address Register 22 - Interrupt Vector Address Register 22 - 0x158 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 22 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[23] - Interrupt Vector Address Register 23 - Interrupt Vector Address Register 23 - 0x15C - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 23 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[24] - Interrupt Vector Address Register 24 - Interrupt Vector Address Register 24 - 0x160 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 24 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[25] - Interrupt Vector Address Register 25 - Interrupt Vector Address Register 25 - 0x164 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 25 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[26] - Interrupt Vector Address Register 26 - Interrupt Vector Address Register 26 - 0x168 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 26 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[27] - Interrupt Vector Address Register 27 - Interrupt Vector Address Register 27 - 0x16C - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 27 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[28] - Interrupt Vector Address Register 28 - Interrupt Vector Address Register 28 - 0x170 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 28 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[29] - Interrupt Vector Address Register 29 - Interrupt Vector Address Register 29 - 0x174 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 29 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[30] - Interrupt Vector Address Register 30 - Interrupt Vector Address Register 30 - 0x178 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 30 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVAR[31] - Interrupt Vector Address Register 31 - Interrupt Vector Address Register 31 - 0x17C - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 31 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[0] - Interrupt Vector Address Register 0 - Interrupt Vector Address Register 0 - 0x200 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 0 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[1] - Interrupt Vector Address Register 1 - Interrupt Vector Address Register 1 - 0x208 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 1 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[2] - Interrupt Vector Address Register 2 - Interrupt Vector Address Register 2 - 0x210 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 2 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[3] - Interrupt Vector Address Register 3 - Interrupt Vector Address Register 3 - 0x218 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 3 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[4] - Interrupt Vector Address Register 4 - Interrupt Vector Address Register 4 - 0x220 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 4 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[5] - Interrupt Vector Address Register 5 - Interrupt Vector Address Register 5 - 0x228 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 5 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[6] - Interrupt Vector Address Register 6 - Interrupt Vector Address Register 6 - 0x230 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 6 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[7] - Interrupt Vector Address Register 7 - Interrupt Vector Address Register 7 - 0x238 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 7 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[8] - Interrupt Vector Address Register 8 - Interrupt Vector Address Register 8 - 0x240 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 8 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[9] - Interrupt Vector Address Register 9 - Interrupt Vector Address Register 9 - 0x248 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 9 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[10] - Interrupt Vector Address Register 10 - Interrupt Vector Address Register 10 - 0x250 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 10 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[11] - Interrupt Vector Address Register 11 - Interrupt Vector Address Register 11 - 0x258 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 11 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[12] - Interrupt Vector Address Register 12 - Interrupt Vector Address Register 12 - 0x260 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 12 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[13] - Interrupt Vector Address Register 13 - Interrupt Vector Address Register 13 - 0x268 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 13 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[14] - Interrupt Vector Address Register 14 - Interrupt Vector Address Register 14 - 0x270 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 14 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[15] - Interrupt Vector Address Register 15 - Interrupt Vector Address Register 15 - 0x278 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 15 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[16] - Interrupt Vector Address Register 16 - Interrupt Vector Address Register 16 - 0x280 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 16 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[17] - Interrupt Vector Address Register 17 - Interrupt Vector Address Register 17 - 0x288 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 17 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[18] - Interrupt Vector Address Register 18 - Interrupt Vector Address Register 18 - 0x290 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 18 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[19] - Interrupt Vector Address Register 19 - Interrupt Vector Address Register 19 - 0x298 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 19 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[20] - Interrupt Vector Address Register 20 - Interrupt Vector Address Register 20 - 0x2A0 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 20 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[21] - Interrupt Vector Address Register 21 - Interrupt Vector Address Register 21 - 0x2A8 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 21 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[22] - Interrupt Vector Address Register 22 - Interrupt Vector Address Register 22 - 0x2B0 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 22 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[23] - Interrupt Vector Address Register 23 - Interrupt Vector Address Register 23 - 0x2B8 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 23 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[24] - Interrupt Vector Address Register 24 - Interrupt Vector Address Register 24 - 0x2C0 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 24 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[25] - Interrupt Vector Address Register 25 - Interrupt Vector Address Register 25 - 0x2C8 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 25 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[26] - Interrupt Vector Address Register 26 - Interrupt Vector Address Register 26 - 0x2D0 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 26 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[27] - Interrupt Vector Address Register 27 - Interrupt Vector Address Register 27 - 0x2D8 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 27 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[28] - Interrupt Vector Address Register 28 - Interrupt Vector Address Register 28 - 0x2E0 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 28 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[29] - Interrupt Vector Address Register 29 - Interrupt Vector Address Register 29 - 0x2E8 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 29 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[30] - Interrupt Vector Address Register 30 - Interrupt Vector Address Register 30 - 0x2F0 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 30 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - IVEAR[31] - Interrupt Vector Address Register 31 - Interrupt Vector Address Register 31 - 0x2F8 - 32 - true - read-write - - 16 - - - IVA - Interrupt Vector Address - Interrupt vector address of active interrupt 31 with highest priority. - - 0 - 32 - true - read-write - - 0 - 0 - - false - - - - - false - - - - - - - - - - - s_axi_aclk - - in - - - std_logic - dummy_view - - - - - - s_axi_aresetn - - in - - - std_logic - dummy_view - - - - - - s_axi_awaddr - - in - - 8 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_awvalid - - in - - - std_logic - dummy_view - - - - - - s_axi_awready - - out - - - std_logic - dummy_view - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_wvalid - - in - - - std_logic - dummy_view - - - - - - s_axi_wready - - out - - - std_logic - dummy_view - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_bvalid - - out - - - std_logic - dummy_view - - - - - - s_axi_bready - - in - - - std_logic - dummy_view - - - - - - s_axi_araddr - - in - - 8 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_arvalid - - in - - - std_logic - dummy_view - - - - - - s_axi_arready - - out - - - std_logic - dummy_view - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - s_axi_rvalid - - out - - - std_logic - dummy_view - - - - - - s_axi_rready - - in - - - std_logic - dummy_view - - - - - - intr - - in - - 2 - 0 - - - - std_logic_vector - dummy_view - - - - - - processor_clk - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - processor_rst - - in - - - std_logic - dummy_view - - - - 0 - - - - - - true - - - - - - irq - - out - - - std_logic - dummy_view - - - - - - processor_ack - - in - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - true - - - - - - interrupt_address - - out - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - - - - true - - - - - - irq_in - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - interrupt_address_in - - in - - 31 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - processor_ack_out - - out - - 1 - 0 - - - - std_logic_vector - dummy_view - - - - - - - false - - - - - - - - C_FAMILY - kintexu - - - C_INSTANCE - design_1_microblaze_0_axi_intc_0 - - - C_S_AXI_ADDR_WIDTH - S_AXI Address Width - 9 - - - C_S_AXI_DATA_WIDTH - 32 - - - C_NUM_INTR_INPUTS - Number of Peripheral Interrupts - 3 - - - C_NUM_SW_INTR - Number of Software Interrupts - 0 - - - C_KIND_OF_INTR - Interrupts type (Level or Edge) - 0xfffffff9 - - - C_KIND_OF_EDGE - 0xFFFFFFFF - - - C_KIND_OF_LVL - 0xFFFFFFFF - - - C_ASYNC_INTR - 0xFFFFFFF9 - - - C_NUM_SYNC_FF - Number of synchronization flip-flops - 2 - - - C_ADDR_WIDTH - 32 - - - C_IVAR_RESET_VALUE - 0x0000000000000010 - - - C_ENABLE_ASYNC - Enable Async clocks - 0 - - - C_HAS_IPR - Enable Interrupt Pending Register - 1 - - - C_HAS_SIE - 1 - - - C_HAS_CIE - 1 - - - C_HAS_IVR - 1 - - - C_HAS_ILR - 0 - - - C_IRQ_IS_LEVEL - 1 - - - C_IRQ_ACTIVE - 0x1 - - - C_DISABLE_SYNCHRONIZERS - Disable Synchronizers in Design - 1 - - - C_MB_CLK_NOT_CONNECTED - MB Clock Used - 1 - - - C_HAS_FAST - 1 - - - C_EN_CASCADE_MODE - Enable Cascade Interrupt Mode - 0 - - - C_CASCADE_MASTER - Cascade Mode Master - 0 - - - - - - choice_list_5945ab3f - Rising - Falling - - - choice_list_eb22ba99 - Active_High - Active_Low - - - choice_pairs_4873554b - 0 - 1 - - - choice_pairs_706a7d3a - 1 - 0 - - - choice_pairs_d4609148 - 0 - 1 - - - The LogiCORE IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. - - - C_HAS_IPR - Enable Interrupt Pending Register - This check box should be set when the Interrupt Pending Register is required in the core. - 1 - - - C_HAS_SIE - Enable Set Interrupt Enable Register - This check box should be set when the Set Interrupt Enable Register is required in the core. - 1 - - - C_HAS_CIE - Enable Clear Interrupt Enable Register - This check box should be set when the Clear Interrupt Enable Register is required in the core. - 1 - - - C_HAS_IVR - Enable Interrupt Vector Register - This check box should be set when the Interrupt Vector Register is required in the core. - 1 - - - C_HAS_ILR - Enable Interrupt Level Register - This check box should be set when nested interrupt support using the Interrupt Level Register is required in the core. - 0 - - - C_IRQ_ACTIVE - C Irq Active - This option should be set to define the IRQ port active logic level. 0 = Falling/Low, 1 = Rising/High. - 0x1 - - - C_KIND_OF_INTR - Interrupts type - Edge or Level - The setting of each bit in this option indicates the type of incoming interrupt for each bit. 0 = Level, 1 = Edge. Updates of these settings will affect C_KIND_OF_INTR parameter values. - 0xFFFFFFF9 - - - C_NUM_INTR_INPUTS - Number of Peripheral Interrupts - The setting of this option indicates number of interrupts input to the core. - 3 - - - C_NUM_SW_INTR - Number of Software Interrupts - Number of interrupts controlled by software in addition to the hardware interrupt inputs - 0 - - - C_KIND_OF_LVL - Level type - High or Low - The setting of each bit in this option indicates type of logic level for the incoming interrupt of each bit. 0 = Low, 1 = High. - 0xFFFFFFFF - - - C_ASYNC_INTR - Interrupts asynchronous - The setting of each bit in this option indicates whether the incoming interrupt is treated as asynchronous or not. 0 = Synchronous, 1 = Asynchronous. - 0xFFFFFFF9 - - - C_NUM_SYNC_FF - Number of synchronization flip-flops - Number of synchronization flip-flops used to synchronize asynchronous interrupt inputs - 2 - - - C_IRQ_IS_LEVEL - Interrupt type - The setting of this option indicates the IRQ port active type. 0 = Active Edge, 1 = Active Level. - 1 - - - C_KIND_OF_EDGE - Edge type - Rising or Falling - The setting of each bit in this option indicates the type of edge for the incoming interrupt of each bit. 0 = Falling, 1 = Rising. - 0xFFFFFFFF - - - C_HAS_FAST - Enable Fast Interrupt Logic - This check box should be set when the core is configured with Fast Mode Interrupt. The processor uses this setting to automatically enable the low-latency interrupt functionality. Fast Mode Interrupt is not available when selecting Single interrupt output connection. - 1 - - - - true - - - - - - C_ADDR_WIDTH - Interrupt Address Width - Interrupt address width with Fast Mode Interrupt. - 32 - - - - true - - - - - - C_IVAR_RESET_VALUE - Interrupt Vector Address reset value - This option determines the Interrupt Vector Address reset value. It should be set to the processor interrupt vector address, which is C_BASE_VECTORS + 0x10 for MicroBlaze. Only used when the core is configured with Fast Mode Interrupt. - 0x0000000000000010 - - - C_ENABLE_ASYNC - Enable Asynchronous Clock operation - Set this option when the AXI clock is asynchronous to the processor clock. In this case the processor_clk and processor_rst inputs must be connected to the processor clock and reset, respectively. Only used when the core is configured with Fast Mode Interrupt. - 0 - - - Component_Name - design_1_microblaze_0_axi_intc_0 - - - Sense_of_IRQ_Level_Type - Level type - The setting of this parameter indicates the IRQ port type of level. 0 = Level Low, 1 = Level High. - Active_High - - - Sense_of_IRQ_Edge_Type - Edge type - The setting of this parameter indicates the IRQ port type of edge. 0 = Falling Edge, 1 = Rising Edge. - Rising - - - C_EN_CASCADE_MODE - Enable Cascade Interrupt Mode - This check box should be set only when the system has more than 32 interrupt sources. This setting is applicable for all instances of the AXI INTC core cascaded together to handle more than 32 interrupts. - 0 - - - C_CASCADE_MASTER - Cascade Mode Master - This check box should be set only when the system has more than 32 interrupt sources. The setting of this check box is only applicable to the primary instance of the AXI INTC core with the IRQ output directly connected to the processor. For the remaining instances of the cascaded AXI INTC cores, this check box should be left un-checked. - 0 - - - C_MB_CLK_NOT_CONNECTED - MicroBlaze Clock Connected - This parameter should be set only when the core has the processor clock connected to its interrupt interface. - 0 - - - C_DISABLE_SYNCHRONIZERS - Disable Synchronizers - This check box should be set only when the core has the processor clock connected to its interrupt interface and the core and processor clock are synchronous. - 1 - - - C_S_AXI_ACLK_FREQ_MHZ - s_axi_aclk frequency (MHz) - 100.0 - - - - true - - - - - - C_PROCESSOR_CLK_FREQ_MHZ - processor_clk frequency (MHz) - 100.0 - - - - true - - - - - - C_IRQ_CONNECTION - Interrupt Output Connection - Select interrupt output connection bus interface. Normally Bus is used when connecting to MicroBlaze and cascaded AXI Interrupt Controllers. Otherwise Single can be used when Fast Mode Interrupt is not enabled, and the target has a single interrupt input. - 0 - - - - false - - - - - - - - AXI Interrupt Controller - 14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci b/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci deleted file mode 100644 index 658ff64..0000000 --- a/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci +++ /dev/null @@ -1,360 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_microblaze_0_axi_periph_0 - - - design_1_microblaze_0_axi_periph_0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 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0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 3 - 32 - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Integrator_AppCore - 22 - TRUE - . - - ../../ipshared - 2020.1 - GLOBAL - - - - - - - - - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xml b/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xml deleted file mode 100644 index 2bb3f63..0000000 --- a/hub_test/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xml +++ /dev/null @@ -1,1644 +0,0 @@ - - - xilinx.com - customized_ip - design_1_microblaze_0_axi_periph_0 - 1.0 - - - choice_list_40181835 - 32 - 64 - 128 - 256 - 512 - 1024 - - - choice_list_661c4a03 - 2 - 4 - 8 - 16 - 32 - 64 - - - choice_pairs_4873554b - 0 - 1 - - - choice_pairs_76d086ea - 0 - 1 - 2 - - - choice_pairs_ab2668a2 - 0 - 1 - 2 - - - choice_pairs_b6c9535e - 0 - 1 - 3 - 4 - - - The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices - - - NUM_SI - Number of Slave Interfaces - 1 - - - NUM_MI - Number of Master Interfaces - 6 - - - STRATEGY - Interconnect Optimization Strategy - 0 - - - ENABLE_ADVANCED_OPTIONS - Enable Advanced Configuration Options - 0 - - - ENABLE_PROTOCOL_CHECKERS - Enable Protocol Checkers and mark interfaces for debug - 0 - - - XBAR_DATA_WIDTH - Data Width of the AXI Crossbar - 32 - - - PCHK_WAITS - Maximum number of idle cycles for READY monitoring - 0 - - - PCHK_MAX_RD_BURSTS - Maximum outstanding READ Transactions per ID - 2 - - - PCHK_MAX_WR_BURSTS - Maximum outstanding WRITE Transactions per ID - 2 - - - SYNCHRONIZATION_STAGES - Synchronization Stages - 3 - - - M00_HAS_REGSLICE - Enable Register Slice on interface M00_AXI - 0 - - - M01_HAS_REGSLICE - Enable Register Slice on interface M01_AXI - 0 - - - M02_HAS_REGSLICE - Enable Register Slice on interface M02_AXI - 0 - - - M03_HAS_REGSLICE - Enable Register Slice on interface M03_AXI - 0 - - - M04_HAS_REGSLICE - Enable Register Slice on interface M04_AXI - 0 - - - M05_HAS_REGSLICE - Enable Register Slice on interface M05_AXI - 0 - - - M06_HAS_REGSLICE - Enable Register Slice on interface M06_AXI - 0 - - - M07_HAS_REGSLICE - Enable Register Slice on interface M07_AXI - 0 - - - M08_HAS_REGSLICE - Enable Register Slice on interface M08_AXI - 0 - - - M09_HAS_REGSLICE - Enable Register Slice on interface M09_AXI - 0 - - - M10_HAS_REGSLICE - Enable Register Slice on interface M10_AXI - 0 - - - M11_HAS_REGSLICE - Enable Register Slice on interface M11_AXI - 0 - - - M12_HAS_REGSLICE - Enable Register Slice on interface M12_AXI - 0 - - - M13_HAS_REGSLICE - Enable Register Slice on interface M13_AXI - 0 - - - M14_HAS_REGSLICE - Enable Register Slice on interface M14_AXI - 0 - - - M15_HAS_REGSLICE - Enable Register Slice on interface M15_AXI - 0 - - - M16_HAS_REGSLICE - Enable Register Slice on interface M16_AXI - 0 - - - M17_HAS_REGSLICE - Enable Register Slice on interface M17_AXI - 0 - - - M18_HAS_REGSLICE - Enable Register Slice on interface M18_AXI - 0 - - - M19_HAS_REGSLICE - Enable Register Slice on interface M19_AXI - 0 - - - M20_HAS_REGSLICE - Enable Register Slice on interface M20_AXI - 0 - - - M21_HAS_REGSLICE - Enable Register Slice on interface M21_AXI - 0 - - - M22_HAS_REGSLICE - Enable Register Slice on interface M22_AXI - 0 - - - M23_HAS_REGSLICE - Enable Register Slice on interface M23_AXI - 0 - - - M24_HAS_REGSLICE - Enable Register Slice on interface M24_AXI - 0 - - - M25_HAS_REGSLICE - Enable Register Slice on interface M25_AXI - 0 - - - M26_HAS_REGSLICE - Enable Register Slice on interface M26_AXI - 0 - - - M27_HAS_REGSLICE - Enable Register Slice on interface M27_AXI - 0 - - - M28_HAS_REGSLICE - Enable Register Slice on interface M28_AXI - 0 - - - M29_HAS_REGSLICE - Enable Register Slice on interface M29_AXI - 0 - - - M30_HAS_REGSLICE - Enable Register Slice on interface M30_AXI - 0 - - - M31_HAS_REGSLICE - Enable Register Slice on interface M31_AXI - 0 - - - M32_HAS_REGSLICE - Enable Register Slice on interface M32_AXI - 0 - - - M33_HAS_REGSLICE - Enable Register Slice on interface M33_AXI - 0 - - - M34_HAS_REGSLICE - Enable Register Slice on interface M34_AXI - 0 - - - M35_HAS_REGSLICE - Enable Register Slice on interface M35_AXI - 0 - - - M36_HAS_REGSLICE - Enable Register Slice on interface M36_AXI - 0 - - - M37_HAS_REGSLICE - Enable Register Slice on interface M37_AXI - 0 - - - M38_HAS_REGSLICE - Enable Register Slice on interface M38_AXI - 0 - - - M39_HAS_REGSLICE - Enable Register Slice on interface M39_AXI - 0 - - - M40_HAS_REGSLICE - Enable Register Slice on interface M40_AXI - 0 - - - M41_HAS_REGSLICE - Enable Register Slice on interface M41_AXI - 0 - - - M42_HAS_REGSLICE - Enable Register Slice on interface M42_AXI - 0 - - - M43_HAS_REGSLICE - Enable Register Slice on interface M43_AXI - 0 - - - M44_HAS_REGSLICE - Enable Register Slice on interface M44_AXI - 0 - - - M45_HAS_REGSLICE - Enable Register Slice on interface M45_AXI - 0 - - - M46_HAS_REGSLICE - Enable Register Slice on interface M46_AXI - 0 - - - M47_HAS_REGSLICE - Enable Register Slice on interface M47_AXI - 0 - - - M48_HAS_REGSLICE - Enable Register Slice on interface M48_AXI - 0 - - - M49_HAS_REGSLICE - Enable Register Slice on interface M49_AXI - 0 - - - M50_HAS_REGSLICE - Enable Register Slice on interface M50_AXI - 0 - - - M51_HAS_REGSLICE - Enable Register Slice on interface M51_AXI - 0 - - - M52_HAS_REGSLICE - Enable Register Slice on interface M52_AXI - 0 - - - M53_HAS_REGSLICE - Enable Register Slice on interface M53_AXI - 0 - - - M54_HAS_REGSLICE - Enable Register Slice on interface M54_AXI - 0 - - - M55_HAS_REGSLICE - Enable Register Slice on interface M55_AXI - 0 - - - M56_HAS_REGSLICE - Enable Register Slice on interface M56_AXI - 0 - - - M57_HAS_REGSLICE - Enable Register Slice on interface M57_AXI - 0 - - - M58_HAS_REGSLICE - Enable Register Slice on interface M58_AXI - 0 - - - M59_HAS_REGSLICE - Enable Register Slice on interface M59_AXI - 0 - - - M60_HAS_REGSLICE - Enable Register Slice on interface M60_AXI - 0 - - - M61_HAS_REGSLICE - Enable Register Slice on interface M61_AXI - 0 - - - M62_HAS_REGSLICE - Enable Register Slice on interface M62_AXI - 0 - - - M63_HAS_REGSLICE - Enable Register Slice on interface M63_AXI - 0 - - - M00_HAS_DATA_FIFO - Enable Data FIFO on interface M00_AXI - 0 - - - M01_HAS_DATA_FIFO - Enable Data FIFO on interface M01_AXI - 0 - - - M02_HAS_DATA_FIFO - Enable Data FIFO on interface M02_AXI - 0 - - - M03_HAS_DATA_FIFO - Enable Data FIFO on interface M03_AXI - 0 - - - M04_HAS_DATA_FIFO - Enable Data FIFO on interface M04_AXI - 0 - - - M05_HAS_DATA_FIFO - Enable Data FIFO on interface M05_AXI - 0 - - - M06_HAS_DATA_FIFO - Enable Data FIFO on interface M06_AXI - 0 - - - M07_HAS_DATA_FIFO - Enable Data FIFO on interface M07_AXI - 0 - - - M08_HAS_DATA_FIFO - Enable Data FIFO on interface M08_AXI - 0 - - - M09_HAS_DATA_FIFO - Enable Data FIFO on interface M09_AXI - 0 - - - M10_HAS_DATA_FIFO - Enable Data FIFO on interface M10_AXI - 0 - - - M11_HAS_DATA_FIFO - Enable Data FIFO on interface M11_AXI - 0 - - - M12_HAS_DATA_FIFO - Enable Data FIFO on interface M12_AXI - 0 - - - M13_HAS_DATA_FIFO - Enable Data FIFO on interface M13_AXI - 0 - - - M14_HAS_DATA_FIFO - Enable Data FIFO on interface M14_AXI - 0 - - - M15_HAS_DATA_FIFO - Enable Data FIFO on interface M15_AXI - 0 - - - M16_HAS_DATA_FIFO - Enable Data FIFO on interface M16_AXI - 0 - - - M17_HAS_DATA_FIFO - Enable Data FIFO on interface M17_AXI - 0 - - - M18_HAS_DATA_FIFO - Enable Data FIFO on interface M18_AXI - 0 - - - M19_HAS_DATA_FIFO - Enable Data FIFO on interface M19_AXI - 0 - - - M20_HAS_DATA_FIFO - Enable Data FIFO on interface M20_AXI - 0 - - - M21_HAS_DATA_FIFO - Enable Data FIFO on interface M21_AXI - 0 - - - M22_HAS_DATA_FIFO - Enable Data FIFO on interface M22_AXI - 0 - - - M23_HAS_DATA_FIFO - Enable Data FIFO on interface M23_AXI - 0 - - - M24_HAS_DATA_FIFO - Enable Data FIFO on interface M24_AXI - 0 - - - M25_HAS_DATA_FIFO - Enable Data FIFO on interface M25_AXI - 0 - - - M26_HAS_DATA_FIFO - Enable Data FIFO on interface M26_AXI - 0 - - - M27_HAS_DATA_FIFO - Enable Data FIFO on interface M27_AXI - 0 - - - M28_HAS_DATA_FIFO - Enable Data FIFO on interface M28_AXI - 0 - - - M29_HAS_DATA_FIFO - Enable Data FIFO on interface M29_AXI - 0 - - - M30_HAS_DATA_FIFO - Enable Data FIFO on interface M30_AXI - 0 - - - M31_HAS_DATA_FIFO - Enable Data FIFO on interface M31_AXI - 0 - - - M32_HAS_DATA_FIFO - Enable Data FIFO on interface M32_AXI - 0 - - - M33_HAS_DATA_FIFO - Enable Data FIFO on interface M33_AXI - 0 - - - M34_HAS_DATA_FIFO - Enable Data FIFO on interface M34_AXI - 0 - - - M35_HAS_DATA_FIFO - Enable Data FIFO on interface M35_AXI - 0 - - - M36_HAS_DATA_FIFO - Enable Data FIFO on interface M36_AXI - 0 - - - M37_HAS_DATA_FIFO - Enable Data FIFO on interface M37_AXI - 0 - - - M38_HAS_DATA_FIFO - Enable Data FIFO on interface M38_AXI - 0 - - - M39_HAS_DATA_FIFO - Enable Data FIFO on interface M39_AXI - 0 - - - M40_HAS_DATA_FIFO - Enable Data FIFO on interface M40_AXI - 0 - - - M41_HAS_DATA_FIFO - Enable Data FIFO on interface M41_AXI - 0 - - - M42_HAS_DATA_FIFO - Enable Data FIFO on interface M42_AXI - 0 - - - M43_HAS_DATA_FIFO - Enable Data FIFO on interface M43_AXI - 0 - - - M44_HAS_DATA_FIFO - Enable Data FIFO on interface M44_AXI - 0 - - - M45_HAS_DATA_FIFO - Enable Data FIFO on interface M45_AXI - 0 - - - M46_HAS_DATA_FIFO - Enable Data FIFO on interface M46_AXI - 0 - - - M47_HAS_DATA_FIFO - Enable Data FIFO on interface M47_AXI - 0 - - - M48_HAS_DATA_FIFO - Enable Data FIFO on interface M48_AXI - 0 - - - M49_HAS_DATA_FIFO - Enable Data FIFO on interface M49_AXI - 0 - - - M50_HAS_DATA_FIFO - Enable Data FIFO on interface M50_AXI - 0 - - - M51_HAS_DATA_FIFO - Enable Data FIFO on interface M51_AXI - 0 - - - M52_HAS_DATA_FIFO - Enable Data FIFO on interface M52_AXI - 0 - - - M53_HAS_DATA_FIFO - Enable Data FIFO on interface M53_AXI - 0 - - - M54_HAS_DATA_FIFO - Enable Data FIFO on interface M54_AXI - 0 - - - M55_HAS_DATA_FIFO - Enable Data FIFO on interface M55_AXI - 0 - - - M56_HAS_DATA_FIFO - Enable Data FIFO on interface M56_AXI - 0 - - - M57_HAS_DATA_FIFO - Enable Data FIFO on interface M57_AXI - 0 - - - M58_HAS_DATA_FIFO - Enable Data FIFO on interface M58_AXI - 0 - - - M59_HAS_DATA_FIFO - Enable Data FIFO on interface M59_AXI - 0 - - - M60_HAS_DATA_FIFO - Enable Data FIFO on interface M60_AXI - 0 - - - M61_HAS_DATA_FIFO - Enable Data FIFO on interface M61_AXI - 0 - - - M62_HAS_DATA_FIFO - Enable Data FIFO on interface M62_AXI - 0 - - - M63_HAS_DATA_FIFO - Enable Data FIFO on interface M63_AXI - 0 - - - S00_HAS_REGSLICE - Enable Register Slice on interface S00_AXI - 0 - - - S01_HAS_REGSLICE - Enable Register Slice on interface S01_AXI - 0 - - - S02_HAS_REGSLICE - Enable Register Slice on interface S02_AXI - 0 - - - S03_HAS_REGSLICE - Enable Register Slice on interface S03_AXI - 0 - - - S04_HAS_REGSLICE - Enable Register Slice on interface S04_AXI - 0 - - - S05_HAS_REGSLICE - Enable Register Slice on interface S05_AXI - 0 - - - S06_HAS_REGSLICE - Enable Register Slice on interface S06_AXI - 0 - - - S07_HAS_REGSLICE - Enable Register Slice on interface S07_AXI - 0 - - - S08_HAS_REGSLICE - Enable Register Slice on interface S08_AXI - 0 - - - S09_HAS_REGSLICE - Enable Register Slice on interface S09_AXI - 0 - - - S10_HAS_REGSLICE - Enable Register Slice on interface S10_AXI - 0 - - - S11_HAS_REGSLICE - Enable Register Slice on interface S11_AXI - 0 - - - S12_HAS_REGSLICE - Enable Register Slice on interface S12_AXI - 0 - - - S13_HAS_REGSLICE - Enable Register Slice on interface S13_AXI - 0 - - - S14_HAS_REGSLICE - Enable Register Slice on interface S14_AXI - 0 - - - S15_HAS_REGSLICE - Enable Register Slice on interface S15_AXI - 0 - - - S00_HAS_DATA_FIFO - Enable Data FIFO on interface S00_AXI - 0 - - - S01_HAS_DATA_FIFO - Enable Data FIFO on interface S01_AXI - 0 - - - S02_HAS_DATA_FIFO - Enable Data FIFO on interface S02_AXI - 0 - - - S03_HAS_DATA_FIFO - Enable Data FIFO on interface S03_AXI - 0 - - - S04_HAS_DATA_FIFO - Enable Data FIFO on interface S04_AXI - 0 - - - S05_HAS_DATA_FIFO - Enable Data FIFO on interface S05_AXI - 0 - - - S06_HAS_DATA_FIFO - Enable Data FIFO on interface S06_AXI - 0 - - - S07_HAS_DATA_FIFO - Enable Data FIFO on interface S07_AXI - 0 - - - S08_HAS_DATA_FIFO - Enable Data FIFO on interface S08_AXI - 0 - - - S09_HAS_DATA_FIFO - Enable Data FIFO on interface S09_AXI - 0 - - - S10_HAS_DATA_FIFO - Enable Data FIFO on interface S10_AXI - 0 - - - S11_HAS_DATA_FIFO - Enable Data FIFO on interface S11_AXI - 0 - - - S12_HAS_DATA_FIFO - Enable Data FIFO on interface S12_AXI - 0 - - - S13_HAS_DATA_FIFO - Enable Data FIFO on interface S13_AXI - 0 - - - S14_HAS_DATA_FIFO - Enable Data FIFO on interface S14_AXI - 0 - - - S15_HAS_DATA_FIFO - Enable Data FIFO on interface S15_AXI - 0 - - - M00_ISSUANCE - Incicates whether M00_AXI connects to a secure slave - 0 - - - M01_ISSUANCE - Incicates whether M01_AXI connects to a secure slave - 0 - - - M02_ISSUANCE - Incicates whether M02_AXI connects to a secure slave - 0 - - - M03_ISSUANCE - Incicates whether M03_AXI connects to a secure slave - 0 - - - M04_ISSUANCE - Incicates whether M04_AXI connects to a secure slave - 0 - - - M05_ISSUANCE - Incicates whether M05_AXI connects to a secure slave - 0 - - - M06_ISSUANCE - Incicates whether M06_AXI connects to a secure slave - 0 - - - M07_ISSUANCE - Incicates whether M07_AXI connects to a secure slave - 0 - - - M08_ISSUANCE - Incicates whether M08_AXI connects to a secure slave - 0 - - - M09_ISSUANCE - Incicates whether M09_AXI connects to a secure slave - 0 - - - M10_ISSUANCE - Incicates whether M10_AXI connects to a secure slave - 0 - - - M11_ISSUANCE - Incicates whether M11_AXI connects to a secure slave - 0 - - - M12_ISSUANCE - Incicates whether M12_AXI connects to a secure slave - 0 - - - M13_ISSUANCE - Incicates whether M13_AXI connects to a secure slave - 0 - - - M14_ISSUANCE - Incicates whether M14_AXI connects to a secure slave - 0 - - - M15_ISSUANCE - Incicates whether M15_AXI connects to a secure slave - 0 - - - M16_ISSUANCE - Incicates whether M16_AXI connects to a secure slave - 0 - - - M17_ISSUANCE - Incicates whether M17_AXI connects to a secure slave - 0 - - - M18_ISSUANCE - Incicates whether M18_AXI connects to a secure slave - 0 - - - M19_ISSUANCE - Incicates whether M19_AXI connects to a secure slave - 0 - - - M20_ISSUANCE - Incicates whether M20_AXI connects to a secure slave - 0 - - - M21_ISSUANCE - Incicates whether M21_AXI connects to a secure slave - 0 - - - M22_ISSUANCE - Incicates whether M22_AXI connects to a secure slave - 0 - - - M23_ISSUANCE - Incicates whether M23_AXI connects to a secure slave - 0 - - - M24_ISSUANCE - Incicates whether M24_AXI connects to a secure slave - 0 - - - M25_ISSUANCE - Incicates whether M25_AXI connects to a secure slave - 0 - - - M26_ISSUANCE - Incicates whether M26_AXI connects to a secure slave - 0 - - - M27_ISSUANCE - Incicates whether M27_AXI connects to a secure slave - 0 - - - M28_ISSUANCE - Incicates whether M28_AXI connects to a secure slave - 0 - - - M29_ISSUANCE - Incicates whether M29_AXI connects to a secure slave - 0 - - - M30_ISSUANCE - Incicates whether M30_AXI connects to a secure slave - 0 - - - M31_ISSUANCE - Incicates whether M31_AXI connects to a secure slave - 0 - - - M32_ISSUANCE - Incicates whether M32_AXI connects to a secure slave - 0 - - - M33_ISSUANCE - Incicates whether M33_AXI connects to a secure slave - 0 - - - M34_ISSUANCE - Incicates whether M34_AXI connects to a secure slave - 0 - - - M35_ISSUANCE - Incicates whether M35_AXI connects to a secure slave - 0 - - - M36_ISSUANCE - Incicates whether M36_AXI connects to a secure slave - 0 - - - M37_ISSUANCE - Incicates whether M37_AXI connects to a secure slave - 0 - - - M38_ISSUANCE - Incicates whether M38_AXI connects to a secure slave - 0 - - - M39_ISSUANCE - Incicates whether M39_AXI connects to a secure slave - 0 - - - M40_ISSUANCE - Incicates whether M40_AXI connects to a secure slave - 0 - - - M41_ISSUANCE - Incicates whether M41_AXI connects to a secure slave - 0 - - - M42_ISSUANCE - Incicates whether M42_AXI connects to a secure slave - 0 - - - M43_ISSUANCE - Incicates whether M43_AXI connects to a secure slave - 0 - - - M44_ISSUANCE - Incicates whether M44_AXI connects to a secure slave - 0 - - - M45_ISSUANCE - Incicates whether M45_AXI connects to a secure slave - 0 - - - M46_ISSUANCE - Incicates whether M46_AXI connects to a secure slave - 0 - - - M47_ISSUANCE - Incicates whether M47_AXI connects to a secure slave - 0 - - - M48_ISSUANCE - Incicates whether M48_AXI connects to a secure slave - 0 - - - M49_ISSUANCE - Incicates whether M49_AXI connects to a secure slave - 0 - - - M50_ISSUANCE - Incicates whether M50_AXI connects to a secure slave - 0 - - - M51_ISSUANCE - Incicates whether M51_AXI connects to a secure slave - 0 - - - M52_ISSUANCE - Incicates whether M52_AXI connects to a secure slave - 0 - - - M53_ISSUANCE - Incicates whether M53_AXI connects to a secure slave - 0 - - - M54_ISSUANCE - Incicates whether M54_AXI connects to a secure slave - 0 - - - M55_ISSUANCE - Incicates whether M55_AXI connects to a secure slave - 0 - - - M56_ISSUANCE - Incicates whether M56_AXI connects to a secure slave - 0 - - - M57_ISSUANCE - Incicates whether M57_AXI connects to a secure slave - 0 - - - M58_ISSUANCE - Incicates whether M58_AXI connects to a secure slave - 0 - - - M59_ISSUANCE - Incicates whether M59_AXI connects to a secure slave - 0 - - - M60_ISSUANCE - Incicates whether M60_AXI connects to a secure slave - 0 - - - M61_ISSUANCE - Incicates whether M61_AXI connects to a secure slave - 0 - - - M62_ISSUANCE - Incicates whether M62_AXI connects to a secure slave - 0 - - - M63_ISSUANCE - Incicates whether M63_AXI connects to a secure slave - 0 - - - M00_SECURE - Incicates whether M00_AXI connects to a secure slave - 0 - - - M01_SECURE - Incicates whether M01_AXI connects to a secure slave - 0 - - - M02_SECURE - Incicates whether M02_AXI connects to a secure slave - 0 - - - M03_SECURE - Incicates whether M03_AXI connects to a secure slave - 0 - - - M04_SECURE - Incicates whether M04_AXI connects to a secure slave - 0 - - - M05_SECURE - Incicates whether M05_AXI connects to a secure slave - 0 - - - M06_SECURE - Incicates whether M06_AXI connects to a secure slave - 0 - - - M07_SECURE - Incicates whether M07_AXI connects to a secure slave - 0 - - - M08_SECURE - Incicates whether M08_AXI connects to a secure slave - 0 - - - M09_SECURE - Incicates whether M09_AXI connects to a secure slave - 0 - - - M10_SECURE - Incicates whether M10_AXI connects to a secure slave - 0 - - - M11_SECURE - Incicates whether M11_AXI connects to a secure slave - 0 - - - M12_SECURE - Incicates whether M12_AXI connects to a secure slave - 0 - - - M13_SECURE - Incicates whether M13_AXI connects to a secure slave - 0 - - - M14_SECURE - Incicates whether M14_AXI connects to a secure slave - 0 - - - M15_SECURE - Incicates whether M15_AXI connects to a secure slave - 0 - - - M16_SECURE - Incicates whether M16_AXI connects to a secure slave - 0 - - - M17_SECURE - Incicates whether M17_AXI connects to a secure slave - 0 - - - M18_SECURE - Incicates whether M18_AXI connects to a secure slave - 0 - - - M19_SECURE - Incicates whether M19_AXI connects to a secure slave - 0 - - - M20_SECURE - Incicates whether M20_AXI connects to a secure slave - 0 - - - M21_SECURE - Incicates whether M21_AXI connects to a secure slave - 0 - - - M22_SECURE - Incicates whether M22_AXI connects to a secure slave - 0 - - - M23_SECURE - Incicates whether M23_AXI connects to a secure slave - 0 - - - M24_SECURE - Incicates whether M24_AXI connects to a secure slave - 0 - - - M25_SECURE - Incicates whether M25_AXI connects to a secure slave - 0 - - - M26_SECURE - Incicates whether M26_AXI connects to a secure slave - 0 - - - M27_SECURE - Incicates whether M27_AXI connects to a secure slave - 0 - - - M28_SECURE - Incicates whether M28_AXI connects to a secure slave - 0 - - - M29_SECURE - Incicates whether M29_AXI connects to a secure slave - 0 - - - M30_SECURE - Incicates whether M30_AXI connects to a secure slave - 0 - - - M31_SECURE - Incicates whether M31_AXI connects to a secure slave - 0 - - - M32_SECURE - Incicates whether M32_AXI connects to a secure slave - 0 - - - M33_SECURE - Incicates whether M33_AXI connects to a secure slave - 0 - - - M34_SECURE - Incicates whether M34_AXI connects to a secure slave - 0 - - - M35_SECURE - Incicates whether M35_AXI connects to a secure slave - 0 - - - M36_SECURE - Incicates whether M36_AXI connects to a secure slave - 0 - - - M37_SECURE - Incicates whether M37_AXI connects to a secure slave - 0 - - - M38_SECURE - Incicates whether M38_AXI connects to a secure slave - 0 - - - M39_SECURE - Incicates whether M39_AXI connects to a secure slave - 0 - - - M40_SECURE - Incicates whether M40_AXI connects to a secure slave - 0 - - - M41_SECURE - Incicates whether M41_AXI connects to a secure slave - 0 - - - M42_SECURE - Incicates whether M42_AXI connects to a secure slave - 0 - - - M43_SECURE - Incicates whether M43_AXI connects to a secure slave - 0 - - - M44_SECURE - Incicates whether M44_AXI connects to a secure slave - 0 - - - M45_SECURE - Incicates whether M45_AXI connects to a secure slave - 0 - - - M46_SECURE - Incicates whether M46_AXI connects to a secure slave - 0 - - - M47_SECURE - Incicates whether M47_AXI connects to a secure slave - 0 - - - M48_SECURE - Incicates whether M48_AXI connects to a secure slave - 0 - - - M49_SECURE - Incicates whether M49_AXI connects to a secure slave - 0 - - - M50_SECURE - Incicates whether M50_AXI connects to a secure slave - 0 - - - M51_SECURE - Incicates whether M51_AXI connects to a secure slave - 0 - - - M52_SECURE - Incicates whether M52_AXI connects to a secure slave - 0 - - - M53_SECURE - Incicates whether M53_AXI connects to a secure slave - 0 - - - M54_SECURE - Incicates whether M54_AXI connects to a secure slave - 0 - - - M55_SECURE - Incicates whether M55_AXI connects to a secure slave - 0 - - - M56_SECURE - Incicates whether M56_AXI connects to a secure slave - 0 - - - M57_SECURE - Incicates whether M57_AXI connects to a secure slave - 0 - - - M58_SECURE - Incicates whether M58_AXI connects to a secure slave - 0 - - - M59_SECURE - Incicates whether M59_AXI connects to a secure slave - 0 - - - M60_SECURE - Incicates whether M60_AXI connects to a secure slave - 0 - - - M61_SECURE - Incicates whether M61_AXI connects to a secure slave - 0 - - - M62_SECURE - Incicates whether M62_AXI connects to a secure slave - 0 - - - M63_SECURE - Incicates whether M63_AXI connects to a secure slave - 0 - - - S00_ARB_PRIORITY - Controls S00_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S01_ARB_PRIORITY - Controls S01_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S02_ARB_PRIORITY - Controls S02_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S03_ARB_PRIORITY - Controls S03_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S04_ARB_PRIORITY - Controls S04_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S05_ARB_PRIORITY - Controls S05_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S06_ARB_PRIORITY - Controls S06_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S07_ARB_PRIORITY - Controls S07_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S08_ARB_PRIORITY - Controls S08_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S09_ARB_PRIORITY - Controls S09_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S10_ARB_PRIORITY - Controls S10_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S11_ARB_PRIORITY - Controls S11_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S12_ARB_PRIORITY - Controls S12_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S13_ARB_PRIORITY - Controls S13_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S14_ARB_PRIORITY - Controls S14_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S15_ARB_PRIORITY - Controls S15_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - Component_Name - design_1_microblaze_0_axi_periph_0 - - - - - AXI Interconnect - 22 - - - - - - - - 2020.1 - - - - - diff --git a/hub_test/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci b/hub_test/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci deleted file mode 100644 index 5d0e148..0000000 --- a/hub_test/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci +++ /dev/null @@ -1,145 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - design_1_microblaze_0_xlconcat_0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 3 - 3 - design_1_microblaze_0_xlconcat_0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 3 - 3 - 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xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_2_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_3_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_3_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_4_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_4_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_5_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_5_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_6_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_6_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_7_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_7_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_8_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_8_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_9_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_9_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_10_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_10_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_11_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_11_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_12_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_12_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_13_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_13_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_14_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_14_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - target_15_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - target_15_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_target_socket - xtlm.h - - - provides - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_0_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_0_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_1_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_1_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_2_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_2_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_3_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_3_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_4_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_4_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_5_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_5_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_6_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_6_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_7_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_7_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_8_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_8_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_9_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_9_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_10_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_10_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_11_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_11_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_12_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_12_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_13_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_13_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_14_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_14_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_15_wr_socket - AXIMM Write Socket - AXIMM Socket for Write - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - wr_socket - - - width - 32 - - - - - - - 1 - - - - - initiator_15_rd_socket - AXIMM Read Socket - AXIMM Socket for Read - - - xtlm::xtlm_aximm_initiator_socket - xtlm.h - - - requires - - - tlm - - - name - rd_socket - - - width - 32 - - - - - - - 1 - - - - - - - C_FAMILY - kintexu - - - C_NUM_SLAVE_SLOTS - 1 - - - C_NUM_MASTER_SLOTS - 6 - - - C_AXI_ID_WIDTH - 1 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_DATA_WIDTH - 32 - - - C_AXI_PROTOCOL - 2 - - - C_NUM_ADDR_RANGES - 1 - - - C_M_AXI_BASE_ADDR - 0x00000000400100000000000041c000000000000040000000000000004080000000000000414000000000000041200000 - - - C_M_AXI_ADDR_WIDTH - 0x000000100000001000000010000000100000000c00000010 - - - C_S_AXI_BASE_ID - 0x00000000 - - - C_S_AXI_THREAD_ID_WIDTH - 0x00000000 - - - C_AXI_SUPPORTS_USER_SIGNALS - 0 - - - C_AXI_AWUSER_WIDTH - 1 - - - C_AXI_ARUSER_WIDTH - 1 - - - C_AXI_WUSER_WIDTH - 1 - - - C_AXI_RUSER_WIDTH - 1 - - - C_AXI_BUSER_WIDTH - 1 - - - C_M_AXI_WRITE_CONNECTIVITY - 0x000000010000000100000001000000010000000100000001 - - - C_M_AXI_READ_CONNECTIVITY - 0x000000010000000100000001000000010000000100000001 - - - C_R_REGISTER - 1 - - - C_S_AXI_SINGLE_THREAD - 0x00000001 - - - C_S_AXI_WRITE_ACCEPTANCE - 0x00000001 - - - C_S_AXI_READ_ACCEPTANCE - 0x00000001 - - - C_M_AXI_WRITE_ISSUING - 0x000000010000000100000001000000010000000100000001 - - - C_M_AXI_READ_ISSUING - 0x000000010000000100000001000000010000000100000001 - - - C_S_AXI_ARB_PRIORITY - 0x00000000 - - - C_M_AXI_SECURE - 0x000000000000000000000000000000000000000000000000 - - - C_CONNECTIVITY_MODE - 0 - - - - - - choice_list_7235ff92 - AXI4 - AXI3 - AXI4LITE - - - choice_list_99ba8646 - 32 - 64 - - - choice_pairs_12c5c5a3 - 0 - 1 - 7 - 8 - - - choice_pairs_37189c7b - 0 - 1 - - - choice_pairs_4873554b - 0 - 1 - - - choice_pairs_6c89085d - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - - - choice_pairs_d73d287f - SASD - SAMD - - - choice_pairs_d9a0b468 - 0 - 1 - - - choice_pairs_dd3f402c - 0 - 1 - 2 - - - The AXI Crossbar IP provides the infrastructure to connect multiple AXI4/AXI3/AXI4-Lite masters and slaves. - - - ADDR_RANGES - Number of Address Ranges - 1 - - - - true - - - - - - NUM_SI - Number of Slave Interfaces - 1 - - - - true - - - - - - NUM_MI - Number of Master Interfaces - 6 - - - - true - - - - - - ADDR_WIDTH - Address Width - 32 - - - - true - - - - - - STRATEGY - Crossbar Optimization Strategy - 0 - - - - true - - - - - - PROTOCOL - Protocol - AXI4LITE - - - - true - - - - - - DATA_WIDTH - Data Width - 32 - - - - true - - - - - - CONNECTIVITY_MODE - Connectivity Mode - SASD - - - - false - - - - - - ID_WIDTH - ID Width - 0 - - - - false - - - - - - AWUSER_WIDTH - AWUSER Signal Width - 0 - - - - false - - - - - - ARUSER_WIDTH - ARUSER Signal Width - 0 - - - - false - - - - - - WUSER_WIDTH - WUSER Signal Width - 0 - - - - false - - - - - - RUSER_WIDTH - RUSER Signal Width - 0 - - - - false - - - - - - BUSER_WIDTH - BUSER Signal Width - 0 - - - - false - - - - - - R_REGISTER - Read Channel Register Slice - 1 - - - - true - - - - - - M00_S00_READ_CONNECTIVITY - My M00_S00_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S01_READ_CONNECTIVITY - My M00_S01_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S02_READ_CONNECTIVITY - My M00_S02_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S03_READ_CONNECTIVITY - My M00_S03_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S04_READ_CONNECTIVITY - My M00_S04_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S05_READ_CONNECTIVITY - My M00_S05_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S06_READ_CONNECTIVITY - My M00_S06_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S07_READ_CONNECTIVITY - My M00_S07_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S08_READ_CONNECTIVITY - My M00_S08_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S09_READ_CONNECTIVITY - My M00_S09_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S10_READ_CONNECTIVITY - My M00_S10_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S11_READ_CONNECTIVITY - My M00_S11_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S12_READ_CONNECTIVITY - My M00_S12_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S13_READ_CONNECTIVITY - My M00_S13_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S14_READ_CONNECTIVITY - My M00_S14_READ_CONNECTIVITY - 1 - - - - true - - - - - - M00_S15_READ_CONNECTIVITY - My M00_S15_READ_CONNECTIVITY - 1 - - - - true - - - - - - M01_S00_READ_CONNECTIVITY - My M01_S00_READ_CONNECTIVITY - 1 - - - - true - - - - - - M01_S01_READ_CONNECTIVITY - My M01_S01_READ_CONNECTIVITY - 1 - - - - true - - - - - - M01_S02_READ_CONNECTIVITY - My M01_S02_READ_CONNECTIVITY - 1 - - - - true - - - - - - M01_S03_READ_CONNECTIVITY - My M01_S03_READ_CONNECTIVITY - 1 - - - - true - - - - - - M01_S04_READ_CONNECTIVITY - My M01_S04_READ_CONNECTIVITY - 1 - - - - true - - - - - - M01_S05_READ_CONNECTIVITY - My M01_S05_READ_CONNECTIVITY - 1 - - - - true - - - - - - M01_S06_READ_CONNECTIVITY - My M01_S06_READ_CONNECTIVITY - 1 - - - - true - - - - - - M01_S07_READ_CONNECTIVITY - My M01_S07_READ_CONNECTIVITY - 1 - - - - true - - - - - - M01_S08_READ_CONNECTIVITY - My M01_S08_READ_CONNECTIVITY - 1 - - - - true - - - - - - M01_S09_READ_CONNECTIVITY - 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