From: hadeshyp Date: Wed, 28 Jul 2010 13:35:24 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~212 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0e308959a10de8559ba3931d0d0bd6a88bcbcf87;p=trbnet.git *** empty log message *** --- diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index 6f26af8..ef7f3ab 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -120,7 +120,7 @@ begin if( clear = '1' ) then cv_ctr <= (others => '0'); elsif( rising_edge(sysclk) ) then - if ( rst_cctr = '1' ) then + if ( rst_cctr = '1' or timing_ctr(9 downto 0) = 0) then cv_ctr <= (others => '0'); elsif( ce_cctr = '1' ) then cv_ctr <= cv_ctr + 1; diff --git a/special/handler_ipu.vhd b/special/handler_ipu.vhd index 8af3cfb..959831b 100644 --- a/special/handler_ipu.vhd +++ b/special/handler_ipu.vhd @@ -212,7 +212,7 @@ begin if rising_edge(CLOCK) then if hdr_fifo_valid_read = '1' then dat_fifo_read_length(i) <= unsigned(DAT_DATA_LENGTH_IN(i*16+15 downto i*16)); - elsif dat_fifo_read(i) = '1' then + elsif next_dat_fifo_valid_read = '1' and dat_fifo_select(i) = '1' then --dat_fifo_read dat_fifo_read_length(i) <= dat_fifo_read_length(i) - to_unsigned(1,1); end if; end if; @@ -225,8 +225,8 @@ begin if rising_edge(CLOCK) then if hdr_fifo_valid_read = '1' then dat_fifo_finished(i) <= '0'; - elsif (dat_fifo_read_length(i) = to_unsigned(1,10) and dat_fifo_read(i) = '1') - or dat_fifo_read_length(i) = 0 then + elsif -- (dat_fifo_read_length(i) = to_unsigned(1,10) and dat_fifo_read(i) = '1') or + dat_fifo_read_length(i) = 0 then dat_fifo_finished(i) <= '1'; end if; end if; diff --git a/testbenches/testbench_endpoint_hades_full_handler.vhd b/testbenches/testbench_endpoint_hades_full_handler.vhd index 61194d3..9a64d89 100644 --- a/testbenches/testbench_endpoint_hades_full_handler.vhd +++ b/testbenches/testbench_endpoint_hades_full_handler.vhd @@ -13,7 +13,7 @@ end entity; architecture tb_arch of tb is - constant NUMBER_OF_ADC : integer := 2; + constant NUMBER_OF_ADC : integer := 6; signal clk : std_logic := '1'; signal reset : std_logic := '1'; @@ -313,23 +313,18 @@ proc_write_data_1 : process while 1 = 1 loop wait until rising_edge(trg_valid_timing); wait for 100 ns; --- wait until falling_edge(clk); --- fee_data(31 downto 0) <= x"11110001"; --- fee_data_write(0) <= '1'; --- wait until falling_edge(clk); --- fee_data_write(0) <= '0'; --- wait until falling_edge(clk); --- fee_data(31 downto 0) <= x"22220002"; --- fee_data_write(0) <= '1'; --- if event /= 0 then --- wait until falling_edge(clk); --- fee_data(31 downto 0) <= x"33330003"; --- fee_data_write(0) <= '1'; --- end if; --- wait until falling_edge(clk); --- fee_data_write(0) <= '0'; --- wait until falling_edge(clk); --- fee_trg_release(0) <= '1'; + wait until falling_edge(clk); + fee_data(31 downto 0) <= x"11110001"; + fee_data_write(0) <= '1'; + wait until falling_edge(clk); + fee_data(31 downto 0) <= x"11110002"; + fee_data_write(0) <= '1'; + wait until falling_edge(clk); + fee_data_write(0) <= '0'; + wait until falling_edge(clk); + fee_data_write(0) <= '0'; + wait until falling_edge(clk); + fee_trg_release(0) <= '1'; wait until falling_edge(clk); fee_trg_release(0) <= '0'; fee_data_finished(0) <= '1'; @@ -344,25 +339,10 @@ proc_write_data_2 : process while 1 = 1 loop wait until rising_edge(trg_valid_timing); wait for 700 ns; --- wait until falling_edge(clk); --- fee_data(63 downto 32) <= x"11110001"; --- fee_data_write(1) <= '1'; --- wait until falling_edge(clk); --- fee_data_write(1) <= '0'; --- wait until falling_edge(clk); --- fee_data(63 downto 32) <= x"22220002"; --- fee_data_write(1) <= '1'; --- wait until falling_edge(clk); --- fee_data(63 downto 32) <= x"33330003"; --- fee_data_write(1) <= '1'; --- wait until falling_edge(clk); --- fee_data(63 downto 32) <= x"44440004"; --- fee_data_write(1) <= '1'; --- wait until falling_edge(clk); --- fee_data_write(1) <= '0'; --- wait for 200 ns; --- wait until falling_edge(clk); --- fee_trg_release(1) <= '1'; + wait until falling_edge(clk); + wait for 200 ns; + wait until falling_edge(clk); + fee_trg_release(1) <= '1'; wait until falling_edge(clk); fee_trg_release(1) <= '0'; fee_data_finished(1) <= '1'; @@ -371,7 +351,85 @@ proc_write_data_2 : process end loop; end process; +proc_write_data_3 : process + begin + while 1 = 1 loop + wait until rising_edge(trg_valid_timing); + wait for 700 ns; + wait until falling_edge(clk); + wait for 200 ns; + wait until falling_edge(clk); + fee_trg_release(2) <= '1'; + wait until falling_edge(clk); + fee_trg_release(2) <= '0'; + fee_data_finished(2) <= '1'; + wait until falling_edge(clk); + fee_data_finished(2) <= '0'; + end loop; + end process; + +proc_write_data_4 : process + begin + while 1 = 1 loop + wait until rising_edge(trg_valid_timing); + wait for 700 ns; + wait until falling_edge(clk); + fee_data(127 downto 96) <= x"44440001"; + fee_data_write(3) <= '1'; + wait until falling_edge(clk); + fee_data_write(3) <= '0'; + wait for 200 ns; + wait until falling_edge(clk); + fee_trg_release(3) <= '1'; + wait until falling_edge(clk); + fee_trg_release(3) <= '0'; + fee_data_finished(3) <= '1'; + wait until falling_edge(clk); + fee_data_finished(3) <= '0'; + end loop; + end process; + +proc_write_data_5 : process + begin + while 1 = 1 loop + wait until rising_edge(trg_valid_timing); + wait for 700 ns; + wait until falling_edge(clk); + fee_data(159 downto 128) <= x"55550001"; + fee_data_write(4) <= '1'; + wait until falling_edge(clk); + fee_data_write(4) <= '0'; + wait for 200 ns; + wait until falling_edge(clk); + fee_trg_release(4) <= '1'; + wait until falling_edge(clk); + fee_trg_release(4) <= '0'; + fee_data_finished(4) <= '1'; + wait until falling_edge(clk); + fee_data_finished(4) <= '0'; + end loop; + end process; +proc_write_data_6 : process + begin + while 1 = 1 loop + wait until rising_edge(trg_valid_timing); + wait for 700 ns; + wait until falling_edge(clk); + fee_data(191 downto 160) <= x"66660001"; + fee_data_write(5) <= '1'; + wait until falling_edge(clk); + fee_data_write(5) <= '0'; + wait for 200 ns; + wait until falling_edge(clk); + fee_trg_release(5) <= '1'; + wait until falling_edge(clk); + fee_trg_release(5) <= '0'; + fee_data_finished(5) <= '1'; + wait until falling_edge(clk); + fee_data_finished(5) <= '0'; + end loop; + end process; proc_timer : process(CLK) begin diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 507755b..e9fb212 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -1207,7 +1207,7 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); begin if rising_edge(CLK) then gen_bits : for i in 0 to MII_NUMBER-1 loop - if MED_STAT_OP(i*16+7 downto i*16+4) = x"9" then + if MED_STAT_OP(i*16+15) = '0' and MED_STAT_OP(i*16+13) = '0' and MED_STAT_OP(i*16+7 downto i*16+4) = "0111" then mii_error(i) <= '1'; elsif STAT_REG_STROBE(16) = '1' then mii_error(i) <= '0'; @@ -1217,7 +1217,6 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); end process; - PROC_TIMEOUT : process(CLK) begin if rising_edge(CLK) then diff --git a/trb_net16_med_16_IC.vhd b/trb_net16_med_16_IC.vhd index eef805a..1667425 100644 --- a/trb_net16_med_16_IC.vhd +++ b/trb_net16_med_16_IC.vhd @@ -326,7 +326,7 @@ begin if pattern_valid_q = '1' then pattern_counter <= pattern_counter + "1"; elsif pattern_detected_q = '0' then - pattern_counter <= pattern_counter - x"40"; + pattern_counter <= pattern_counter - x"39"; end if; if pattern_counter < x"040" then link_state <= STARTUP; diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 0694e00..7c82c43 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -109,6 +109,8 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal wait_for_ack_max_bit : std_logic_vector(2 downto 0); signal timer_tick : std_logic; + signal reset_transmitted_buffers : std_logic; + attribute syn_preserve : boolean; attribute syn_keep : boolean; attribute syn_preserve of wait_for_ack_timeout : signal is true; @@ -482,7 +484,7 @@ begin reg_TRANSMITTED_BUFFERS : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then + if RESET = '1' or reset_transmitted_buffers = '1' then TRANSMITTED_BUFFERS <= "00"; buffer_number <= (others => '0'); elsif CLK_EN = '1' then