From: Ingo Froehlich Date: Thu, 30 Nov 2017 15:31:56 +0000 (+0100) Subject: changed amps2 to new flash and SPI scheme, IF X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0e4f3e9fdc9124f63932acd0728fa12d35ef55a4;p=padiwa.git changed amps2 to new flash and SPI scheme, IF --- diff --git a/amps2/padiwa_amps2.prj b/amps2/padiwa_amps2.prj index 03d5ddc..d7e790c 100644 --- a/amps2/padiwa_amps2.prj +++ b/amps2/padiwa_amps2.prj @@ -7,7 +7,8 @@ add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.9_x64/cae_library/synthesis/vhdl/machxo3lf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "workdir/version.vhd" -add_file -vhdl -lib work "../source/spi_slave.vhd" +#add_file -vhdl -lib work "../source/spi_slave.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd" add_file -vhdl -lib work "../source/Stretcher.vhd" add_file -vhdl -lib work "../source/Stretcher_A.vhd" add_file -vhdl -lib work "../source/Stretcher_B.vhd" @@ -25,6 +26,12 @@ add_file -vhdl -lib work "padiwa_amps2.vhd" #add_file -vhdl -lib work "../code/sedcheck.vhd" #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd" +add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd" +add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v" +add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB.v" +add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd" + #implementation: "PadiwaAmps2" impl -add workdir -type fpga diff --git a/amps2/padiwa_amps2.vhd b/amps2/padiwa_amps2.vhd index dfe77e8..d0dc111 100644 --- a/amps2/padiwa_amps2.vhd +++ b/amps2/padiwa_amps2.vhd @@ -52,10 +52,10 @@ architecture arch of padiwa_amps2 is signal led_timer : led_timer_t; signal led_state : std_logic_vector(8 downto 1); - signal ram_write_i : std_logic; - signal ram_data_i: std_logic_vector(7 downto 0); - signal ram_data_o: std_logic_vector(7 downto 0); - signal ram_addr_i: std_logic_vector(3 downto 0); +-- signal ram_write_i : std_logic; +-- signal ram_data_i: std_logic_vector(7 downto 0); +-- signal ram_data_o: std_logic_vector(7 downto 0); +-- signal ram_addr_i: std_logic_vector(3 downto 0); signal temperature_i : std_logic_vector(11 downto 0); @@ -63,18 +63,33 @@ architecture arch of padiwa_amps2 is signal INP_i : std_logic_vector(15 downto 0); signal fast_input : std_logic_vector(8 downto 1); signal slow_input : std_logic_vector(8 downto 1); - signal spi_reg00_i : std_logic_vector(15 downto 0); - signal spi_reg10_i : std_logic_vector(15 downto 0); - signal spi_reg20_i : std_logic_vector(15 downto 0); - signal spi_reg40_i : std_logic_vector(15 downto 0); - signal spi_data_i : std_logic_vector(15 downto 0); - signal spi_operation_i : std_logic_vector(3 downto 0); - signal spi_channel_i : std_logic_vector(7 downto 0); - signal spi_write_i : std_logic_vector(15 downto 0); - signal buf_SPI_OUT : std_logic; - signal spi_debug_i : std_logic_vector(15 downto 0); - signal last_spi_channel: std_logic_vector(7 downto 0); - +-- signal spi_reg00_i : std_logic_vector(15 downto 0); +-- signal spi_reg10_i : std_logic_vector(15 downto 0); +-- signal spi_reg20_i : std_logic_vector(15 downto 0); +-- signal spi_reg40_i : std_logic_vector(15 downto 0); +-- signal spi_data_i : std_logic_vector(15 downto 0); +-- signal spi_operation_i : std_logic_vector(3 downto 0); +-- signal spi_channel_i : std_logic_vector(7 downto 0); +-- signal spi_write_i : std_logic_vector(15 downto 0); +-- signal buf_SPI_OUT : std_logic; +-- signal spi_debug_i : std_logic_vector(15 downto 0); +-- signal last_spi_channel: std_logic_vector(7 downto 0); + signal spi_rx_data : std_logic_vector(15 downto 0); + signal spi_tx_data : std_logic_vector(15 downto 0); + signal spi_addr : std_logic_vector(7 downto 0); + signal bus_read : std_logic := '0'; + signal bus_write : std_logic := '0'; + signal bus_ready : std_logic; + signal bus_busy : std_logic; + + signal spi_data_out : std_logic_vector(15 downto 0); + signal spi_data_in : std_logic_vector(15 downto 0); + signal spi_addr_out : std_logic_vector(7 downto 0); + signal spi_write_out : std_logic; + signal spi_read_out : std_logic; + signal spi_ready_in : std_logic; + signal spi_busy_out : std_logic; + signal inp_select : integer range 0 to 31 := 0; @@ -167,41 +182,78 @@ THE_PLL : entity work.pll_in133_out33_133_266 --------------------------------------------------------------------------- -- SPI Interface --------------------------------------------------------------------------- -THE_SPI_SLAVE : entity work.spi_slave - port map( - CLK => clk_i, - SPI_CLK => SPI_CLK, - SPI_CS => SPI_CS, - SPI_IN => SPI_IN, - SPI_OUT => buf_SPI_OUT, - DATA_OUT => spi_data_i, - REG00_IN => spi_reg00_i, - REG10_IN => spi_reg10_i, - REG20_IN => spi_reg20_i, - REG40_IN => spi_reg40_i, - OPERATION_OUT => spi_operation_i, - CHANNEL_OUT => spi_channel_i, - WRITE_OUT => spi_write_i, - DEBUG_OUT => spi_debug_i - ); - -SPI_OUT <= buf_SPI_OUT; - -spi_reg00_i <= pwm_data_o; +--THE_SPI_SLAVE : entity work.spi_slave +-- port map( +-- CLK => clk_i, +-- SPI_CLK => SPI_CLK, +-- SPI_CS => SPI_CS, +-- SPI_IN => SPI_IN, +-- SPI_OUT => buf_SPI_OUT, +-- DATA_OUT => spi_data_i, +-- REG00_IN => spi_reg00_i, +-- REG10_IN => spi_reg10_i, +-- REG20_IN => spi_reg20_i, +-- REG40_IN => spi_reg40_i, +-- OPERATION_OUT => spi_operation_i, +-- CHANNEL_OUT => spi_channel_i, +-- WRITE_OUT => spi_write_i, +-- DEBUG_OUT => spi_debug_i +-- ); + +--SPI_OUT <= buf_SPI_OUT; + +--spi_reg00_i <= pwm_data_o; -- spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0)))); -- spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o; -spi_reg10_i <= (others => '0'); -spi_reg40_i <= '0' & '0' & "000000" & ram_data_o; - +--spi_reg10_i <= (others => '0'); +--spi_reg40_i <= '0' & '0' & "000000" & ram_data_o; ---------------------------------------------------------------------------- --- RAM Interface ---------------------------------------------------------------------------- +THE_SPI : entity work.spi_slave + port map( + CLK => clk_i, + SPI_CLK => SPI_CLK, + SPI_CS => SPI_CS, + SPI_IN => SPI_IN, + SPI_OUT => SPI_OUT, + + DATA_OUT => spi_data_out, + DATA_IN => spi_data_in, + ADDR_OUT => spi_addr_out, + WRITE_OUT => spi_write_out, + READ_OUT => spi_read_out, + READY_IN => spi_ready_in, + + DEBUG => open + ); --------------------------------------------------------------------------- -- Flash Controller --------------------------------------------------------------------------- +THE_FLASH_CONTROLLER : entity generic_flash_ctrl + port map( + CLK => clk_i, + RESET => '0', + + SPI_DATA_IN => spi_data_out, + SPI_DATA_OUT => spi_data_in, + SPI_ADDR_IN => spi_addr_out, + SPI_WRITE_IN => spi_write_out, + SPI_READ_IN => spi_read_out, + SPI_READY_OUT => spi_ready_in, + SPI_BUSY_IN => spi_busy_out, + + LOC_DATA_OUT => spi_rx_data, + LOC_DATA_IN => spi_tx_data, + LOC_ADDR_OUT => spi_addr, + LOC_WRITE_OUT => bus_write, + LOC_READ_OUT => bus_read, + LOC_READY_IN => bus_ready, + LOC_BUSY_OUT => bus_busy + ); + + + --------------------------------------------------------------------------- -- Temperature and UID reader --------------------------------------------------------------------------- @@ -215,64 +267,67 @@ temperature_i_s <= temperature_i when rising_edge(clk_33); comp_setting_s <= comp_setting when rising_edge(clk_33); temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_33); + gen_comp: if TEMP_CORRECTION = 1 generate compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_33); end generate; + gen_no_comp: if TEMP_CORRECTION = 0 generate compensate_i <= (others => '0'); -end generate; - - +end generate; + --------------------------------------------------------------------------- --- I/O Register 0x20 +-- I/O Register --------------------------------------------------------------------------- -THE_IO_REG_READ : process begin - wait until rising_edge(clk_i); - if spi_channel_i(4) = '0' then - case spi_channel_i(3 downto 0) is - when x"0" => spi_reg20_i <= input_enable; - when x"1" => spi_reg20_i <= inp_status; - when x"2" => spi_reg20_i <= x"0" & "000" & led_status(8) & led_state ; - when x"3" => spi_reg20_i <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5)); - when x"4" => spi_reg20_i <= inp_invert; - when x"5" => spi_reg20_i <= inp_stretch; - when x"6" => spi_reg20_i <= comp_setting; - when x"7" => spi_reg20_i <= x"00" & discharge_disable; - when x"8" => spi_reg20_i <= x"00" & discharge_override; - when x"9" => spi_reg20_i <= x"00" & discharge_highz; - when x"a" => spi_reg20_i <= x"00" & delay_invert; - when x"b" => spi_reg20_i <= x"00" & std_logic_vector(to_unsigned(delayselect,8)); --- when x"f" => spi_reg20_i <= ffarr_data; - when others => null; - end case; - else - case spi_channel_i(3 downto 0) is - when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16)); - when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16)); - when x"2" => spi_reg20_i <= x"0000"; - when others => null; - end case; - end if; -end process; -THE_IO_REG_WRITE : process begin +THE_IO_REG : process begin wait until rising_edge(clk_i); - if spi_write_i(2) = '1' then - case spi_channel_i(3 downto 0) is - when x"0" => input_enable <= spi_data_i; - when x"1" => null; - when x"2" => led_status <= spi_data_i(8 downto 0); - when x"3" => inp_select <= to_integer(unsigned(spi_data_i(4 downto 0))); - when x"4" => inp_invert <= spi_data_i; - when x"5" => inp_stretch <= spi_data_i; - when x"6" => comp_setting <= spi_data_i; - when x"7" => discharge_disable <= spi_data_i(7 downto 0); - when x"8" => discharge_override <= spi_data_i(7 downto 0); - when x"9" => discharge_highz <= spi_data_i(7 downto 0); - when x"a" => delay_invert <= spi_data_i(7 downto 0); - when x"b" => delayselect <= to_integer(unsigned(spi_data_i(7 downto 0))); + bus_ready <= '0'; + pwm_write_i <= '0'; + + if bus_read = '1' then + bus_ready <= '1'; + case spi_addr is + when x"20" => spi_tx_data <= input_enable; + when x"21" => spi_tx_data <= inp_status; + when x"22" => spi_tx_data <= x"0" & "000" & led_status(8) & led_state ; + when x"23" => spi_tx_data <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5)); + when x"24" => spi_tx_data <= inp_invert; + when x"25" => spi_tx_data <= inp_stretch; + when x"26" => spi_tx_data <= comp_setting; + when x"27" => spi_tx_data <= x"00" & discharge_disable; + when x"28" => spi_tx_data <= x"00" & discharge_override; + when x"29" => spi_tx_data <= x"00" & discharge_highz; + when x"2a" => spi_tx_data <= x"00" & delay_invert; + when x"2b" => spi_tx_data <= x"00" & std_logic_vector(to_unsigned(delayselect,8)); + + when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16)); + when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16)); + when x"32" => spi_tx_data <= x"0000"; when others => null; end case; + elsif bus_write = '1' then + if (spi_addr >= x"00") and (spi_addr < x"10") then -- write directly to PWM + pwm_data_i <= spi_rx_data; + pwm_addr_i <= spi_addr(3 downto 0); + pwm_write_i <= '1'; + else + case spi_addr is + when x"20" => input_enable <= spi_rx_data; + when x"21" => null; + when x"22" => led_status <= spi_rx_data(8 downto 0); + when x"23" => inp_select <= to_integer(unsigned(spi_rx_data(4 downto 0))); + when x"24" => inp_invert <= spi_rx_data; + when x"25" => inp_stretch <= spi_rx_data; + when x"26" => comp_setting <= spi_rx_data; + when x"27" => discharge_disable <= spi_rx_data(7 downto 0); + when x"28" => discharge_override <= spi_rx_data(7 downto 0); + when x"29" => discharge_highz <= spi_rx_data(7 downto 0); + when x"2a" => delay_invert <= spi_rx_data(7 downto 0); + when x"2b" => delayselect <= to_integer(unsigned(spi_rx_data(7 downto 0))); + when others => null; + end case; + end if; end if; end process; @@ -292,30 +347,6 @@ THE_PWM_GEN : entity work.pwm_generator ); - --- PROC_PWM_DATA_MUX : process(fsm_copydat, spi_data_i, spi_write_i, spi_channel_i, --- pwm_fsm_addr, pwm_fsm_data_i, pwm_fsm_write, --- ram_fsm_addr_i, ram_fsm_data_i, ram_fsm_write_i) --- begin --- if(fsm_copydat = IDLE) then - pwm_data_i <= spi_data_i; - pwm_write_i <= spi_write_i(0); - pwm_addr_i <= spi_channel_i(3 downto 0); - ram_write_i <= spi_write_i(4); - ram_data_i <= spi_data_i(7 downto 0); - ram_addr_i <= spi_channel_i(3 downto 0); --- else --- pwm_data_i <= pwm_fsm_data_i; --- pwm_write_i <= pwm_fsm_write; --- pwm_addr_i <= pwm_fsm_addr; --- ram_write_i <= ram_fsm_write_i; --- ram_data_i <= ram_fsm_data_i; --- ram_addr_i <= ram_fsm_addr_i; --- end if; --- end process; - - - --------------------------------------------------------------------------- -- LED ---------------------------------------------------------------------------