From: Jan Michel Date: Tue, 1 Dec 2015 17:59:21 +0000 (+0100) Subject: Adjusting timeout for external clock detection to allow for correct selection when... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0eab223285cb773e8b97f2b6a699274d91e0f7ef;p=trb3sc.git Adjusting timeout for external clock detection to allow for correct selection when powering up a crate with TRB3sc. --- diff --git a/adcaddon/config.vhd b/adcaddon/config.vhd index cc5efa4..700293a 100644 --- a/adcaddon/config.vhd +++ b/adcaddon/config.vhd @@ -13,6 +13,7 @@ package config is --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? --Use sync mode, RX clock for all parts of the FPGA constant USE_RXCLOCK : integer := c_NO; diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd index eb775b4..4fe7a18 100644 --- a/backplanemaster/config.vhd +++ b/backplanemaster/config.vhd @@ -14,6 +14,7 @@ package config is --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)? --Use sync mode, RX clock for all parts of the FPGA constant USE_RXCLOCK : integer := c_NO; diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 6ad71bd..77ba5d9 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -47,7 +47,7 @@ signal pll_int_lock, pll_ext_lock : std_logic; signal wait_for_lock : std_logic := '1'; signal clock_select : std_logic := '0'; -signal timer : unsigned(15 downto 0) := (others => '0'); +signal timer : unsigned(26 downto 0) := (others => '0'); signal clear_n_i : std_logic := '0'; signal reset_i : std_logic; @@ -169,10 +169,10 @@ gen_norecov_clock : if USE_RXCLOCK = c_NO generate process begin wait until rising_edge(INT_CLK_IN); - if timer(15) = '1' and timer(0) = '0' then --after 135us + if timer(26-CLOCK_FAST_SELECT*11) = '1' and timer(0) = '0' then --after 135us or 8.8ms timer <= timer + 1; clock_select <= pll_ext_lock; - elsif timer(15) = '1' and timer(0) = '1' then --after 135us plus 1 + elsif timer(26-CLOCK_FAST_SELECT*11) = '1' and timer(0) = '1' then --after 135us or 8.8ms plus 1 timer <= timer; else timer <= timer + 1; @@ -183,7 +183,7 @@ gen_norecov_clock : if USE_RXCLOCK = c_NO generate end generate; -clear_n_i <= timer(15) when rising_edge(INT_CLK_IN); +clear_n_i <= timer(26-CLOCK_FAST_SELECT*11) when rising_edge(INT_CLK_IN); --------------------------------------------------------------------------- -- Reset generation diff --git a/hubaddon/config.vhd b/hubaddon/config.vhd index 41269f7..13c11fe 100644 --- a/hubaddon/config.vhd +++ b/hubaddon/config.vhd @@ -14,6 +14,7 @@ package config is --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? --Use sync mode, RX clock for all parts of the FPGA constant USE_RXCLOCK : integer := c_NO; diff --git a/padiwa/config.vhd b/padiwa/config.vhd index 33017d2..2827b40 100644 --- a/padiwa/config.vhd +++ b/padiwa/config.vhd @@ -28,6 +28,7 @@ package config is --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? --Use sync mode, RX clock for all parts of the FPGA constant USE_RXCLOCK : integer := c_NO; diff --git a/pulser/config.vhd b/pulser/config.vhd index a56d795..1fb8e03 100644 --- a/pulser/config.vhd +++ b/pulser/config.vhd @@ -13,6 +13,7 @@ package config is --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? --Use sync mode, RX clock for all parts of the FPGA constant USE_RXCLOCK : integer := c_NO; diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd index add1aba..a91b01b 100644 --- a/tdctemplate/config.vhd +++ b/tdctemplate/config.vhd @@ -28,6 +28,7 @@ package config is --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? --Use sync mode, RX clock for all parts of the FPGA constant USE_RXCLOCK : integer := c_NO; diff --git a/template/config.vhd b/template/config.vhd index 8302114..baa4db7 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -13,6 +13,7 @@ package config is --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? --Use sync mode, RX clock for all parts of the FPGA constant USE_RXCLOCK : integer := c_NO; diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl index d3aaf19..f3d687d 100644 --- a/template/config_compile_frankfurt.pl +++ b/template/config_compile_frankfurt.pl @@ -2,10 +2,10 @@ TOPNAME => "trb3sc_basic", lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", lattice_path => '/d/jspc29/lattice/diamond/3.6_x64', -synplify_path => '/d/jspc29/lattice/synplify/J-2014.09-SP2/', +synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", -#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", - +# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", +# synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #", nodelist_file => 'nodelist_frankfurt.txt',