From: Jan Michel Date: Tue, 28 Jun 2022 14:53:46 +0000 (+0200) Subject: additional reset pulse for main PLL to prevent start-up issues after reload X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0f404910174850e07950f01a00bae85f3083ccf2;p=trb3sc.git additional reset pulse for main PLL to prevent start-up issues after reload --- diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index d23748b..671a3f2 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -54,9 +54,20 @@ signal reset_i : std_logic; signal debug_reset_handler : std_logic_vector(15 downto 0); signal send_reset_detect, trb_reset_i : std_logic := '0'; +signal pll_reset : std_logic := '0'; +signal pll_reset_counter : unsigned(13 downto 0) := (others => '0'); +signal osc_int : std_logic; + attribute syn_keep of clear_n_i : signal is true; attribute syn_preserve of clear_n_i : signal is true; +component OSCF + generic (NOM_FREQ: string := "133.00"); + port ( + OSC :OUT std_logic + ); +end component; + begin assert not (USE_RXCLOCK = c_YES and USE_200MHZOSCILLATOR = c_YES) report "RX Clock and 200 MHz oscillator not implemented" severity error; @@ -74,6 +85,21 @@ LED_RED_OUT(1) <= clock_select; GSR_OUT <= not pll_int_lock or clear_n_i; + + OSCInst0 : OSCF + generic map ( + NOM_FREQ => "2.5") + port map ( + OSC => osc_int); + +process begin + wait until rising_edge(osc_int); + if pll_reset_counter(pll_reset_counter'left) = '0' then + pll_reset_counter <= pll_reset_counter + 1; + end if; + pll_reset <= not pll_reset_counter(pll_reset_counter'left); +end process; + --------------------------------------------------------------------------- -- if RX clock is used, just forward what is provided, adjust internal as reference --------------------------------------------------------------------------- @@ -129,7 +155,8 @@ gen_norecov_clock : if USE_RXCLOCK = c_NO generate CLKOP => open, --200 CLKOS => clk_int_full, --same as OP, but for DCS CLKOK => clk_int_half, --100 - LOCK => pll_int_lock + LOCK => pll_int_lock, + RESET => pll_reset ); end generate; diff --git a/cores/pll_in200_out200.ipx b/cores/pll_in200_out200.ipx index 1a04856..dd57544 100644 --- a/cores/pll_in200_out200.ipx +++ b/cores/pll_in200_out200.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/cores/pll_in200_out200.lpc b/cores/pll_in200_out200.lpc index 9261469..4c916bd 100644 --- a/cores/pll_in200_out200.lpc +++ b/cores/pll_in200_out200.lpc @@ -16,8 +16,8 @@ CoreRevision=5.8 ModuleName=pll_in200_out200 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=12/18/2017 -Time=16:27:33 +Date=02/23/2022 +Time=12:35:23 [Parameters] Verilog=0 @@ -54,7 +54,7 @@ U_KFrq=100 OK_Tol=0.0 KFrq=100.000000 ClkRst=0 -PCDR=0 +PCDR=1 FINDELA=0 VcoRate= Bandwidth=2.970786 @@ -66,4 +66,4 @@ ClkOKBp=0 enClkOK2=0 [Command] -cmd_line= -w -n pll_in200_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 200 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw +cmd_line= -w -n pll_in200_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 200 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw diff --git a/cores/pll_in200_out200.vhd b/cores/pll_in200_out200.vhd index f576e91..c34226d 100644 --- a/cores/pll_in200_out200.vhd +++ b/cores/pll_in200_out200.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119 +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 -- Module Version: 5.7 ---/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 200 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_in200_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 200 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw --- Mon Dec 18 16:27:33 2017 +-- Wed Feb 23 12:35:23 2022 library IEEE; use IEEE.std_logic_1164.all; @@ -14,6 +14,7 @@ use ecp3.components.all; entity pll_in200_out200 is port ( CLK: in std_logic; + RESET: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; CLKOK: out std_logic; @@ -78,14 +79,13 @@ begin PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 1, CLKI_DIV=> 1, FIN=> "200.000000") - port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo, - RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, - DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, - DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, - DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, - FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, - CLKOS=>CLKOS_t, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, - CLKINTFB=>CLKFB_t); + port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>RESET, RSTK=>scuba_vlo, + WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, + DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, + DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, + FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, + FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>CLKFB_t); CLKOS <= CLKOS_t; CLKOP <= CLKOP_t;