From: hadaq <hadaq>
Date: Tue, 29 Jun 2010 09:01:06 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~251
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=0fc79d260ae8bb3c26b5348cfa45c28c57b50088;p=trbnet.git

*** empty log message ***
---

diff --git a/lattice/scm/trb_net16_fifo_arch.vhd b/lattice/scm/trb_net16_fifo_arch.vhd
index ffdedf5..b8aae5a 100644
--- a/lattice/scm/trb_net16_fifo_arch.vhd
+++ b/lattice/scm/trb_net16_fifo_arch.vhd
@@ -14,154 +14,145 @@ entity trb_net16_fifo is
       CLK    : in std_logic;
       RESET  : in std_logic;
       CLK_EN : in std_logic;
-      DATA_IN         : in  std_logic_vector(c_DATA_WIDTH - 1 downto 0);  -- Input data
+      DATA_IN         : in  std_logic_vector(15 downto 0);  -- Input data
       PACKET_NUM_IN   : in  std_logic_vector(1 downto 0);  -- Input data
       WRITE_ENABLE_IN : in  std_logic;
-      DATA_OUT        : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);  -- Output data
+      DATA_OUT        : out std_logic_vector(15 downto 0);  -- Output data
       PACKET_NUM_OUT  : out std_logic_vector(1 downto 0);  -- Input data
       READ_ENABLE_IN  : in  std_logic;
       FULL_OUT        : out std_logic;    -- Full Flag
-      EMPTY_OUT       : out std_logic;
-      DEPTH_OUT       : out std_logic_vector(7 downto 0)
+      EMPTY_OUT       : out std_logic
       );
 end entity;
 
 architecture arch_trb_net16_fifo of trb_net16_fifo is
-  component lattice_scm_fifo_18x1k is
+component lattice_scm_fifo_18x1k is
     port (
         Data: in  std_logic_vector(17 downto 0);
-        WrClock: in  std_logic;
-        RdClock: in  std_logic;
+        Clock: in  std_logic;
         WrEn: in  std_logic;
         RdEn: in  std_logic;
         Reset: in  std_logic;
-        RPReset: in  std_logic;
-        Q: out  std_logic_vector(17 downto 0);
-        Empty: out  std_logic;
-        Full: out  std_logic;
-        AlmostEmpty: out  std_logic;
-        AlmostFull: out  std_logic);
-  end component;
-
-  component lattice_scm_fifo_18x16 is
-    port (
-        Data: in  std_logic_vector(17 downto 0);
-        WrClock: in  std_logic;
-        RdClock: in  std_logic;
-        WrEn: in  std_logic;
-        RdEn: in  std_logic;
-        Reset: in  std_logic;
-        RPReset: in  std_logic;
-        Q: out  std_logic_vector(17 downto 0);
-        Empty: out  std_logic;
-        Full: out  std_logic);
-  end component;
-
-  component lattice_scm_fifo_18x32 is
-    port (
-        Data: in  std_logic_vector(17 downto 0);
-        WrClock: in  std_logic;
-        RdClock: in  std_logic;
-        WrEn: in  std_logic;
-        RdEn: in  std_logic;
-        Reset: in  std_logic;
-        RPReset: in  std_logic;
-        Q: out  std_logic_vector(17 downto 0);
-        Empty: out  std_logic;
-        Full: out  std_logic);
-  end component;
-
-  component lattice_scm_fifo_18x64 is
-    port (
-        Data: in  std_logic_vector(17 downto 0);
-        WrClock: in  std_logic;
-        RdClock: in  std_logic;
-        WrEn: in  std_logic;
-        RdEn: in  std_logic;
-        Reset: in  std_logic;
-        RPReset: in  std_logic;
         Q: out  std_logic_vector(17 downto 0);
         Empty: out  std_logic;
         Full: out  std_logic);
-  end component;
-
-
-  signal din, dout : std_logic_vector(17 downto 0);
-  signal depth16   : std_logic_vector(7 downto 0);
+end component;
+
+
+--   component lattice_scm_fifo_18x16 is
+--     port (
+--         Data: in  std_logic_vector(17 downto 0);
+--         WrClock: in  std_logic;
+--         RdClock: in  std_logic;
+--         WrEn: in  std_logic;
+--         RdEn: in  std_logic;
+--         Reset: in  std_logic;
+--         RPReset: in  std_logic;
+--         Q: out  std_logic_vector(17 downto 0);
+--         Empty: out  std_logic;
+--         Full: out  std_logic);
+--   end component;
+--
+--   component lattice_scm_fifo_18x32 is
+--     port (
+--         Data: in  std_logic_vector(17 downto 0);
+--         WrClock: in  std_logic;
+--         RdClock: in  std_logic;
+--         WrEn: in  std_logic;
+--         RdEn: in  std_logic;
+--         Reset: in  std_logic;
+--         RPReset: in  std_logic;
+--         Q: out  std_logic_vector(17 downto 0);
+--         Empty: out  std_logic;
+--         Full: out  std_logic);
+--   end component;
+--
+--   component lattice_scm_fifo_18x64 is
+--     port (
+--         Data: in  std_logic_vector(17 downto 0);
+--         WrClock: in  std_logic;
+--         RdClock: in  std_logic;
+--         WrEn: in  std_logic;
+--         RdEn: in  std_logic;
+--         Reset: in  std_logic;
+--         RPReset: in  std_logic;
+--         Q: out  std_logic_vector(17 downto 0);
+--         Empty: out  std_logic;
+--         Full: out  std_logic);
+--   end component;
+
+
+  signal din, dout : std_logic_vector(c_DATA_WIDTH +1 downto 0);
 
 begin
   din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN;
   din(c_DATA_WIDTH + 1 downto c_DATA_WIDTH) <= PACKET_NUM_IN;
   DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0);
   PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 1 downto c_DATA_WIDTH);
-  DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8));
 
-  gen_FIFO6 : if DEPTH = 6  generate
+--  gen_FIFO6 : if DEPTH = 6  generate
     fifo:lattice_scm_fifo_18x1k
       port map (
         Data     => din,
-        WrClock  => CLK,
-        RdClock  => CLK,
+        Clock    => CLK,
         WrEn     => WRITE_ENABLE_IN,
         RdEn     => READ_ENABLE_IN,
         Reset    => RESET,
-        RPReset  => RESET,
         Q        => dout,
         Empty    => EMPTY_OUT,
-        Full     => FULL_OUT,
-        AlmostEmpty => open,
-        AlmostFull  => open
+        Full     => FULL_OUT
         );
-  end generate;
-
-    gen_FIFO1 : if DEPTH = 1  generate
-      fifo:lattice_scm_fifo_18x16
-        port map (
-          Data     => din,
-          WrClock  => CLK,
-          RdClock  => CLK,
-          WrEn     => WRITE_ENABLE_IN,
-          RdEn     => READ_ENABLE_IN,
-          Reset    => RESET,
-          RPReset  => RESET,
-          Q        => dout,
-          Empty    => EMPTY_OUT,
-          Full     => FULL_OUT
-          );
-    end generate;
-
-    gen_FIFO2 : if DEPTH = 2  generate
-      fifo:lattice_scm_fifo_18x32
-        port map (
-          Data     => din,
-          WrClock  => CLK,
-          RdClock  => CLK,
-          WrEn     => WRITE_ENABLE_IN,
-          RdEn     => READ_ENABLE_IN,
-          Reset    => RESET,
-          RPReset  => RESET,
-          Q        => dout,
-          Empty    => EMPTY_OUT,
-          Full     => FULL_OUT
-          );
-    end generate;
-
-
-    gen_FIFO3 : if DEPTH = 3  generate
-      fifo:lattice_scm_fifo_18x64
-        port map (
-          Data     => din,
-          WrClock  => CLK,
-          RdClock  => CLK,
-          WrEn     => WRITE_ENABLE_IN,
-          RdEn     => READ_ENABLE_IN,
-          Reset    => RESET,
-          RPReset  => RESET,
-          Q        => dout,
-          Empty    => EMPTY_OUT,
-          Full     => FULL_OUT
-          );
-    end generate;
+--  end generate;
+
+
+--     gen_FIFO1 : if DEPTH = 1  generate
+--       fifo:lattice_scm_fifo_18x16
+--         port map (
+--           Data     => din,
+--           WrClock  => CLK,
+--           RdClock  => CLK,
+--           WrEn     => WRITE_ENABLE_IN,
+--           RdEn     => READ_ENABLE_IN,
+--           Reset    => RESET,
+--           RPReset  => RESET,
+--           Q        => dout,
+--           Empty    => EMPTY_OUT,
+--           Full     => FULL_OUT
+--           );
+--     end generate;
+--
+--     gen_FIFO2 : if DEPTH = 2  generate
+--       fifo:lattice_scm_fifo_18x32
+--         port map (
+--           Data     => din,
+--           WrClock  => CLK,
+--           RdClock  => CLK,
+--           WrEn     => WRITE_ENABLE_IN,
+--           RdEn     => READ_ENABLE_IN,
+--           Reset    => RESET,
+--           RPReset  => RESET,
+--           Q        => dout,
+--           Empty    => EMPTY_OUT,
+--           Full     => FULL_OUT
+--           );
+--     end generate;
+--
+--
+--     gen_FIFO3 : if DEPTH = 3  generate
+--       fifo:lattice_scm_fifo_18x64
+--         port map (
+--           Data     => din,
+--           WrClock  => CLK,
+--           RdClock  => CLK,
+--           WrEn     => WRITE_ENABLE_IN,
+--           RdEn     => READ_ENABLE_IN,
+--           Reset    => RESET,
+--           RPReset  => RESET,
+--           Q        => dout,
+--           Empty    => EMPTY_OUT,
+--           Full     => FULL_OUT
+--           );
+--     end generate;
 
 
 end architecture;