From: Thomas Gessler Date: Fri, 25 Sep 2020 12:44:45 +0000 (+0200) Subject: XCKU MGTs: Change from quads to individual links X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=10eaa14acc682ba0aa8303a9117c57e928ea24d0;p=trbnet.git XCKU MGTs: Change from quads to individual links This makes it easier to run the transceivers within a single quad as individual links with separate line rates. Additional changes: - Change from QPLL to CPLLs. - Provide a single top entity for multiple possible frequency/reference-clock combinations. - Remove GT reset logic and rely on the TrbNet reset logic. This is not fully compatible with GTH cores. In particular, RX PCS reset must be ignored. Otherwise, RX allow is asserted too early, and faulty data reaches the RX control state machine. - Change the default equalizer mode to LPM, which is more reliable that DFE for 8b10b data with non-random sequences. - Change the clock-correction sequences to 4 words: (K)BC (D)C5 (K)BC (D)50 and (K)BC (D)50 (K)BC (D)50 --- diff --git a/media_interfaces/med_xcku_sfp_sync.vhd b/media_interfaces/med_xcku_sfp_sync.vhd new file mode 100644 index 0000000..0a0d743 --- /dev/null +++ b/media_interfaces/med_xcku_sfp_sync.vhd @@ -0,0 +1,231 @@ +library ieee; +use ieee.std_logic_1164.all; + +library xpm; +use xpm.vcomponents.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; + +entity med_xcku_sfp_sync is + generic ( + IS_SYNC_SLAVE : integer := c_NO; + LINE_RATE_KBPS : integer := 2000000; + REFCLK_FREQ_HZ : integer := 100000000 + ); + port ( + SYSCLK : in std_logic; + CLK_100 : in std_logic; + GTREFCLK : in std_logic; + GTREFCLK_BUFG : in std_logic; + RXOUTCLK : out std_logic; + TXOUTCLK : out std_logic; + RXUSRCLK : in std_logic; + RXUSRCLK_DOUBLE : in std_logic; + TXUSRCLK : in std_logic; + TXUSRCLK_DOUBLE : in std_logic; + + RXUSRCLK_ACTIVE : in std_logic; + TXUSRCLK_ACTIVE : in std_logic; + RXPMARESETDONE : out std_logic; + TXPMARESETDONE : out std_logic; + + RESET : in std_logic; + CLEAR : in std_logic; + + RXN : in std_logic; + RXP : in std_logic; + TXN : out std_logic; + TXP : out std_logic; + + MEDIA_MED2INT : out MED2INT; + MEDIA_INT2MED : in INT2MED; + + RX_DLM : out std_logic := '0'; + RX_DLM_WORD : out std_logic_vector(7 downto 0) := (others => '0'); + TX_DLM : in std_logic := '0'; + TX_DLM_WORD : in std_logic_vector(7 downto 0) := (others => '0'); + + SD_LOS_IN : in std_logic; + SD_TXDIS_OUT : out std_logic; + + STAT_DEBUG : out std_logic_vector(63 downto 0); + CTRL_DEBUG : in std_logic_vector(63 downto 0) := (others => '0'); + + DRPADDR : in std_logic_vector(8 downto 0) := (others => '0'); + DRPCLK : in std_logic := '0'; + DRPDI : in std_logic_vector(15 downto 0) := (others => '0'); + DRPEN : in std_logic := '0'; + DRPWE : in std_logic := '0'; + DRPDO : out std_logic_vector(15 downto 0); + DRPRDY : out std_logic; + + EYESCANRESET : in std_logic := '0'; + RXLPMEN : in std_logic := '1'; + RXRATE : in std_logic_vector(2 downto 0) := b"000"; + TXDIFFCTRL : in std_logic_vector(3 downto 0) := b"1100"; + TXPOSTCURSOR : in std_logic_vector(4 downto 0) := b"00000"; + TXPRECURSOR : in std_logic_vector(4 downto 0) := b"00000" + ); +end entity; + + +architecture med_xcku_sfp_sync_arch of med_xcku_sfp_sync is + signal txdata : std_logic_vector(7 downto 0); + signal txcharisk : std_logic; + signal txchardispmode : std_logic; + signal rxdata : std_logic_vector(7 downto 0); + signal rxcharisk : std_logic; + signal rxnotintable : std_logic; + + signal rxpmareset : std_logic; + signal reset_all : std_logic; + + signal rx_cdr_lol : std_logic; + signal tx_lol : std_logic; + + signal rxpmaresetdone_i : std_logic; + signal txpmaresetdone_i : std_logic; + + signal debug_rx_control_i : std_logic_vector(31 downto 0); + signal debug_tx_control_i : std_logic_vector(31 downto 0); + + signal rx_los : std_logic; + signal sfp_los : std_logic; +begin + xpm_cdc_single_rx_los : xpm_cdc_single + generic map ( + DEST_SYNC_FF => 4, + INIT_SYNC_FF => 0, + SIM_ASSERT_CHK => 0, + SRC_INPUT_REG => 0 + ) + port map ( + dest_out => rx_los, + dest_clk => GTREFCLK_BUFG, + src_clk => '0', + src_in => SD_LOS_IN + ); + + xpm_cdc_single_sfp_los : xpm_cdc_single + generic map ( + DEST_SYNC_FF => 4, + INIT_SYNC_FF => 0, + SIM_ASSERT_CHK => 0, + SRC_INPUT_REG => 0 + ) + port map ( + dest_out => sfp_los, + dest_clk => SYSCLK, + src_clk => '0', + src_in => SD_LOS_IN + ); + + SD_TXDIS_OUT <= '0'; + + THE_SERDES : entity work.gth_xcku_top + generic map ( + LINE_RATE_KBPS => LINE_RATE_KBPS, + REFCLK_FREQ_HZ => REFCLK_FREQ_HZ + ) + port map ( + CLK_100 => CLK_100, + GTREFCLK => GTREFCLK, + RXOUTCLK => RXOUTCLK, + TXOUTCLK => TXOUTCLK, + RXUSRCLK => RXUSRCLK, + RXUSRCLK_DOUBLE => RXUSRCLK_DOUBLE, + TXUSRCLK => TXUSRCLK, + TXUSRCLK_DOUBLE => TXUSRCLK_DOUBLE, + RXUSRCLK_ACTIVE => RXUSRCLK_ACTIVE, + TXUSRCLK_ACTIVE => TXUSRCLK_ACTIVE, + RESET_ALL => reset_all, + RXPMARESET => rxpmareset, + RXPCSRESET => '0', + TXPMARESET => '0', + TXPCSRESET => '0', + INIT_DONE => open, + RXRESETDONE => open, + TXRESETDONE => open, + RXPMARESETDONE => rxpmaresetdone_i, + TXPMARESETDONE => txpmaresetdone_i, + RXBYTEISALIGNED => open, + RXN => RXN, + RXP => RXP, + TXN => TXN, + TXP => TXP, + TXDATA => txdata, + TXCHARISK => txcharisk, + TXCHARDISPMODE => txchardispmode, + TXCHARDISPVAL => '0', + RXDATA => rxdata, + RXCHARISK => rxcharisk, + RXCHARISCOMMA => open, + RXNOTINTABLE => rxnotintable, + RXDISPERR => open, + DRPADDR => DRPADDR, + DRPCLK => DRPCLK, + DRPDI => DRPDI, + DRPEN => DRPEN, + DRPWE => DRPWE, + DRPDO => DRPDO, + DRPRDY => DRPRDY, + EYESCANRESET => EYESCANRESET, + RXLPMEN => RXLPMEN, + RXRATE => RXRATE, + TXDIFFCTRL => TXDIFFCTRL, + TXPOSTCURSOR => TXPOSTCURSOR, + TXPRECURSOR => TXPRECURSOR + ); + + tx_lol <= not txpmaresetdone_i; + rx_cdr_lol <= not rxpmaresetdone_i; + + RXPMARESETDONE <= rxpmaresetdone_i; + TXPMARESETDONE <= txpmaresetdone_i; + + THE_MED_CONTROL : entity work.med_sync_control + generic map( + IS_SYNC_SLAVE => IS_SYNC_SLAVE, + IS_TX_RESET => 1 + ) + port map( + CLK_SYS => SYSCLK, + CLK_RXI => RXUSRCLK_DOUBLE, + CLK_RXHALF => RXUSRCLK, + CLK_TXI => TXUSRCLK_DOUBLE, + CLK_REF => GTREFCLK_BUFG, + RESET => RESET, + CLEAR => CLEAR, + SFP_LOS => sfp_los, + TX_LOL => tx_lol, + RX_CDR_LOL => rx_cdr_lol, + RX_LOS => rx_los, + WA_POSITION => (others => '0'), + RX_SERDES_RST => rxpmareset, + RX_PCS_RST => open, + QUAD_RST => reset_all, + TX_PCS_RST => open, + MEDIA_MED2INT => MEDIA_MED2INT, + MEDIA_INT2MED => MEDIA_INT2MED, + TX_DATA => txdata, + TX_K => txcharisk, + TX_CD => txchardispmode, + RX_DATA => rxdata, + RX_K => rxcharisk, + TX_DLM_WORD => TX_DLM_WORD, + TX_DLM => TX_DLM, + RX_DLM_WORD => RX_DLM_WORD, + RX_DLM => RX_DLM, + STAT_TX_CONTROL => open, + STAT_RX_CONTROL => open, + DEBUG_TX_CONTROL => debug_tx_control_i, + DEBUG_RX_CONTROL => debug_rx_control_i, + STAT_RESET => open + ); + + STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0); + STAT_DEBUG(15 downto 14) <= debug_tx_control_i(17 downto 16); +end architecture med_xcku_sfp_sync_arch; diff --git a/media_interfaces/med_xcku_sfp_sync_4.vhd b/media_interfaces/med_xcku_sfp_sync_4.vhd deleted file mode 100644 index 11dedfc..0000000 --- a/media_interfaces/med_xcku_sfp_sync_4.vhd +++ /dev/null @@ -1,219 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.med_sync_define.all; - -entity med_xcku_sfp_sync_4 is - generic ( - IS_SYNC_SLAVE : int_array_t(0 to 3) := (c_NO, c_NO, c_NO, c_NO); - IS_USED : int_array_t(0 to 3) := (c_YES, c_YES, c_YES, c_YES) - ); - port ( - SYSCLK : in std_logic; - CLK_200 : in std_logic; - GTREFCLK : in std_logic; - RXOUTCLK : out std_logic_vector(3 downto 0); - TXOUTCLK : out std_logic_vector(3 downto 0); - RXUSRCLK : in std_logic_vector(3 downto 0); - RXUSRCLK_DOUBLE : in std_logic_vector(3 downto 0); - TXUSRCLK : in std_logic_vector(3 downto 0); - TXUSRCLK_DOUBLE : in std_logic_vector(3 downto 0); - - RXUSRCLK_ACTIVE : in std_logic; - TXUSRCLK_ACTIVE : in std_logic; - RXPMARESETDONE : out std_logic_vector(3 downto 0); - TXPMARESETDONE : out std_logic_vector(3 downto 0); - - RESET : in std_logic; - CLEAR : in std_logic; - - RXN : in std_logic_vector(3 downto 0); - RXP : in std_logic_vector(3 downto 0); - TXN : out std_logic_vector(3 downto 0); - TXP : out std_logic_vector(3 downto 0); - - MEDIA_MED2INT : out med2int_array_t(0 to 3); - MEDIA_INT2MED : in int2med_array_t(0 to 3); - - RX_DLM : out std_logic_vector(3 downto 0) := x"0"; - RX_DLM_WORD : out std_logic_vector(31 downto 0) := (others => '0'); - TX_DLM : in std_logic_vector(3 downto 0) := x"0"; - TX_DLM_WORD : in std_logic_vector(31 downto 0) := (others => '0'); - - SD_LOS_IN : in std_logic_vector(3 downto 0); - SD_TXDIS_OUT : out std_logic_vector(3 downto 0); - - BUS_RX : in CTRLBUS_RX; - BUS_TX : out CTRLBUS_TX; - - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0'); - - DRPADDR : in std_logic_vector(35 downto 0) := (others => '0'); - DRPCLK : in std_logic_vector(3 downto 0) := (others => '0'); - DRPDI : in std_logic_vector(63 downto 0) := (others => '0'); - DRPEN : in std_logic_vector(3 downto 0) := (others => '0'); - DRPWE : in std_logic_vector(3 downto 0) := (others => '0'); - DRPDO : out std_logic_vector(63 downto 0); - DRPRDY : out std_logic_vector(3 downto 0); - - EYESCANRESET : in std_logic_vector(3 downto 0) := (others => '0'); - RXLPMEN : in std_logic_vector(3 downto 0) := (others => '0'); - RXRATE : in std_logic_vector(11 downto 0) := (others => '0'); - TXDIFFCTRL : in std_logic_vector(15 downto 0) := b"1100_1100_1100_1100"; - TXPOSTCURSOR : in std_logic_vector(19 downto 0) := (others => '0'); - TXPRECURSOR : in std_logic_vector(19 downto 0) := (others => '0') - ); -end entity; - - -architecture med_xcku_sfp_sync_4_arch of med_xcku_sfp_sync_4 is - signal txdata : std_logic_vector(31 downto 0); - signal txcharisk : std_logic_vector(3 downto 0); - signal txchardispmode : std_logic_vector(3 downto 0); - signal rxdata : std_logic_vector(31 downto 0); - signal rxcharisk : std_logic_vector(3 downto 0); - signal rxnotintable : std_logic_vector(3 downto 0); - - signal rxpmareset : std_logic_vector(3 downto 0); - signal txpcsreset : std_logic_vector(3 downto 0); - signal rxpcsreset : std_logic_vector(3 downto 0); - signal quad_rst : std_logic_vector(3 downto 0); - signal reset_all : std_logic; - - signal rx_los : std_logic_vector(3 downto 0); - signal rx_cdr_lol : std_logic_vector(3 downto 0); - signal tx_lol : std_logic; - - signal reset_tx_done : std_logic; - signal rxpmaresetdone_i : std_logic_vector(3 downto 0); - signal txpmaresetdone_i : std_logic_vector(3 downto 0); - - signal debug_rx_control_i : std_logic_vector(127 downto 0); - signal debug_tx_control_i : std_logic_vector(127 downto 0); -begin - SD_TXDIS_OUT <= (others =>'0'); - - reset_all <= quad_rst(0) or quad_rst(1) or quad_rst(2) or quad_rst(3); - - THE_SERDES : entity work.gth_xcku_quad_x0y2_top - port map ( - CLK_100 => SYSCLK, - GTREFCLK => GTREFCLK, - RXOUTCLK => RXOUTCLK, - TXOUTCLK => TXOUTCLK, - RXUSRCLK => RXUSRCLK, - RXUSRCLK_DOUBLE => RXUSRCLK_DOUBLE, - TXUSRCLK => TXUSRCLK, - TXUSRCLK_DOUBLE => TXUSRCLK_DOUBLE, - RXUSRCLK_ACTIVE => RXUSRCLK_ACTIVE, - TXUSRCLK_ACTIVE => TXUSRCLK_ACTIVE, - RESET_ALL => reset_all, - RXPMARESET => rxpmareset, - RXPCSRESET => rxpcsreset, - TXPMARESET => "0000", - TXPCSRESET => txpcsreset, - INIT_DONE => open, - RXRESETDONE => open, - TXRESETDONE => open, - RXPMARESETDONE => rxpmaresetdone_i, - TXPMARESETDONE => txpmaresetdone_i, - RXBYTEISALIGNED => open, - RXN => RXN, - RXP => RXP, - TXN => TXN, - TXP => TXP, - TXDATA => txdata, - TXCHARISK => txcharisk, - TXCHARDISPMODE => txchardispmode, - TXCHARDISPVAL => "0000", - RXDATA => rxdata, - RXCHARISK => rxcharisk, - RXCHARISCOMMA => open, - RXNOTINTABLE => rxnotintable, - RXDISPERR => open, - DRPADDR => DRPADDR, - DRPCLK => DRPCLK, - DRPDI => DRPDI, - DRPEN => DRPEN, - DRPWE => DRPWE, - DRPDO => DRPDO, - DRPRDY => DRPRDY, - EYESCANRESET => EYESCANRESET, - RXLPMEN => RXLPMEN, - RXRATE => RXRATE, - TXDIFFCTRL => TXDIFFCTRL, - TXPOSTCURSOR => TXPOSTCURSOR, - TXPRECURSOR => TXPRECURSOR - ); - - tx_lol <= not txpmaresetdone_i(0); - rx_cdr_lol <= not rxpmaresetdone_i; - - RXPMARESETDONE <= rxpmaresetdone_i; - TXPMARESETDONE <= txpmaresetdone_i; - - gen_control : for i in 0 to 3 generate - gen_used_control : if IS_USED(i) = c_YES generate - THE_MED_CONTROL : entity work.med_sync_control - generic map( - IS_SYNC_SLAVE => IS_SYNC_SLAVE(i), - IS_TX_RESET => 1 - ) - port map( - CLK_SYS => SYSCLK, - CLK_RXI => RXUSRCLK_DOUBLE(i), - CLK_RXHALF => RXUSRCLK(i), - CLK_TXI => TXUSRCLK_DOUBLE(i), - CLK_REF => CLK_200, - RESET => RESET, - CLEAR => CLEAR, - SFP_LOS => SD_LOS_IN(i), - TX_LOL => tx_lol, - RX_CDR_LOL => rx_cdr_lol(i), - RX_LOS => SD_LOS_IN(i), - WA_POSITION => (others => '0'), - RX_SERDES_RST => rxpmareset(i), - RX_PCS_RST => rxpcsreset(i), - QUAD_RST => quad_rst(i), - TX_PCS_RST => txpcsreset(i), - MEDIA_MED2INT => MEDIA_MED2INT(i), - MEDIA_INT2MED => MEDIA_INT2MED(i), - TX_DATA => txdata(8 * i + 7 downto 8 * i), - TX_K => txcharisk(i), - TX_CD => txchardispmode(i), - RX_DATA => rxdata(8 * i + 7 downto 8 * i), - RX_K => rxcharisk(i), - TX_DLM_WORD => TX_DLM_WORD(8 * i + 7 downto 8 * i), - TX_DLM => TX_DLM(i), - RX_DLM_WORD => RX_DLM_WORD(8 * i + 7 downto 8 * i), - RX_DLM => RX_DLM(i), - STAT_TX_CONTROL => open, - STAT_RX_CONTROL => open, - DEBUG_TX_CONTROL => debug_tx_control_i(32 * i + 31 downto 32 * i), - DEBUG_RX_CONTROL => debug_rx_control_i(32 * i + 31 downto 32 * i), - STAT_RESET => open - ); - end generate; - - gen_not_used : if IS_USED(i) = c_NO generate - MEDIA_MED2INT(i).dataready <= '0'; - MEDIA_MED2INT(i).tx_read <= '1'; - MEDIA_MED2INT(i).stat_op <= x"0007"; - end generate; - end generate; - - THE_BUS: - process is - begin - wait until rising_edge(SYSCLK); - BUS_TX.unknown <= BUS_RX.read or BUS_RX.write; - BUS_TX.ack <= '0'; - end process; - - STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0); - STAT_DEBUG(15 downto 14) <= debug_tx_control_i(17 downto 16); -end architecture; diff --git a/media_interfaces/xcku/common/gth_xcku_init.v b/media_interfaces/xcku/common/gth_xcku_init.v deleted file mode 100644 index 98491da..0000000 --- a/media_interfaces/xcku/common/gth_xcku_init.v +++ /dev/null @@ -1,288 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - - -`timescale 1ps/1ps - -// ===================================================================================================================== -// This example design initialization module provides a demonstration of how initialization logic can be constructed to -// interact with and enhance the reset controller helper block in order to assist with successful system bring-up. This -// example initialization logic monitors for timely reset completion, retrying resets as necessary to mitigate problems -// with system bring-up such as clock or data connection readiness. This is an example and can be modified as necessary. -// ===================================================================================================================== - -module gth_xcku_init # ( - - parameter real P_FREERUN_FREQUENCY = 100, - parameter real P_TX_TIMER_DURATION_US = 30000, - parameter real P_RX_TIMER_DURATION_US = 130000 - -)( - - input wire clk_freerun_in, - input wire reset_all_in, - input wire tx_init_done_in, - input wire rx_init_done_in, - input wire rx_data_good_in, - output reg reset_all_out = 1'b0, - output reg reset_rx_out = 1'b0, - output reg init_done_out = 1'b0, - output reg [3:0] retry_ctr_out = 4'd0 - -); - - - // ------------------------------------------------------------------------------------------------------------------- - // Synchronizers - // ------------------------------------------------------------------------------------------------------------------- - - // Synchronize the "reset all" input signal into the free-running clock domain - // The reset_all_in input should be driven by the master "reset all" example design input - wire reset_all_sync; - (* DONT_TOUCH = "TRUE" *) - gtwizard_ultrascale_v1_7_8_reset_synchronizer reset_synchronizer_reset_all_inst ( - .clk_in (clk_freerun_in), - .rst_in (reset_all_in), - .rst_out (reset_all_sync) - ); - - // Synchronize the TX initialization done indicator into the free-running clock domain - // The tx_init_done_in input should be driven by the signal or logical combination of signals that represents a - // completed TX initialization process; for example, the reset helper block gtwiz_reset_tx_done_out signal, or the - // logical AND of gtwiz_reset_tx_done_out with gtwiz_buffbypass_tx_done_out if the TX buffer is bypassed. - wire tx_init_done_sync; - (* DONT_TOUCH = "TRUE" *) - gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_tx_init_done_inst ( - .clk_in (clk_freerun_in), - .i_in (tx_init_done_in), - .o_out (tx_init_done_sync) - ); - - // Synchronize the RX initialization done indicator into the free-running clock domain - // The rx_init_done_in input should be driven by the signal or logical combination of signals that represents a - // completed RX initialization process; for example, the reset helper block gtwiz_reset_rx_done_out signal, or the - // logical AND of gtwiz_reset_rx_done_out with gtwiz_buffbypass_rx_done_out if the RX elastic buffer is bypassed. - wire rx_init_done_sync; - (* DONT_TOUCH = "TRUE" *) - gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_rx_init_done_inst ( - .clk_in (clk_freerun_in), - .i_in (rx_init_done_in), - .o_out (rx_init_done_sync) - ); - - // Synchronize the RX data good indicator into the free-running clock domain - // The rx_data_good_in input should be driven the user application's indication of continual good data reception. - // The example design drives rx_data_good_in high when no PRBS checker errors are seen in the 8 most recent - // consecutive clock cycles of data reception. - wire rx_data_good_sync; - (* DONT_TOUCH = "TRUE" *) - gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_rx_data_good_inst ( - .clk_in (clk_freerun_in), - .i_in (rx_data_good_in), - .o_out (rx_data_good_sync) - ); - - - // ------------------------------------------------------------------------------------------------------------------- - // Timer - // ------------------------------------------------------------------------------------------------------------------- - - // Declare registers and local parameters used for the shared TX and RX initialization timer - // The free-running clock frequency is specified by the P_FREERUN_FREQUENCY parameter. The TX initialization timer - // duration is specified by the P_TX_TIMER_DURATION_US parameter (default 30,000us), and the resulting terminal count - // is assigned to p_tx_timer_term_cyc_int. The RX initialization timer duration is specified by the - // P_RX_TIMER_DURATION_US parameter (default 130,000us), and the resulting terminal count is assigned to - // p_rx_timer_term_cyc_int. - reg timer_clr = 1'b1; - reg [24:0] timer_ctr = 25'd0; - reg tx_timer_sat = 1'b0; - reg rx_timer_sat = 1'b0; - wire [24:0] p_tx_timer_term_cyc_int = P_TX_TIMER_DURATION_US * P_FREERUN_FREQUENCY; - wire [24:0] p_rx_timer_term_cyc_int = P_RX_TIMER_DURATION_US * P_FREERUN_FREQUENCY; - - // When the timer is enabled by the initialization state machine, increment the timer_ctr counter until its value - // reaches p_rx_timer_term_cyc_int RX terminal count and rx_timer_sat is asserted. Assert tx_timer_sat when the - // counter value reaches the p_tx_timer_term_cyc_int TX terminal count. Clear the timer and remove assertions when the - // timer is disabled by the initialization state machine. - always @(posedge clk_freerun_in) begin - if (timer_clr) begin - timer_ctr <= 25'd0; - tx_timer_sat <= 1'b0; - rx_timer_sat <= 1'b0; - end - else begin - if (timer_ctr == p_tx_timer_term_cyc_int) - tx_timer_sat <= 1'b1; - - if (timer_ctr == p_rx_timer_term_cyc_int) - rx_timer_sat <= 1'b1; - else - timer_ctr <= timer_ctr + 25'd1; - end - end - - - // ------------------------------------------------------------------------------------------------------------------- - // Retry counter - // ------------------------------------------------------------------------------------------------------------------- - - // Increment the retry_ctr_out register for each TX or RX reset asserted by the initialization state machine until the - // register saturates at 4'd15. This value, which is initialized on device programming and is never reset, could be - // useful for debugging purposes. The initialization state machine will continue to retry as needed beyond the retry - // register saturation point indicated, so 4'd15 should be interpreted as "15 or more attempts since programming." - reg retry_ctr_incr = 1'b0; - - always @(posedge clk_freerun_in) begin - if ((retry_ctr_incr == 1'b1) && (retry_ctr_out != 4'd15)) - retry_ctr_out <= retry_ctr_out + 4'd1; - end - - - // ------------------------------------------------------------------------------------------------------------------- - // Initialization state machine - // ------------------------------------------------------------------------------------------------------------------- - - // Declare local parameters and state register for the initialization state machine - localparam [1:0] ST_START = 2'd0; - localparam [1:0] ST_TX_WAIT = 2'd1; - localparam [1:0] ST_RX_WAIT = 2'd2; - localparam [1:0] ST_MONITOR = 2'd3; - reg [1:0] sm_init = ST_START; - reg sm_init_active = 1'b0; - - // Implement the initialization state machine control and its outputs as a single sequential process. The state - // machine is reset by the synchronized reset_all_in input, and does not begin operating until its first use. Note - // that this state machine is designed to interact with and enhance the reset controller helper block. - always @(posedge clk_freerun_in) begin - if (reset_all_sync) begin - timer_clr <= 1'b1; - reset_all_out <= 1'b0; - reset_rx_out <= 1'b0; - retry_ctr_incr <= 1'b0; - init_done_out <= 1'b0; - sm_init_active <= 1'b1; - sm_init <= ST_START; - end - else begin - case (sm_init) - - // When starting the initialization procedure, clear the timer and remove reset outputs, then proceed to wait - // for completion of TX initialization - ST_START: begin - if (sm_init_active) begin - timer_clr <= 1'b1; - reset_all_out <= 1'b0; - reset_rx_out <= 1'b0; - retry_ctr_incr <= 1'b0; - sm_init <= ST_TX_WAIT; - end - end - - // Enable the timer. If TX initialization completes before the counter's TX terminal count, clear the timer and - // proceed to wait for RX initialization. If the TX terminal count is reached, clear the timer, assert the - // reset_all_out output (which in this example causes a master reset_all assertion), and increment the retry - // counter. Completion conditions for TX initialization are described above. - ST_TX_WAIT: begin - if (tx_init_done_sync) begin - timer_clr <= 1'b1; - sm_init <= ST_RX_WAIT; - end - else begin - if (tx_timer_sat) begin - timer_clr <= 1'b1; - reset_all_out <= 1'b1; - retry_ctr_incr <= 1'b1; - sm_init <= ST_START; - end - else begin - timer_clr <= 1'b0; - end - end - end - - // Enable the timer. When the RX terminal count is reached, check whether RX initialization has completed and - // whether the data good indicator is high. If both conditions are met, transition to the MONITOR state. If - // either condition is not met, then clear the timer, assert the reset_rx_out output (which in this example - // either drives gtwiz_reset_rx_pll_and_datapath_in or gtwiz_reset_rx_datapath_in, depending on PLL sharing), - // and increnent the retry counter. - ST_RX_WAIT: begin - if (rx_timer_sat) begin - if (rx_init_done_sync && rx_data_good_sync) begin - init_done_out <= 1'b1; - sm_init <= ST_MONITOR; - end - else begin - timer_clr <= 1'b1; - reset_rx_out <= 1'b1; - retry_ctr_incr <= 1'b1; - sm_init <= ST_START; - end - end - else begin - timer_clr <= 1'b0; - end - end - - // In this MONITOR state, assert the init_done_out output for use as desired. If RX initialization or the data - // good indicator is lost while in this state, reset the RX components as described in the ST_RX_WAIT state. - ST_MONITOR: begin - if (~rx_init_done_sync || ~rx_data_good_sync) begin - init_done_out <= 1'b0; - timer_clr <= 1'b1; - reset_rx_out <= 1'b1; - retry_ctr_incr <= 1'b1; - sm_init <= ST_START; - end - end - - endcase - end - end - - -endmodule diff --git a/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_bit_sync.v b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_bit_sync.v deleted file mode 100644 index b093c9c..0000000 --- a/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_bit_sync.v +++ /dev/null @@ -1,88 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - -// *************************** -// * DO NOT MODIFY THIS FILE * -// *************************** - -`timescale 1ps/1ps - -module gtwizard_ultrascale_v1_7_8_bit_synchronizer # ( - - parameter INITIALIZE = 5'b00000, - parameter FREQUENCY = 512 - -)( - - input wire clk_in, - input wire i_in, - output wire o_out - -); - - // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to - // enable clustering. Their GSR default values are provided by the INITIALIZE parameter. - - (* ASYNC_REG = "TRUE" *) reg i_in_meta = INITIALIZE[0]; - (* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1]; - (* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2]; - (* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3]; - reg i_in_out = INITIALIZE[4]; - - always @(posedge clk_in) begin - i_in_meta <= i_in; - i_in_sync1 <= i_in_meta; - i_in_sync2 <= i_in_sync1; - i_in_sync3 <= i_in_sync2; - i_in_out <= i_in_sync3; - end - - assign o_out = i_in_out; - - -endmodule diff --git a/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_reset_sync.v b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_reset_sync.v deleted file mode 100644 index 6ddf260..0000000 --- a/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_reset_sync.v +++ /dev/null @@ -1,98 +0,0 @@ -//------------------------------------------------------------------------------ -// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//------------------------------------------------------------------------------ - -// *************************** -// * DO NOT MODIFY THIS FILE * -// *************************** - -`timescale 1ps/1ps - -module gtwizard_ultrascale_v1_7_8_reset_synchronizer # ( - - parameter FREQUENCY = 512 - -)( - - input wire clk_in, - input wire rst_in, - output wire rst_out - -); - - // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to - // enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also - // asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the - // downstream logic is also removed from reset synchronously. This module is designed for active-high reset use. - - (* ASYNC_REG = "TRUE" *) reg rst_in_meta = 1'b0; - (* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0; - (* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0; - (* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0; - reg rst_in_out = 1'b0; - - always @(posedge clk_in, posedge rst_in) begin - if (rst_in) begin - rst_in_meta <= 1'b1; - rst_in_sync1 <= 1'b1; - rst_in_sync2 <= 1'b1; - rst_in_sync3 <= 1'b1; - rst_in_out <= 1'b1; - end - else begin - rst_in_meta <= 1'b0; - rst_in_sync1 <= rst_in_meta; - rst_in_sync2 <= rst_in_sync1; - rst_in_sync3 <= rst_in_sync2; - rst_in_out <= rst_in_sync3; - end - end - - assign rst_out = rst_in_out; - - -endmodule diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci b/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci similarity index 95% rename from media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci rename to media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci index 6e79fe7..6e88795 100644 --- a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci +++ b/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci @@ -6,12 +6,12 @@ 1.0 - gth_xcku_quad_x0y2 + gth_xcku_2gbps0_100mhz - "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000" + "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000" 1 - 2578.125 + 2000.0 0 0 100 @@ -36,16 +36,16 @@ "00000000" "00000000" 1 - 2 + 1 0 "00000000000000000000000000000000000000000000000000000000000000000000000000000000" "00000000" 1 - "00100010" - 2 + "01010101" + 4 2 5000 - "00000000000000000000001011110000110001010000000000000000000000101111000001010000" + "00010100000010111100000101000000101111000001010000001011110000110001010010111100" 1 "1010000011" 1 @@ -58,7 +58,7 @@ 1 100.0000000 1 - 0 + 2 0x000000000000000000000000000000000000000000000000 100 0 @@ -73,11 +73,11 @@ 0 257.8125 1 - 4 - 1 + 1 + 0 0 0 - 0 + 2 100 0 0 @@ -90,7 +90,7 @@ 1 100.0000000 1 - 0 + 2 100 0 0 @@ -101,8 +101,8 @@ 100.0000000 100.0000000 0 - X0Y11 X0Y10 X0Y9 X0Y8 - gth_xcku_quad_x0y2 + X0Y8 + gth_xcku_2gbps0_100mhz 0 0 rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpmareset_in rxresetdone_out txresetdone_out @@ -113,15 +113,15 @@ 2 20 96 - 3 + 5 gthe3 - 1 + 0 0 - 0 - 0 - 0 - 0 - 0 + -1 + -1 + -1 + -1 + -1 0 0 0 @@ -138,7 +138,7 @@ 0 0 0 - 0 + -1 0 0 0 @@ -146,20 +146,20 @@ 0 -1 0 - 0 + -1 1 - 0 + -1 0 - 0 + -1 1 - 0 + -1 1 - 0 + -1 1 - 0 + -1 1 -1 - 0 + -1 1 -1 -1 @@ -174,36 +174,36 @@ 1 0 -1 - 0 - 0 + -1 + -1 0 1 1 1 1 - 0 - 0 + -1 + -1 0 - 0 - 0 + -1 + -1 0 1 - 1 - 0 - 0 - 0 - 0 + -1 + -1 + 1 + -1 + -1 0 0 0 0 -1 -1 - 0 - 0 + -1 + -1 0 - 0 - 0 + -1 + -1 0 -1 -1 @@ -281,53 +281,53 @@ 0 0 0 - 0 - 0 + -1 + -1 0 - 0 - 0 + -1 + -1 -1 - 0 - 0 - -1 - 0 + -1 + -1 + 0 + -1 -1 -1 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 0 -1 - 0 - 0 - -1 - 0 + -1 + -1 + 0 + -1 -1 -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + 0 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 + -1 0 0 0 @@ -489,9 +489,9 @@ 0 1 -1 - 0 + -1 -1 - 0 + -1 0 0 0 @@ -651,13 +651,13 @@ -1 -1 -1 - 17 + 18 0 None 8 100.0000000 - 4 - 1 + 1 + 0 100.0000000 true CORE @@ -710,7 +710,7 @@ false false false - 2 + 1 1 0 00000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -731,17 +731,17 @@ false false false - 00100010 + 01010101 ENABLE - false - true - false + true + false + true false - false - true - false + true + false + true false - 2 + 4 00000000 false false @@ -755,15 +755,15 @@ 5000 ENABLE 0 - 00000000000000000000001011110000110001010000000000000000000000101111000001010000 - 01010000 - 10111100 - 00000000 - 00000000 - 11000101 - 10111100 - 00000000 - 00000000 + 00010100000010111100000101000000101111000001010000001011110000110001010010111100 + 10111100 + 11000101 + 10111100 + 01010000 + 10111100 + 01010000 + 10111100 + 01010000 2 false 1111111111 @@ -777,14 +777,14 @@ AC 8B10B true - AUTO + LPM 20 1.19976 -20 2 X0Y8 RXOUTCLKPMA - QPLL0 + CPLL 0 0 @@ -802,7 +802,7 @@ 257.8125 1 false - QPLL0 + CPLL 100 1 ENABLE @@ -813,7 +813,7 @@ 2 X0Y8 TXOUTCLKPMA - QPLL0 + CPLL 0 100 @@ -890,9 +890,9 @@ false false true - true + false false - false + true false false false @@ -998,8 +998,8 @@ false false false - true - true + false + false false false false @@ -1378,37 +1378,45 @@ - - - - + + + + + + + + + + + + diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml b/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xml similarity index 95% rename from media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml rename to media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xml index 26f5a0c..acdf8a6 100644 --- a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xml +++ b/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xml @@ -2,7 +2,7 @@ xilinx.com customized_ip - gth_xcku_quad_x0y2 + gth_xcku_2gbps0_100mhz 1.0 @@ -14,7 +14,7 @@ outputProductCRC - 9:fde239e5 + 9:5d220aeb @@ -970,7 +970,7 @@ in - 71 + 17 0 @@ -997,7 +997,7 @@ in - 71 + 17 0 @@ -1024,7 +1024,7 @@ in - 3 + 0 0 @@ -1051,7 +1051,7 @@ in - 71 + 17 0 @@ -1078,7 +1078,7 @@ in - 71 + 17 0 @@ -1105,7 +1105,7 @@ in - 3 + 0 0 @@ -1132,7 +1132,7 @@ in - 71 + 17 0 @@ -1159,7 +1159,7 @@ in - 71 + 17 0 @@ -1186,7 +1186,7 @@ in - 3 + 0 0 @@ -1213,7 +1213,7 @@ in - 63 + 15 0 @@ -1240,7 +1240,7 @@ out - 63 + 15 0 @@ -1283,6 +1283,7 @@ + illegal false @@ -1309,6 +1310,7 @@ + illegal false @@ -1335,6 +1337,7 @@ + illegal false @@ -1361,6 +1364,7 @@ + illegal false @@ -1387,6 +1391,7 @@ + illegal false @@ -1413,6 +1418,7 @@ + illegal false @@ -1439,6 +1445,7 @@ + illegal false @@ -1465,6 +1472,7 @@ + illegal false @@ -1491,6 +1499,7 @@ + illegal false @@ -1517,6 +1526,7 @@ + illegal false @@ -1543,6 +1553,7 @@ + illegal false @@ -1569,6 +1580,7 @@ + illegal false @@ -1595,6 +1607,7 @@ + illegal false @@ -1621,6 +1634,7 @@ + illegal false @@ -1647,6 +1661,7 @@ + illegal false @@ -1673,6 +1688,7 @@ + illegal false @@ -1693,14 +1709,14 @@ - 0 + 0x0 - required - true + illegal + false @@ -1726,6 +1742,7 @@ + illegal false @@ -1752,6 +1769,7 @@ + illegal false @@ -1778,6 +1796,7 @@ + illegal false @@ -1804,6 +1823,7 @@ + illegal false @@ -1830,6 +1850,7 @@ + illegal false @@ -1856,6 +1877,7 @@ + illegal false @@ -1882,6 +1904,7 @@ + illegal false @@ -1962,6 +1985,7 @@ + illegal false @@ -1988,6 +2012,7 @@ + illegal false @@ -2014,6 +2039,7 @@ + illegal false @@ -2040,6 +2066,7 @@ + illegal false @@ -2093,6 +2120,7 @@ + illegal false @@ -2113,12 +2141,13 @@ - 0x1 + 0x0 + illegal false @@ -2139,12 +2168,13 @@ - 0x0 + 0x1 + illegal false @@ -2171,6 +2201,7 @@ + illegal false @@ -2191,7 +2222,7 @@ - 0x0 + 0x1 @@ -2224,6 +2255,7 @@ + illegal false @@ -2250,6 +2282,7 @@ + illegal false @@ -2303,6 +2336,7 @@ + illegal false @@ -2329,6 +2363,7 @@ + illegal false @@ -2355,6 +2390,7 @@ + illegal false @@ -2381,6 +2417,7 @@ + illegal false @@ -2407,6 +2444,7 @@ + illegal false @@ -2433,6 +2471,7 @@ + illegal false @@ -2459,6 +2498,7 @@ + illegal false @@ -2485,6 +2525,7 @@ + illegal false @@ -2511,6 +2552,7 @@ + illegal false @@ -2537,6 +2579,7 @@ + illegal false @@ -3319,6 +3362,7 @@ + illegal false @@ -3345,6 +3389,7 @@ + illegal false @@ -3371,6 +3416,7 @@ + illegal false @@ -3397,6 +3443,7 @@ + illegal false @@ -3423,6 +3470,7 @@ + illegal false @@ -3449,6 +3497,7 @@ + illegal false @@ -3475,8 +3524,8 @@ - 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0x000000 + 0x00 @@ -9986,7 +10045,7 @@ in - 3 + 0 0 @@ -9996,7 +10055,7 @@ - 0x0 + 0x0 @@ -10012,7 +10071,7 @@ in - 3 + 0 0 @@ -10022,7 +10081,7 @@ - 0x0 + 0x0 @@ -10119,7 +10178,7 @@ in - 27 + 6 0 @@ -10129,7 +10188,7 @@ - 0x8102040 + 0x40 @@ -10145,7 +10204,7 @@ in - 11 + 2 0 @@ -10155,7 +10214,7 @@ - 0x000 + 0x0 @@ -10252,7 +10311,7 @@ in - 11 + 2 0 @@ -10262,7 +10321,7 @@ - 0x492 + 0x2 @@ -10278,7 +10337,7 @@ in - 3 + 0 0 @@ -10304,7 +10363,7 @@ in - 7 + 1 0 @@ -10314,7 +10373,7 @@ - 0x00 + 0x0 @@ -10330,7 +10389,7 @@ in - 3 + 0 0 @@ -10340,7 +10399,7 @@ - 0x0 + 0x0 @@ -10356,7 +10415,7 @@ in - 3 + 0 0 @@ -10366,7 +10425,7 @@ - 0x0 + 0x0 @@ -10382,7 +10441,7 @@ in - 3 + 0 0 @@ -10392,7 +10451,7 @@ - 0x0 + 0x0 @@ -10408,7 +10467,7 @@ in - 3 + 0 0 @@ -10418,7 +10477,7 @@ - 0xF + 0x1 @@ -10434,7 +10493,7 @@ in - 3 + 0 0 @@ -10444,7 +10503,7 @@ - 0x0 + 0x0 @@ -10460,7 +10519,7 @@ in - 3 + 0 0 @@ -10470,7 +10529,7 @@ - 0x0 + 0x0 @@ -10486,7 +10545,7 @@ in - 3 + 0 0 @@ -10496,7 +10555,7 @@ - 0x0 + 0x0 @@ -10512,7 +10571,7 @@ in - 3 + 0 0 @@ -10522,7 +10581,7 @@ - 0x0 + 0x0 @@ -10538,7 +10597,7 @@ in - 3 + 0 0 @@ -10548,7 +10607,7 @@ - 0x0 + 0x0 @@ -10564,7 +10623,7 @@ in - 3 + 0 0 @@ -10574,7 +10633,7 @@ - 0x0 + 0x0 @@ -10590,7 +10649,7 @@ in - 3 + 0 0 @@ -10600,7 +10659,7 @@ - 0x0 + 0x0 @@ -10616,7 +10675,7 @@ in - 3 + 0 0 @@ -10626,7 +10685,7 @@ - 0x0 + 0x0 @@ -10642,7 +10701,7 @@ in - 19 + 4 0 @@ -10652,7 +10711,7 @@ - 0x00000 + 0x00 @@ -10668,7 +10727,7 @@ in - 3 + 0 0 @@ -10678,7 +10737,7 @@ - 0x0 + 0x0 @@ -10694,7 +10753,7 @@ in - 7 + 1 0 @@ -10704,7 +10763,7 @@ - 0xFF + 0x0 @@ -10720,7 +10779,7 @@ in - 3 + 0 0 @@ -10746,7 +10805,7 @@ in - 3 + 0 0 @@ -10756,7 +10815,7 @@ - 0x0 + 0x0 @@ -10772,7 +10831,7 @@ in - 19 + 4 0 @@ -10782,7 +10841,7 @@ - 0x00000 + 0 @@ -10799,7 +10858,7 @@ in - 3 + 0 0 @@ -10809,7 +10868,7 @@ - 0x0 + 0x0 @@ -10825,7 +10884,7 @@ in - 3 + 0 0 @@ -10835,7 +10894,7 @@ - 0x0 + 0x0 @@ -10851,7 +10910,7 @@ in - 15 + 3 0 @@ -10861,7 +10920,7 @@ - 0x0000 + 0x0 @@ -10877,7 +10936,7 @@ in - 19 + 4 0 @@ -10887,7 +10946,7 @@ - 0x00000 + 0 @@ -10904,7 +10963,7 @@ in - 3 + 0 0 @@ -10914,7 +10973,7 @@ - 0x0 + 0x0 @@ -10930,7 +10989,7 @@ in - 3 + 0 0 @@ -10940,7 +10999,7 @@ - 0x0 + 0x0 @@ -10957,7 +11016,7 @@ in - 3 + 0 0 @@ -10967,7 +11026,7 @@ - 0x0 + 0x0 @@ -10983,7 +11042,7 @@ in - 3 + 0 0 @@ -10993,7 +11052,7 @@ - 0x0 + 0x0 @@ -11009,7 +11068,7 @@ in - 3 + 0 0 @@ -11019,7 +11078,7 @@ - 0x0 + 0x0 @@ -11035,7 +11094,7 @@ in - 11 + 2 0 @@ -11045,7 +11104,7 @@ - 0x000 + 0x0 @@ -11061,7 +11120,7 @@ in - 3 + 0 0 @@ -11071,7 +11130,7 @@ - 0x0 + 0x0 @@ -11087,7 +11146,7 @@ in - 27 + 6 0 @@ -11097,7 +11156,7 @@ - 0x0000000 + 0x00 @@ -11113,7 +11172,7 @@ in - 3 + 0 0 @@ -11123,7 +11182,7 @@ - 0x0 + 0x0 @@ -11139,7 +11198,7 @@ in - 3 + 0 0 @@ -11149,7 +11208,7 @@ - 0x0 + 0x0 @@ -11165,7 +11224,7 @@ in - 3 + 0 0 @@ -11175,7 +11234,7 @@ - 0x0 + 0x0 @@ -11191,7 +11250,7 @@ in - 3 + 0 0 @@ -11201,7 +11260,7 @@ - 0x0 + 0x0 @@ -11217,7 +11276,7 @@ in - 7 + 1 0 @@ -11227,7 +11286,7 @@ - 0xAA + 0x0 @@ -11243,7 +11302,7 @@ in - 3 + 0 0 @@ -11253,7 +11312,7 @@ - 0xF + 0x1 @@ -11270,7 +11329,7 @@ in - 3 + 0 0 @@ -11297,7 +11356,7 @@ in - 3 + 0 0 @@ -11324,7 +11383,7 @@ out - 11 + 2 0 @@ -11350,7 +11409,7 @@ out - 11 + 2 0 @@ -11376,7 +11435,7 @@ out - 35 + 8 0 @@ -11402,7 +11461,7 @@ out - 11 + 2 0 @@ -11428,7 +11487,7 @@ out - 11 + 2 0 @@ -11454,7 +11513,7 @@ out - 3 + 0 0 @@ -11480,7 +11539,7 @@ out - 3 + 0 0 @@ -11506,7 +11565,7 @@ out - 3 + 0 0 @@ -11532,7 +11591,7 @@ out - 67 + 16 0 @@ -11585,7 +11644,7 @@ out - 63 + 15 0 @@ -11612,7 +11671,7 @@ out - 3 + 0 0 @@ -11639,7 +11698,7 @@ out - 3 + 0 0 @@ -11665,7 +11724,7 @@ out - 3 + 0 0 @@ -11692,7 +11751,7 @@ out - 3 + 0 0 @@ -11719,7 +11778,7 @@ out - 3 + 0 0 @@ -11746,7 +11805,7 @@ out - 3 + 0 0 @@ -11826,7 +11885,7 @@ out - 3 + 0 0 @@ -11852,7 +11911,7 @@ out - 3 + 0 0 @@ -11878,7 +11937,7 @@ out - 7 + 1 0 @@ -11904,7 +11963,7 @@ out - 7 + 1 0 @@ -11930,7 +11989,7 @@ out - 3 + 0 0 @@ -11956,7 +12015,7 @@ out - 3 + 0 0 @@ -11982,7 +12041,7 @@ out - 3 + 0 0 @@ -12008,7 +12067,7 @@ out - 3 + 0 0 @@ -12034,7 +12093,7 @@ out - 47 + 11 0 @@ -12060,7 +12119,7 @@ out - 3 + 0 0 @@ -12086,7 +12145,7 @@ out - 31 + 7 0 @@ -12139,7 +12198,7 @@ out - 3 + 0 0 @@ -12165,7 +12224,7 @@ out - 11 + 2 0 @@ -12192,7 +12251,7 @@ out - 3 + 0 0 @@ -12219,7 +12278,7 @@ out - 3 + 0 0 @@ -12246,7 +12305,7 @@ out - 3 + 0 0 @@ -12272,7 +12331,7 @@ out - 3 + 0 0 @@ -12298,7 +12357,7 @@ out - 3 + 0 0 @@ -12324,7 +12383,7 @@ out - 3 + 0 0 @@ -12350,7 +12409,7 @@ out - 3 + 0 0 @@ -12376,7 +12435,7 @@ out - 19 + 4 0 @@ -12429,7 +12488,7 @@ out - 7 + 1 0 @@ -12456,7 +12515,7 @@ out - 3 + 0 0 @@ -12482,7 +12541,7 @@ out - 3 + 0 0 @@ -12509,7 +12568,7 @@ out - 3 + 0 0 @@ -12535,7 +12594,7 @@ out - 3 + 0 0 @@ -12561,7 +12620,7 @@ out - 63 + 15 0 @@ -12588,7 +12647,7 @@ out - 63 + 15 0 @@ -12615,7 +12674,7 @@ out - 31 + 7 0 @@ -12642,7 +12701,7 @@ out - 31 + 7 0 @@ -12669,7 +12728,7 @@ out - 511 + 127 0 @@ -12695,7 +12754,7 @@ out - 31 + 7 0 @@ -12721,7 +12780,7 @@ out - 7 + 1 0 @@ -12747,7 +12806,7 @@ out - 3 + 0 0 @@ -12773,7 +12832,7 @@ out - 3 + 0 0 @@ -12799,7 +12858,7 @@ out - 23 + 5 0 @@ -12825,7 +12884,7 @@ out - 7 + 1 0 @@ -12932,7 +12991,7 @@ out - 27 + 6 0 @@ -12958,7 +13017,7 @@ out - 3 + 0 0 @@ -12984,7 +13043,7 @@ out - 3 + 0 0 @@ -13010,7 +13069,7 @@ out - 3 + 0 0 @@ -13036,7 +13095,7 @@ out - 3 + 0 0 @@ -13062,7 +13121,7 @@ out - 3 + 0 0 @@ -13089,7 +13148,7 @@ out - 3 + 0 0 @@ -13115,7 +13174,7 @@ out - 3 + 0 0 @@ -13141,7 +13200,7 @@ out - 3 + 0 0 @@ -13167,7 +13226,7 @@ out - 3 + 0 0 @@ -13193,7 +13252,7 @@ out - 3 + 0 0 @@ -13220,7 +13279,7 @@ out - 3 + 0 0 @@ -13246,7 +13305,7 @@ out - 3 + 0 0 @@ -13272,7 +13331,7 @@ out - 3 + 0 0 @@ -13298,7 +13357,7 @@ out - 3 + 0 0 @@ -13324,7 +13383,7 @@ out - 3 + 0 0 @@ -13350,7 +13409,7 @@ out - 3 + 0 0 @@ -13376,7 +13435,7 @@ out - 3 + 0 0 @@ -13402,7 +13461,7 @@ out - 3 + 0 0 @@ -13428,7 +13487,7 @@ out - 3 + 0 0 @@ -13454,7 +13513,7 @@ out - 3 + 0 0 @@ -13480,7 +13539,7 @@ out - 3 + 0 0 @@ -13506,7 +13565,7 @@ out - 3 + 0 0 @@ -13532,7 +13591,7 @@ out - 7 + 1 0 @@ -13558,7 +13617,7 @@ out - 11 + 2 0 @@ -13584,7 +13643,7 @@ out - 3 + 0 0 @@ -13610,7 +13669,7 @@ out - 3 + 0 0 @@ -13636,7 +13695,7 @@ out - 3 + 0 0 @@ -13662,7 +13721,7 @@ out - 7 + 1 0 @@ -13688,7 +13747,7 @@ out - 3 + 0 0 @@ -13741,7 +13800,7 @@ out - 3 + 0 0 @@ -13767,7 +13826,7 @@ out - 3 + 0 0 @@ -13794,7 +13853,7 @@ out - 3 + 0 0 @@ -13820,7 +13879,7 @@ out - 3 + 0 0 @@ -13846,7 +13905,7 @@ out - 3 + 0 0 @@ -13872,7 +13931,7 @@ out - 3 + 0 0 @@ -13898,7 +13957,7 @@ out - 3 + 0 0 @@ -13925,7 +13984,7 @@ out - 3 + 0 0 @@ -13951,7 +14010,7 @@ out - 3 + 0 0 @@ -13977,7 +14036,7 @@ out - 3 + 0 0 @@ -14003,7 +14062,7 @@ out - 3 + 0 0 @@ -14029,7 +14088,7 @@ out - 3 + 0 0 @@ -14055,7 +14114,7 @@ out - 3 + 0 0 @@ -14081,7 +14140,7 @@ out - 3 + 0 0 @@ -14106,7 +14165,7 @@ C_CHANNEL_ENABLE - "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000" + "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000" C_PCIE_ENABLE @@ -14122,7 +14181,7 @@ C_CPLL_VCO_FREQUENCY - 2578.125 + 2000.0 C_FORCE_COMMONS @@ -14214,7 +14273,7 @@ C_RX_CB_MAX_LEVEL - 2 + 1 C_RX_CB_LEN_SEQ @@ -14242,11 +14301,11 @@ C_RX_CC_K - "00100010" + "01010101" C_RX_CC_LEN_SEQ - 2 + 4 C_RX_CC_NUM_SEQ @@ -14258,7 +14317,7 @@ C_RX_CC_VAL - "00000000000000000000001011110000110001010000000000000000000000101111000001010000" + "00010100000010111100000101000000101111000001010000001011110000110001010010111100" C_RX_COMMA_M_ENABLE @@ -14310,7 +14369,7 @@ C_RX_PLL_TYPE - 0 + 2 C_RX_RECCLK_OUTPUT @@ -14366,11 +14425,11 @@ C_TOTAL_NUM_CHANNELS - 4 + 1 C_TOTAL_NUM_COMMONS - 1 + 0 C_TOTAL_NUM_COMMONS_EXAMPLE @@ -14382,7 +14441,7 @@ C_TXPROGDIV_FREQ_SOURCE - 0 + 2 C_TXPROGDIV_FREQ_VAL @@ -14434,7 +14493,7 @@ C_TX_PLL_TYPE - 0 + 2 C_TX_REFCLK_FREQUENCY @@ -14623,6 +14682,33 @@ choice_list_6b979ebc 250 + + choice_list_707d3027 + 80 + 100 + 125 + 133.3333333 + 160 + 166.6666667 + 200 + 250 + 266.6666667 + 320 + 333.3333333 + 400 + 500 + 533.3333333 + 666.6666667 + 800 + + + choice_list_7612b160 + X0Y8 + + + choice_list_822b7946 + CPLL + choice_list_98c4d361 257.8125 @@ -14675,336 +14761,12 @@ 14 15 - - choice_list_c83270be - X0Y11 - X0Y10 - X0Y9 - X0Y8 - - - choice_list_d3562949 - 100 - 100.6289308 - 101.2658228 - 101.910828 - 102.5641026 - 103.2258065 - 103.8961039 - 104.5751634 - 105.2631579 - 105.9602649 - 106.6666667 - 107.3825503 - 108.1081081 - 108.8435374 - 109.5890411 - 110.3448276 - 111.1111111 - 111.8881119 - 112.6760563 - 113.4751773 - 114.2857143 - 115.1079137 - 115.942029 - 116.7883212 - 117.6470588 - 118.5185185 - 119.4029851 - 120.3007519 - 121.2121212 - 122.1374046 - 123.0769231 - 124.0310078 - 125 - 125.984252 - 126.984127 - 128 - 129.0322581 - 130.0813008 - 131.147541 - 132.231405 - 133.3333333 - 134.4537815 - 135.5932203 - 136.7521368 - 137.9310345 - 139.1304348 - 140.3508772 - 141.5929204 - 142.8571429 - 144.1441441 - 145.4545455 - 146.7889908 - 148.1481481 - 149.5327103 - 150.9433962 - 152.3809524 - 153.8461538 - 155.3398058 - 156.8627451 - 158.4158416 - 160 - 161.6161616 - 163.2653061 - 164.9484536 - 166.6666667 - 168.4210526 - 170.212766 - 172.0430108 - 173.9130435 - 175.8241758 - 177.7777778 - 179.7752809 - 181.8181818 - 183.908046 - 186.0465116 - 188.2352941 - 190.4761905 - 192.7710843 - 195.1219512 - 197.5308642 - 200 - 201.2578616 - 202.5316456 - 203.8216561 - 205.1282051 - 206.4516129 - 207.7922078 - 209.1503268 - 210.5263158 - 211.9205298 - 213.3333333 - 214.7651007 - 216.2162162 - 217.6870748 - 219.1780822 - 220.6896552 - 222.2222222 - 223.7762238 - 225.3521127 - 226.9503546 - 228.5714286 - 230.2158273 - 231.884058 - 233.5766423 - 235.2941176 - 237.037037 - 238.8059701 - 240.6015038 - 242.4242424 - 244.2748092 - 246.1538462 - 248.0620155 - 250 - 251.9685039 - 253.968254 - 256 - 258.0645161 - 260.1626016 - 262.295082 - 264.4628099 - 266.6666667 - 268.907563 - 271.1864407 - 273.5042735 - 275.862069 - 278.2608696 - 280.7017544 - 283.1858407 - 285.7142857 - 288.2882883 - 290.9090909 - 293.5779817 - 296.2962963 - 299.0654206 - 300 - 301.8867925 - 303.7974684 - 304.7619048 - 305.7324841 - 307.6923077 - 309.6774194 - 310.6796117 - 311.6883117 - 313.7254902 - 315.7894737 - 316.8316832 - 317.8807947 - 320 - 322.147651 - 323.2323232 - 324.3243243 - 326.5306122 - 328.7671233 - 329.8969072 - 331.0344828 - 333.3333333 - 335.6643357 - 336.8421053 - 338.028169 - 340.4255319 - 342.8571429 - 344.0860215 - 345.323741 - 347.826087 - 350.3649635 - 351.6483516 - 352.9411765 - 355.5555556 - 358.2089552 - 359.5505618 - 360.9022556 - 363.6363636 - 366.4122137 - 367.816092 - 369.2307692 - 372.0930233 - 375 - 376.4705882 - 377.9527559 - 380.952381 - 384 - 385.5421687 - 387.0967742 - 390.2439024 - 393.442623 - 395.0617284 - 396.6942149 - 400 - 402.5157233 - 403.3613445 - 405.0632911 - 406.779661 - 407.6433121 - 410.2564103 - 412.9032258 - 413.7931034 - 415.5844156 - 417.3913043 - 418.3006536 - 421.0526316 - 423.8410596 - 424.7787611 - 426.6666667 - 428.5714286 - 429.5302013 - 432.4324324 - 435.3741497 - 436.3636364 - 438.3561644 - 440.3669725 - 441.3793103 - 444.4444444 - 447.5524476 - 448.5981308 - 450.7042254 - 452.8301887 - 453.9007092 - 457.1428571 - 460.4316547 - 461.5384615 - 463.7681159 - 466.0194175 - 467.1532847 - 470.5882353 - 474.0740741 - 475.2475248 - 477.6119403 - 480 - 481.2030075 - 484.8484848 - 488.5496183 - 489.7959184 - 492.3076923 - 494.8453608 - 496.124031 - 500 - 503.9370079 - 505.2631579 - 507.9365079 - 510.6382979 - 512 - 516.1290323 - 520.3252033 - 521.7391304 - 524.5901639 - 527.4725275 - 528.9256198 - 533.3333333 - 537.8151261 - 539.3258427 - 542.3728814 - 545.4545455 - 547.008547 - 551.7241379 - 556.5217391 - 558.1395349 - 561.4035088 - 564.7058824 - 566.3716814 - 571.4285714 - 576.5765766 - 578.313253 - 581.8181818 - 585.3658537 - 587.1559633 - 592.5925926 - 598.1308411 - 600 - 603.7735849 - 607.5949367 - 609.5238095 - 615.3846154 - 621.3592233 - 623.3766234 - 627.4509804 - 631.5789474 - 633.6633663 - 640 - 646.4646465 - 648.6486486 - 653.0612245 - 657.5342466 - 659.7938144 - 666.6666667 - 673.6842105 - 676.056338 - 680.8510638 - 685.7142857 - 688.172043 - 695.6521739 - 703.2967033 - 705.8823529 - 711.1111111 - 716.4179104 - 719.1011236 - 727.2727273 - 735.6321839 - 738.4615385 - 744.1860465 - 750 - 752.9411765 - 761.9047619 - 771.0843373 - 774.1935484 - 780.4878049 - 786.8852459 - 790.1234568 - 800 - 810.1265823 - 813.559322 - choice_list_e6469819 1 2 4 - - choice_list_ed5e3eb0 - QPLL0 - choice_pairs_03018cc1 1 @@ -15221,24 +14983,38 @@ CHANNEL_ENABLE Enable channel Indicate whether this transceiver channel is instantiated and enabled for use - X0Y11 X0Y10 X0Y9 X0Y8 + X0Y8 TX_MASTER_CHANNEL Master TX channel Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 + X0Y8 + + + + false + + + RX_MASTER_CHANNEL Master RX channel Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 + X0Y8 + + + + false + + + INTERNAL_TOTAL_NUM_CHANNELS Total number of channels - 4 + 1 @@ -15250,7 +15026,7 @@ INTERNAL_TOTAL_NUM_COMMONS Total number of commons required - 1 + 0 @@ -15264,11 +15040,18 @@ Include transceiver COMMON in the If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. CORE + + + + false + + + INTERNAL_NUM_COMMONS_CORE Number of commons in core - 1 + 0 @@ -15360,13 +15143,13 @@ TX_PLL_TYPE PLL type Select the transmitter PLL type - QPLL0 + CPLL TX_REFCLK_FREQUENCY Actual Reference clock (MHz) Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type - 100 + 100 TX_DATA_ENCODING @@ -15427,13 +15210,13 @@ RX_PLL_TYPE PLL type Select the receiver PLL type - QPLL0 + CPLL RX_REFCLK_FREQUENCY Actual Reference clock (MHz) Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type - 100 + 100 RX_DATA_DECODING @@ -15476,7 +15259,7 @@ RX_EQ_MODE Equalization mode Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. - AUTO + LPM RX_JTOL_FC @@ -15642,6 +15425,13 @@ Enable and select number of sequences to use Select whether to enable channel bonding, and how many sequences to use if enabled 0 + + + + false + + + RX_CB_LEN_SEQ @@ -15673,7 +15463,7 @@ RX_CB_MAX_LEVEL Maximum channel bonding level to be used Select the maximum channel bonding level that will be used in the system channel bonding topology - 2 + 1 @@ -16152,7 +15942,7 @@ RX_CC_LEN_SEQ Length of each sequence Select the number of characters in each channel clock correction sequence - 2 + 4 RX_CC_PERIODICITY @@ -16200,11 +15990,11 @@ RX_CC_VAL - 00000000000000000000001011110000110001010000000000000000000000101111000001010000 + 00010100000010111100000101000000101111000001010000001011110000110001010010111100 RX_CC_K - 00100010 + 01010101 @@ -16234,13 +16024,13 @@ RX_CC_VAL_0_0 Value Specify the value for this clock correction sequence and pattern - 01010000 + 10111100 RX_CC_K_0_0 K character Indicate whether or not the corresponding clock correction value is a K character - false + true RX_CC_DISP_0_0 @@ -16258,13 +16048,13 @@ RX_CC_VAL_0_1 Value Specify the value for this clock correction sequence and pattern - 10111100 + 11000101 RX_CC_K_0_1 K character Indicate whether or not the corresponding clock correction value is a K character - true + false RX_CC_DISP_0_1 @@ -16277,104 +16067,48 @@ Don't care Mark this pattern "don't care" to always consider it as a match within a clock correction sequence false - - - - false - - - RX_CC_VAL_0_2 Value Specify the value for this clock correction sequence and pattern - 00000000 - - - - false - - - + 10111100 RX_CC_K_0_2 K character Indicate whether or not the corresponding clock correction value is a K character - false - - - - false - - - + true RX_CC_DISP_0_2 Inverted disparity Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error false - - - - false - - - RX_CC_MASK_0_3 Don't care Mark this pattern "don't care" to always consider it as a match within a clock correction sequence false - - - - false - - - RX_CC_VAL_0_3 Value Specify the value for this clock correction sequence and pattern - 00000000 - - - - false - - - + 01010000 RX_CC_K_0_3 K character Indicate whether or not the corresponding clock correction value is a K character false - - - - false - - - RX_CC_DISP_0_3 Inverted disparity Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error false - - - - false - - - RX_CC_MASK_1_0 @@ -16386,13 +16120,13 @@ RX_CC_VAL_1_0 Value Specify the value for this clock correction sequence and pattern - 11000101 + 10111100 RX_CC_K_1_0 K character Indicate whether or not the corresponding clock correction value is a K character - false + true RX_CC_DISP_1_0 @@ -16410,13 +16144,13 @@ RX_CC_VAL_1_1 Value Specify the value for this clock correction sequence and pattern - 10111100 + 01010000 RX_CC_K_1_1 K character Indicate whether or not the corresponding clock correction value is a K character - true + false RX_CC_DISP_1_1 @@ -16429,104 +16163,48 @@ Don't care Mark this pattern "don't care" to always consider it as a match within a clock correction sequence false - - - - false - - - RX_CC_VAL_1_2 Value Specify the value for this clock correction sequence and pattern - 00000000 - - - - false - - - + 10111100 RX_CC_K_1_2 K character Indicate whether or not the corresponding clock correction value is a K character - false - - - - false - - - + true RX_CC_DISP_1_2 Inverted disparity Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error false - - - - false - - - RX_CC_MASK_1_3 Don't care Mark this pattern "don't care" to always consider it as a match within a clock correction sequence false - - - - false - - - RX_CC_VAL_1_3 Value Specify the value for this clock correction sequence and pattern - 00000000 - - - - false - - - + 01010000 RX_CC_K_1_3 K character Indicate whether or not the corresponding clock correction value is a K character false - - - - false - - - RX_CC_DISP_1_3 Inverted disparity Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error false - - - - false - - - ENABLE_OPTIONAL_PORTS @@ -16613,6 +16291,13 @@ In the example design, organize ports across multiple channels by If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) NAME + + + + false + + + PRESET @@ -16638,7 +16323,7 @@ INTERNAL_PORT_ENABLEMENT_UPDATED - 17 + 18 @@ -16649,7 +16334,7 @@ INTERNAL_CHANNEL_SITES_UPDATED - 3 + 5 @@ -16696,6 +16381,13 @@ Enable secondary QPLL Enable and configure the QPLL which is not used in this core configuration false + + + + false + + + SECONDARY_QPLL_LINE_RATE @@ -16753,7 +16445,7 @@ TXPROGDIV_FREQ_SOURCE Programmable divider clock source Select which PLL source is used to generate the selectable TXOUTCLK frequency - QPLL0 + CPLL @@ -16785,7 +16477,7 @@ FREERUN_FREQUENCY Free-running and DRP clock frequency (MHz) Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface - 100 + 100 INCLUDE_CPLL_CAL @@ -17325,7 +17017,7 @@ INTERNAL_PORT_ENABLED_BGBYPASSB_IN - 0 + -1 @@ -17336,7 +17028,7 @@ INTERNAL_PORT_ENABLED_BGMONITORENB_IN - 0 + -1 @@ -17347,7 +17039,7 @@ INTERNAL_PORT_ENABLED_BGPDB_IN - 0 + -1 @@ -17358,7 +17050,7 @@ INTERNAL_PORT_ENABLED_BGRCALOVRD_IN - 0 + -1 @@ -17369,7 +17061,7 @@ INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN - 0 + -1 @@ -17380,7 +17072,7 @@ INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN - 0 + -1 @@ -17391,7 +17083,7 @@ INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN - 0 + -1 @@ -17402,7 +17094,7 @@ INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN - 0 + -1 @@ -17413,7 +17105,7 @@ INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN - 0 + -1 @@ -17424,7 +17116,7 @@ INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN - 0 + -1 @@ -17435,7 +17127,7 @@ INTERNAL_PORT_ENABLED_GTGREFCLK0_IN - 0 + -1 @@ -17446,7 +17138,7 @@ INTERNAL_PORT_ENABLED_GTGREFCLK1_IN - 0 + -1 @@ -17457,7 +17149,7 @@ INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN - 0 + -1 @@ -17468,7 +17160,7 @@ INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN - 0 + -1 @@ -17479,7 +17171,7 @@ INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN - 0 + -1 @@ -17490,7 +17182,7 @@ INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN - 0 + -1 @@ -17501,7 +17193,7 @@ INTERNAL_PORT_ENABLED_GTREFCLK00_IN - 1 + -1 @@ -17512,7 +17204,7 @@ INTERNAL_PORT_ENABLED_GTREFCLK01_IN - 0 + -1 @@ -17523,7 +17215,7 @@ INTERNAL_PORT_ENABLED_GTREFCLK10_IN - 0 + -1 @@ -17534,7 +17226,7 @@ INTERNAL_PORT_ENABLED_GTREFCLK11_IN - 0 + -1 @@ -17545,7 +17237,7 @@ INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN - 0 + -1 @@ -17556,7 +17248,7 @@ INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN - 0 + -1 @@ -17567,7 +17259,7 @@ INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN - 0 + -1 @@ -17578,7 +17270,7 @@ INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN - 0 + -1 @@ -17611,7 +17303,7 @@ INTERNAL_PORT_ENABLED_PMARSVD0_IN - 0 + -1 @@ -17622,7 +17314,7 @@ INTERNAL_PORT_ENABLED_PMARSVD1_IN - 0 + -1 @@ -17633,7 +17325,7 @@ INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN - 0 + -1 @@ -17644,7 +17336,7 @@ INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN - 0 + -1 @@ -17666,7 +17358,7 @@ INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN - 0 + -1 @@ -17677,7 +17369,7 @@ INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN - 0 + -1 @@ -17688,7 +17380,7 @@ INTERNAL_PORT_ENABLED_QPLL0PD_IN - 0 + -1 @@ -17699,7 +17391,7 @@ INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN - 0 + -1 @@ -17721,7 +17413,7 @@ INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN - 0 + -1 @@ -17732,7 +17424,7 @@ INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN - 0 + -1 @@ -17754,7 +17446,7 @@ INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN - 0 + -1 @@ -17765,7 +17457,7 @@ INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN - 0 + -1 @@ -17776,7 +17468,7 @@ INTERNAL_PORT_ENABLED_QPLL1PD_IN - 0 + -1 @@ -17787,7 +17479,7 @@ INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN - 0 + -1 @@ -17798,7 +17490,7 @@ INTERNAL_PORT_ENABLED_QPLL1RESET_IN - 0 + -1 @@ -17809,7 +17501,7 @@ INTERNAL_PORT_ENABLED_QPLLRSVD1_IN - 0 + -1 @@ -17820,7 +17512,7 @@ INTERNAL_PORT_ENABLED_QPLLRSVD2_IN - 0 + -1 @@ -17831,7 +17523,7 @@ INTERNAL_PORT_ENABLED_QPLLRSVD3_IN - 0 + -1 @@ -17842,7 +17534,7 @@ INTERNAL_PORT_ENABLED_QPLLRSVD4_IN - 0 + -1 @@ -17853,7 +17545,7 @@ INTERNAL_PORT_ENABLED_RCALENB_IN - 0 + -1 @@ -18172,7 +17864,7 @@ INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT - 0 + -1 @@ -18183,7 +17875,7 @@ INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT - 0 + -1 @@ -18194,7 +17886,7 @@ INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT - 0 + -1 @@ -18205,7 +17897,7 @@ INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT - 0 + -1 @@ -18216,7 +17908,7 @@ INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT - 0 + -1 @@ -18227,7 +17919,7 @@ INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT - 0 + -1 @@ -18238,7 +17930,7 @@ INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT - 1 + -1 @@ -18249,7 +17941,7 @@ INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT - 1 + -1 @@ -18260,7 +17952,7 @@ INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT - 0 + -1 @@ -18271,7 +17963,7 @@ INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT - 0 + -1 @@ -18282,7 +17974,7 @@ INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT - 0 + -1 @@ -18293,7 +17985,7 @@ INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT - 0 + -1 @@ -18304,7 +17996,7 @@ INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT - 0 + -1 @@ -18315,7 +18007,7 @@ INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT - 0 + -1 @@ -18326,7 +18018,7 @@ INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT - 0 + -1 @@ -18337,7 +18029,7 @@ INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT - 0 + -1 @@ -18348,7 +18040,7 @@ INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT - 0 + -1 @@ -18359,7 +18051,7 @@ INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT - 0 + -1 @@ -18370,7 +18062,7 @@ INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT - 0 + -1 @@ -18381,7 +18073,7 @@ INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT - 0 + -1 @@ -18656,7 +18348,7 @@ INTERNAL_PORT_ENABLED_CPLLPD_IN - 0 + -1 @@ -18964,7 +18656,7 @@ INTERNAL_PORT_ENABLED_GTREFCLK0_IN - 0 + 1 @@ -19228,7 +18920,7 @@ INTERNAL_PORT_ENABLED_QPLL0CLK_IN - -1 + 0 @@ -19250,7 +18942,7 @@ INTERNAL_PORT_ENABLED_QPLL0REFCLK_IN - -1 + 0 @@ -19261,7 +18953,7 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GTH-DisplayPort_1_62G + GTH-DisplayPort_2_7G + GTH-DisplayPort_5_4G + GTH-Gigabit_Ethernet + GTH-HDMI + GTH-HD_SDI + GTH-HMC_12_5G + GTH-Interlaken_10G + GTH-Interlaken_12_5G + GTH-Interlaken_6_25G + GTH-JESD204 + GTH-JESD204_3_125G + GTH-JESD204_6_375G + GTH-OTL4_10 + GTH-OTU2 + GTH-OTU2e + GTH-QSGMII + GTH-RXAUI + GTH-SATA + GTH-SRIO_Gen2 + GTH-XAUI + GTH-XLAUI + + + choice_pairs_40d02874 + 10GBASE_KR + CUSTOM + PCIE_GEN1_GEN2 + PCIE_GEN3 + QPI + + + choice_pairs_4e550952 + NONE + EXAMPLE_DESIGN + + + choice_pairs_7b0c3758 + RX + BOTH + TX + + + choice_pairs_85f99b7f + K28.1 + K28.5 + NONE + + + choice_pairs_8846c8f0 + RAW + 8B10B + 64B66B + 64B66B_CAUI + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_88c85933 + 8B10B + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + RAW + 64B66B + 64B66B_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_93c2d4ee + CORE + EXAMPLE_DESIGN + + + choice_pairs_9c19f015 + 1 + 2 + + + choice_pairs_a537ddda + 0 + 1 + + + choice_pairs_aa541099 + AUTO + DFE + LPM + + + choice_pairs_ae574462 + OFF + PCS + PMA + AUTO + + + choice_pairs_b0974ef0 + 1 + 2 + 0 + + + choice_pairs_d4feb97d + DISABLE + ENABLE + + + choice_pairs_f05b8192 + CHANNEL + NAME + + + The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. + + + GT_TYPE + Transceiver type + For devices which contain more than one serial transceiver type, select the type of transceiver to configure + GTH + + + INTERNAL_GT_PRIM_TYPE + gthe3 + + + + false + + + + + + GT_REV + Transceiver revision + Select the serial transceiver silicon revision + 0 + + + GT_DIRECTION + Transmit and/or Receive direction + Enable transmit and/or receive + BOTH + + + RX_ENABLE + Enabled + Enable the receiver for use + true + + + + false + + + + + + TX_ENABLE + Enabled + Enable the transmitter for use + true + + + + false + + + + + + CHANNEL_ENABLE + Enable channel + Indicate whether this transceiver channel is instantiated and enabled for use + X0Y8 + + + TX_MASTER_CHANNEL + Master TX channel + Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) + X0Y8 + + + + false + + + + + + RX_MASTER_CHANNEL + Master RX channel + Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) + X0Y8 + + + + false + + + + + + INTERNAL_TOTAL_NUM_CHANNELS + Total number of channels + 1 + + + + false + + + + + + INTERNAL_TOTAL_NUM_COMMONS + Total number of commons required + 0 + + + + false + + + + + + LOCATE_COMMON + Include transceiver COMMON in the + If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. + CORE + + + + false + + + + + + INTERNAL_NUM_COMMONS_CORE + Number of commons in core + 0 + + + + false + + + + + + INTERNAL_NUM_COMMONS_EXAMPLE + Number of commons in example + 0 + + + + false + + + + + + INTERNAL_TX_USRCLK_FREQUENCY + 100.0000000 + + + + false + + + + + + INTERNAL_RX_USRCLK_FREQUENCY + 100.0000000 + + + + false + + + + + + RX_PPM_OFFSET + PPM offset between receiver and transmitter + Specify the PPM offset between received data and transmitted data + 0 + + + OOB_ENABLE + Enable Out of Band signaling (OOB)/Electrical Idle + Enable or disable Out of Band signaling (OOB)/Electrical Idle + false + + + + false + + + + + + RX_SSC_PPM + Spread spectrum clocking + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Insertion loss at Nyquist (dB) + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 20 + + + PCIE_CORECLK_FREQ + 250 + + + PCIE_USERCLK_FREQ + 250 + + + TX_LINE_RATE + Line rate (Gb/s) + Enter the transmitter line rate in Gb/s + 2 + + + TX_PLL_TYPE + PLL type + Select the transmitter PLL type + CPLL + + + TX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type + 200 + + + TX_DATA_ENCODING + Encoding + Select the encoding format for data transmission, or choose 'Raw' for no data encoding + 8B10B + + + TX_USER_DATA_WIDTH + User data width + Select the width at which the user logic will provide parallel data to the serial transceiver for transmission + 16 + + + TX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal transmitter data path + 20 + + + TX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the transmitter buffer + 1 + + + TX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection + 0 + + + + false + + + + + + TX_OUTCLK_SOURCE + TXOUTCLK source + Select the source of TXOUTCLK + TXOUTCLKPMA + + + TX_DIFF_SWING_EMPH_MODE + Differential swing and emphasis mode + Select the transmitter differential swing and emphasis mode for your application + CUSTOM + + + RX_LINE_RATE + Line rate (Gb/s) + Enter the receiver line rate in Gb/s + 2 + + + RX_PLL_TYPE + PLL type + Select the receiver PLL type + CPLL + + + RX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type + 200 + + + RX_DATA_DECODING + Decoding + Select the decoding format for data reception, or choose 'Raw' for no data decoding + 8B10B + + + RX_USER_DATA_WIDTH + User data width + Select the width at which the serial transceiver will provide received parallel data to the user logic + 16 + + + RX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal receiver data path + 20 + + + RX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the receiver elastic buffer + 1 + + + RX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection + 0 + + + + false + + + + + + RX_EQ_MODE + Equalization mode + Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. + LPM + + + RX_JTOL_FC + Mask corner frequency (MHz) + Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. + 1.19976 + + + RX_JTOL_LF_SLOPE + Mask low frequency slope (dB/decade) + Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. + -20 + + + RX_OUTCLK_SOURCE + RXOUTCLK source + Select the source of RXOUTCLK + RXOUTCLKPMA + + + SIM_CPLL_CAL_BYPASS + 1 + + + PCIE_ENABLE + false + + + RX_TERMINATION + Termination + Select the receiver termination + PROGRAMMABLE + + + RX_TERMINATION_PROG_VALUE + Programmable termination voltage (mV) + Select the termination voltage (in mV) when in programmable mode + 800 + + + RX_COUPLING + Link coupling + Select the link coupling + AC + + + RX_BUFFER_BYPASS_MODE + Receiver elastic buffer bypass mode + Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode + MULTI + + + + false + + + + + + RX_BUFFER_RESET_ON_CB_CHANGE + Reset receiver elastic buffer on channel bonding change + Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL + ENABLE + + + + false + + + + + + RX_BUFFER_RESET_ON_COMMAALIGN + Reset receiver elastic buffer on comma alignment + Control whether the receiver elastic buffer is reset on comma alignment + DISABLE + + + RX_BUFFER_RESET_ON_RATE_CHANGE + Reset receiver elastic buffer on rate change + Control whether the receiver elastic buffer is reset on rate change + ENABLE + + + TX_BUFFER_RESET_ON_RATE_CHANGE + Reset transmitter buffer on rate change + Control whether the transmitter buffer is reset on rate change + ENABLE + + + RESET_SEQUENCE_INTERVAL + Reset sequence time interval (ns) + Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval + 0 + + + RX_COMMA_PRESET + Comma value preset + K28.5 + + + RX_COMMA_VALID_ONLY + Valid comma values for 8B/10B decoding + Select the range of comma characters decoded by the 8B/10B decoder + 0 + + + RX_COMMA_P_ENABLE + Detect plus comma + Indicate whether or not the specified bit pattern is detected as a plus comma + true + + + RX_COMMA_M_ENABLE + Detect minus comma + Indicate whether or not the specified bit pattern is detected as a minus comma + true + + + RX_COMMA_DOUBLE_ENABLE + Detect combined plus/minus (double-length) comma + Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence + false + + + RX_COMMA_P_VAL + Plus comma value + Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received + 0101111100 + + + RX_COMMA_M_VAL + Minus comma value + Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received + 1010000011 + + + RX_COMMA_MASK + Mask + Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" + 1111111111 + + + RX_COMMA_ALIGN_WORD + Alignment boundary + Select which data byte boundaries are allowed for comma alignment + 2 + + + RX_COMMA_SHOW_REALIGN_ENABLE + Show realign comma + Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency + true + + + RX_SLIDE_MODE + Manual alignment (RXSLIDE) mode + Select whether to enable manual alignment, and in what mode if enabled + OFF + + + RX_CB_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable channel bonding, and how many sequences to use if enabled + 0 + + + + false + + + + + + RX_CB_LEN_SEQ + Length of each sequence + Select the number of characters in each channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_SKEW + Sequence maximum skew + Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_LEVEL + Maximum channel bonding level to be used + Select the maximum channel bonding level that will be used in the system channel bonding topology + 1 + + + + false + + + + + + RX_CB_MASK + 00000000 + + + + false + + + + + + RX_CB_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + + + + false + + + + + + RX_CB_K + 00000000 + + + + false + + + + + + RX_CB_DISP + 00000000 + + + + false + + + + + + RX_CB_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable clock correction, and how many sequences to use if enabled + 2 + + + RX_CC_LEN_SEQ + Length of each sequence + Select the number of characters in each channel clock correction sequence + 4 + + + RX_CC_PERIODICITY + Periodicity of the sequence (in bytes) + Specify the separation between clock correction sequences, in bytes + 5000 + + + RX_CC_KEEP_IDLE + Keep idle + Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received + ENABLE + + + RX_CC_PRECEDENCE + Precedence + Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time + ENABLE + + + + false + + + + + + RX_CC_REPEAT_WAIT + Minimum repetition + Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction + 0 + + + RX_CC_MASK + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + 00000000 + + + + false + + + + + + RX_CC_VAL + 00010100000010111100000101000000101111000001010000001011110000110001010010111100 + + + RX_CC_K + 01010101 + + + + false + + + + + + RX_CC_DISP + 00000000 + + + + false + + + + + + RX_CC_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_0 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_0_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_1 + Value + Specify the value for this clock correction sequence and pattern + 11000101 + + + RX_CC_K_0_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_2 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_0_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_3 + Value + Specify the value for this clock correction sequence and pattern + 01010000 + + + RX_CC_K_0_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_0 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_1_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_1 + Value + Specify the value for this clock correction sequence and pattern + 01010000 + + + RX_CC_K_1_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_2 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_1_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_3 + Value + Specify the value for this clock correction sequence and pattern + 01010000 + + + RX_CC_K_1_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + ENABLE_OPTIONAL_PORTS + Enable optional ports + Indicate whether a port should be included + rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpmareset_in rxresetdone_out txresetdone_out + + + RX_REFCLK_SOURCE + Receiver reference clock source + Select a reference clock input to drive the PLL chosen for receiver operation + + + + TX_REFCLK_SOURCE + Transmitter reference clock source + Select a reference clock input to drive the PLL chosen for transmitter operation + + + + RX_RECCLK_OUTPUT + Drive recovered clock out of device + Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use + + + + LOCATE_RESET_CONTROLLER + Include reset controller in the + Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + LOCATE_TX_BUFFER_BYPASS_CONTROLLER + Include transmitter buffer bypass controller in the + If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_RX_BUFFER_BYPASS_CONTROLLER + Include receiver elastic buffer bypass controller in the + If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_IN_SYSTEM_IBERT_CORE + Include In-System IBERT core + Indicate whether or not the In-System IBERT core should be instantiated in the example design. + EXAMPLE_DESIGN + + + LOCATE_TX_USER_CLOCKING + Include simple transmitter user clocking network in the + Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_RX_USER_CLOCKING + Include simple receiver user clocking network in the + Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_USER_DATA_WIDTH_SIZING + Include user data width sizing in the + Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + ORGANIZE_PORTS_BY + In the example design, organize ports across multiple channels by + If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) + NAME + + + + false + + + + + + PRESET + Transceiver configuration preset + You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard + None + + + INTERNAL_PRESET + Transceiver configuration preset + None + + + INTERNAL_PORT_USAGE_UPDATED + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLEMENT_UPDATED + 20 + + + + false + + + + + + INTERNAL_CHANNEL_SITES_UPDATED + 5 + + + + false + + + + + + INTERNAL_CHANNEL_COLUMN_LOC_MAX + 96 + + + + false + + + + + + INTERNAL_RX_COMMA_PRESET_UPDATE + 8 + + + + false + + + + + + INTERNAL_UPDATE_IP_SYMBOL_drpclk_in + true + + + + false + + + + + + SECONDARY_QPLL_ENABLE + Enable secondary QPLL + Enable and configure the QPLL which is not used in this core configuration + false + + + + false + + + + + + SECONDARY_QPLL_LINE_RATE + Line rate of second core (Gb/s) + Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL + 10.3125 + + + + false + + + + + + SECONDARY_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection + 0 + + + + false + + + + + + SECONDARY_QPLL_REFCLK_FREQUENCY + Actual Reference clock frequency (MHz) + Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate + 257.8125 + + + + false + + + + + + TXPROGDIV_FREQ_ENABLE + Enable selectable TXOUTCLK frequency + Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency + false + + + + false + + + + + + TXPROGDIV_FREQ_SOURCE + Programmable divider clock source + Select which PLL source is used to generate the selectable TXOUTCLK frequency + CPLL + + + + false + + + + + + TXPROGDIV_FREQ_VAL + TXOUTCLK frequency (MHz) + Select the TXOUTCLK frequency to be generated by the TX programmable divider + 100 + + + + false + + + + + + SATA_TX_BURST_LEN + TX COM sequence burst length + Select the number of bursts that make up a SATA COM sequence + 15 + + + FREERUN_FREQUENCY + Free-running and DRP clock frequency (MHz) + Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface + 100 + + + INCLUDE_CPLL_CAL + 2 + + + USER_GTPOWERGOOD_DELAY_EN + Select 1 to enable powergood delay circuit + 1 + + + DISABLE_LOC_XDC + Select to disable generation of LOC constraints in xdc + 0 + + + ENABLE_COMMON_USRCLK + 0 + + + USB_ENABLE + false + + + PCIE_64BIT + false + + + PCIE_GEN4_EIOS + false + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGBYPASSB_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGMONITORENB_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGPDB_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK00_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK01_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK10_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK11_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0PD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1PD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD2_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD3_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD4_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RCALENB_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0DATA_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0WIDTH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1DATA_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1RESET_IN + -1 + + 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+ + INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMREGEN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTDI_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT + -1 + + + + false + + + + + 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INTERNAL_PORT_ENABLED_DRPDI_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANMODE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANRESET_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN + 0 + + + + false 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C_TX_USRCLK_FREQUENCY + 120.0000000 + + + C_TX_USRCLK2_FREQUENCY + 120.0000000 + + + + + + choice_list_00d9575a + 16 + 32 + 64 + + + choice_list_04c1b6c3 + RXOUTCLKPMA + RXOUTCLKPCS + RXPLLREFCLK_DIV1 + RXPROGDIVCLK + + + choice_list_0fbde0c1 + 20 + + + choice_list_13717074 + -20 + -40 + + + choice_list_24871ac1 + AC + DC + + + choice_list_39947cc7 + TXOUTCLKPMA + TXOUTCLKPCS + TXPLLREFCLK_DIV1 + TXPROGDIVCLK + + + choice_list_556e59ba + 0 + 100 + 200 + 300 + 400 + 500 + 600 + 700 + 800 + 900 + 1000 + 1100 + 1200 + 1300 + 1400 + 1500 + 1600 + 1700 + 1800 + 1900 + 2000 + 2100 + 2200 + 2300 + 2400 + 2500 + 2600 + 2700 + 2800 + 2900 + 3000 + 3100 + 3200 + 3300 + 3400 + 3500 + 3600 + 3700 + 3800 + 3900 + 4000 + 4100 + 4200 + 4300 + 4400 + 4500 + 4600 + 4700 + 4800 + 4900 + 5000 + 5100 + 5200 + 5300 + 5400 + 5500 + 5600 + 5700 + 5800 + 5900 + 6000 + 6100 + 6200 + 6300 + 6400 + 6500 + 6600 + 6700 + 6800 + 6900 + 7000 + 7100 + 7200 + 7300 + 7400 + 7500 + 7600 + 7700 + 7800 + 7900 + 8000 + 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choice_pairs_1ebf969f + None + GTH-10GBASE-KR + GTH-10GBASE-R + GTH-12G_SDI + GTH-1G_10G_25G_switchable + GTH-3G_SDI + GTH-Aurora_64B66B + GTH-Aurora_8B10B + GTH-Bandwidth_Engine + GTH-CAUI_10 + GTH-CEI_11G_SR + GTH-CPRI_10G + GTH-CPRI_10_1G + GTH-CPRI_3G + GTH-CPRI_6G + GTH-DisplayPort_1_62G + GTH-DisplayPort_2_7G + GTH-DisplayPort_5_4G + GTH-Gigabit_Ethernet + GTH-HDMI + GTH-HD_SDI + GTH-HMC_12_5G + GTH-Interlaken_10G + GTH-Interlaken_12_5G + GTH-Interlaken_6_25G + GTH-JESD204 + GTH-JESD204_3_125G + GTH-JESD204_6_375G + GTH-OTL4_10 + GTH-OTU2 + GTH-OTU2e + GTH-QSGMII + GTH-RXAUI + GTH-SATA + GTH-SRIO_Gen2 + GTH-XAUI + GTH-XLAUI + + + choice_pairs_40d02874 + 10GBASE_KR + CUSTOM + PCIE_GEN1_GEN2 + PCIE_GEN3 + QPI + + + choice_pairs_4e550952 + NONE + EXAMPLE_DESIGN + + + choice_pairs_7b0c3758 + RX + BOTH + TX + + + choice_pairs_85f99b7f + K28.1 + K28.5 + NONE + + + choice_pairs_8846c8f0 + RAW + 8B10B + 64B66B + 64B66B_CAUI + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_88c85933 + 8B10B + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + RAW + 64B66B + 64B66B_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_93c2d4ee + CORE + EXAMPLE_DESIGN + + + choice_pairs_9c19f015 + 1 + 2 + + + choice_pairs_a537ddda + 0 + 1 + + + choice_pairs_aa541099 + AUTO + DFE + LPM + + + choice_pairs_ae574462 + OFF + PCS + PMA + AUTO + + + choice_pairs_b0974ef0 + 1 + 2 + 0 + + + choice_pairs_d4feb97d + DISABLE + ENABLE + + + choice_pairs_f05b8192 + CHANNEL + NAME + + + The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. + + + GT_TYPE + Transceiver type + For devices which contain more than one serial transceiver type, select the type of transceiver to configure + GTH + + + INTERNAL_GT_PRIM_TYPE + gthe3 + + + + false + + + + + + GT_REV + Transceiver revision + Select the serial transceiver silicon revision + 0 + + + GT_DIRECTION + Transmit and/or Receive direction + Enable transmit and/or receive + BOTH + + + RX_ENABLE + Enabled + Enable the receiver for use + true + + + + false + + + + + + TX_ENABLE + Enabled + Enable the transmitter for use + true + + + + false + + + + + + CHANNEL_ENABLE + Enable channel + Indicate whether this transceiver channel is instantiated and enabled for use + X0Y8 + + + TX_MASTER_CHANNEL + Master TX channel + Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) + X0Y8 + + + + false + + + + + + RX_MASTER_CHANNEL + Master RX channel + Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) + X0Y8 + + + + false + + + + + + INTERNAL_TOTAL_NUM_CHANNELS + Total number of channels + 1 + + + + false + + + + + + INTERNAL_TOTAL_NUM_COMMONS + Total number of commons required + 0 + + + + false + + + + + + LOCATE_COMMON + Include transceiver COMMON in the + If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. + CORE + + + + false + + + + + + INTERNAL_NUM_COMMONS_CORE + Number of commons in core + 0 + + + + false + + + + + + INTERNAL_NUM_COMMONS_EXAMPLE + Number of commons in example + 0 + + + + false + + + + + + INTERNAL_TX_USRCLK_FREQUENCY + 120.0000000 + + + + false + + + + + + INTERNAL_RX_USRCLK_FREQUENCY + 120.0000000 + + + + false + + + + + + RX_PPM_OFFSET + PPM offset between receiver and transmitter + Specify the PPM offset between received data and transmitted data + 0 + + + OOB_ENABLE + Enable Out of Band signaling (OOB)/Electrical Idle + Enable or disable Out of Band signaling (OOB)/Electrical Idle + false + + + + false + + + + + + RX_SSC_PPM + Spread spectrum clocking + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Insertion loss at Nyquist (dB) + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 20 + + + PCIE_CORECLK_FREQ + 250 + + + PCIE_USERCLK_FREQ + 250 + + + TX_LINE_RATE + Line rate (Gb/s) + Enter the transmitter line rate in Gb/s + 2.4 + + + TX_PLL_TYPE + PLL type + Select the transmitter PLL type + CPLL + + + TX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type + 120 + + + TX_DATA_ENCODING + Encoding + Select the encoding format for data transmission, or choose 'Raw' for no data encoding + 8B10B + + + TX_USER_DATA_WIDTH + User data width + Select the width at which the user logic will provide parallel data to the serial transceiver for transmission + 16 + + + TX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal transmitter data path + 20 + + + TX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the transmitter buffer + 1 + + + TX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection + 0 + + + + false + + + + + + TX_OUTCLK_SOURCE + TXOUTCLK source + Select the source of TXOUTCLK + TXOUTCLKPMA + + + TX_DIFF_SWING_EMPH_MODE + Differential swing and emphasis mode + Select the transmitter differential swing and emphasis mode for your application + CUSTOM + + + RX_LINE_RATE + Line rate (Gb/s) + Enter the receiver line rate in Gb/s + 2.4 + + + RX_PLL_TYPE + PLL type + Select the receiver PLL type + CPLL + + + RX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type + 120 + + + RX_DATA_DECODING + Decoding + Select the decoding format for data reception, or choose 'Raw' for no data decoding + 8B10B + + + RX_USER_DATA_WIDTH + User data width + Select the width at which the serial transceiver will provide received parallel data to the user logic + 16 + + + RX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal receiver data path + 20 + + + RX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the receiver elastic buffer + 1 + + + RX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection + 0 + + + + false + + + + + + RX_EQ_MODE + Equalization mode + Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. + LPM + + + RX_JTOL_FC + Mask corner frequency (MHz) + Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. + 1.4397121 + + + RX_JTOL_LF_SLOPE + Mask low frequency slope (dB/decade) + Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. + -20 + + + RX_OUTCLK_SOURCE + RXOUTCLK source + Select the source of RXOUTCLK + RXOUTCLKPMA + + + SIM_CPLL_CAL_BYPASS + 1 + + + PCIE_ENABLE + false + + + RX_TERMINATION + Termination + Select the receiver termination + PROGRAMMABLE + + + RX_TERMINATION_PROG_VALUE + Programmable termination voltage (mV) + Select the termination voltage (in mV) when in programmable mode + 800 + + + RX_COUPLING + Link coupling + Select the link coupling + AC + + + RX_BUFFER_BYPASS_MODE + Receiver elastic buffer bypass mode + Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode + MULTI + + + + false + + + + + + RX_BUFFER_RESET_ON_CB_CHANGE + Reset receiver elastic buffer on channel bonding change + Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL + ENABLE + + + + false + + + + + + RX_BUFFER_RESET_ON_COMMAALIGN + Reset receiver elastic buffer on comma alignment + Control whether the receiver elastic buffer is reset on comma alignment + DISABLE + + + RX_BUFFER_RESET_ON_RATE_CHANGE + Reset receiver elastic buffer on rate change + Control whether the receiver elastic buffer is reset on rate change + ENABLE + + + TX_BUFFER_RESET_ON_RATE_CHANGE + Reset transmitter buffer on rate change + Control whether the transmitter buffer is reset on rate change + ENABLE + + + RESET_SEQUENCE_INTERVAL + Reset sequence time interval (ns) + Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval + 0 + + + RX_COMMA_PRESET + Comma value preset + K28.5 + + + RX_COMMA_VALID_ONLY + Valid comma values for 8B/10B decoding + Select the range of comma characters decoded by the 8B/10B decoder + 0 + + + RX_COMMA_P_ENABLE + Detect plus comma + Indicate whether or not the specified bit pattern is detected as a plus comma + true + + + RX_COMMA_M_ENABLE + Detect minus comma + Indicate whether or not the specified bit pattern is detected as a minus comma + true + + + RX_COMMA_DOUBLE_ENABLE + Detect combined plus/minus (double-length) comma + Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence + false + + + RX_COMMA_P_VAL + Plus comma value + Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received + 0101111100 + + + RX_COMMA_M_VAL + Minus comma value + Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received + 1010000011 + + + RX_COMMA_MASK + Mask + Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" + 1111111111 + + + RX_COMMA_ALIGN_WORD + Alignment boundary + Select which data byte boundaries are allowed for comma alignment + 2 + + + RX_COMMA_SHOW_REALIGN_ENABLE + Show realign comma + Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency + true + + + RX_SLIDE_MODE + Manual alignment (RXSLIDE) mode + Select whether to enable manual alignment, and in what mode if enabled + OFF + + + RX_CB_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable channel bonding, and how many sequences to use if enabled + 0 + + + + false + + + + + + RX_CB_LEN_SEQ + Length of each sequence + Select the number of characters in each channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_SKEW + Sequence maximum skew + Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_LEVEL + Maximum channel bonding level to be used + Select the maximum channel bonding level that will be used in the system channel bonding topology + 1 + + + + false + + + + + + RX_CB_MASK + 00000000 + + + + false + + + + + + RX_CB_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + + + + false + + + + + + RX_CB_K + 00000000 + + + + false + + + + + + RX_CB_DISP + 00000000 + + + + false + + + + + + RX_CB_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable clock correction, and how many sequences to use if enabled + 2 + + + RX_CC_LEN_SEQ + Length of each sequence + Select the number of characters in each channel clock correction sequence + 4 + + + RX_CC_PERIODICITY + Periodicity of the sequence (in bytes) + Specify the separation between clock correction sequences, in bytes + 5000 + + + RX_CC_KEEP_IDLE + Keep idle + Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received + ENABLE + + + RX_CC_PRECEDENCE + Precedence + Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time + ENABLE + + + + false + + + + + + RX_CC_REPEAT_WAIT + Minimum repetition + Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction + 0 + + + RX_CC_MASK + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + 00000000 + + + + false + + + + + + RX_CC_VAL + 00010100000010111100000101000000101111000001010000001011110000110001010010111100 + + + RX_CC_K + 01010101 + + + + false + + + + + + RX_CC_DISP + 00000000 + + + + false + + + + + + RX_CC_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_0 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_0_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_1 + Value + Specify the value for this clock correction sequence and pattern + 11000101 + + + RX_CC_K_0_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_2 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_0_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_3 + Value + Specify the value for this clock correction sequence and pattern + 01010000 + + + RX_CC_K_0_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_0 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_1_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_1 + Value + Specify the value for this clock correction sequence and pattern + 01010000 + + + RX_CC_K_1_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_2 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_1_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_3 + Value + Specify the value for this clock correction sequence and pattern + 01010000 + + + RX_CC_K_1_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + ENABLE_OPTIONAL_PORTS + Enable optional ports + Indicate whether a port should be included + rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpmareset_in rxresetdone_out txresetdone_out + + + RX_REFCLK_SOURCE + Receiver reference clock source + Select a reference clock input to drive the PLL chosen for receiver operation + X0Y8 clk0+2 + + + TX_REFCLK_SOURCE + Transmitter reference clock source + Select a reference clock input to drive the PLL chosen for transmitter operation + X0Y8 clk0+2 + + + RX_RECCLK_OUTPUT + Drive recovered clock out of device + Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use + + + + LOCATE_RESET_CONTROLLER + Include reset controller in the + Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + LOCATE_TX_BUFFER_BYPASS_CONTROLLER + Include transmitter buffer bypass controller in the + If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_RX_BUFFER_BYPASS_CONTROLLER + Include receiver elastic buffer bypass controller in the + If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_IN_SYSTEM_IBERT_CORE + Include In-System IBERT core + Indicate whether or not the In-System IBERT core should be instantiated in the example design. + EXAMPLE_DESIGN + + + LOCATE_TX_USER_CLOCKING + Include simple transmitter user clocking network in the + Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_RX_USER_CLOCKING + Include simple receiver user clocking network in the + Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_USER_DATA_WIDTH_SIZING + Include user data width sizing in the + Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + ORGANIZE_PORTS_BY + In the example design, organize ports across multiple channels by + If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) + NAME + + + + false + + + + + + PRESET + Transceiver configuration preset + You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard + None + + + INTERNAL_PRESET + Transceiver configuration preset + None + + + INTERNAL_PORT_USAGE_UPDATED + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLEMENT_UPDATED + 24 + + + + false + + + + + + INTERNAL_CHANNEL_SITES_UPDATED + 7 + + + + false + + + + + + INTERNAL_CHANNEL_COLUMN_LOC_MAX + 96 + + + + false + + + + + + INTERNAL_RX_COMMA_PRESET_UPDATE + 9 + + + + false + + + + + + INTERNAL_UPDATE_IP_SYMBOL_drpclk_in + true + + + + false + + + + + + SECONDARY_QPLL_ENABLE + Enable secondary QPLL + Enable and configure the QPLL which is not used in this core configuration + false + + + + false + + + + + + SECONDARY_QPLL_LINE_RATE + Line rate of second core (Gb/s) + Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL + 10.3125 + + + + false + + + + + + SECONDARY_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection + 0 + + + + false + + + + + + SECONDARY_QPLL_REFCLK_FREQUENCY + Actual Reference clock frequency (MHz) + Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate + 257.8125 + + + + false + + + + + + TXPROGDIV_FREQ_ENABLE + Enable selectable TXOUTCLK frequency + Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency + false + + + + false + + + + + + TXPROGDIV_FREQ_SOURCE + Programmable divider clock source + Select which PLL source is used to generate the selectable TXOUTCLK frequency + CPLL + + + + false + + + + + + TXPROGDIV_FREQ_VAL + TXOUTCLK frequency (MHz) + Select the TXOUTCLK frequency to be generated by the TX programmable divider + 120 + + + + false + + + + + + SATA_TX_BURST_LEN + TX COM sequence burst length + Select the number of bursts that make up a SATA COM sequence + 15 + + + FREERUN_FREQUENCY + Free-running and DRP clock frequency (MHz) + Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface + 100 + + + INCLUDE_CPLL_CAL + 2 + + + USER_GTPOWERGOOD_DELAY_EN + Select 1 to enable powergood delay circuit + 1 + + + DISABLE_LOC_XDC + Select to disable generation of LOC constraints in xdc + 0 + + + ENABLE_COMMON_USRCLK + 0 + + + USB_ENABLE + false + + + PCIE_64BIT + false + + + PCIE_GEN4_EIOS + false + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGBYPASSB_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGMONITORENB_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGPDB_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK00_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK01_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK10_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK11_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0PD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1PD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD2_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD3_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD4_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RCALENB_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0DATA_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0WIDTH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1DATA_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1RESET_IN + -1 + + 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+ + INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMREGEN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTDI_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT + -1 + + + + false + + + + + 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INTERNAL_PORT_ENABLED_DRPDI_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANMODE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANRESET_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN + 0 + + + + false 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+ + + + INTERNAL_PORT_ENABLED_RXELECIDLE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXHEADER_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXHEADERVALID_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXLFPSTRESETDET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXLFPSU2LPEXITDET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXLFPSU3WAKEDET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXMONITOROUT_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTSTARTED_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTSTROBEDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTSTROBESTARTED_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOUTCLK_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRBSERR_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXQPISENN_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXQPISENP_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRATEDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSTATUS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXVALID_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDCCDONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXOUTCLK_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXQPISENN_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXQPISENP_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXRATEDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT + 0 + + + + false + + + + + + Component_Name + gth_xcku_2gbps4_120mhz + + + + + UltraScale FPGAs Transceivers Wizard + 8 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.1 + + + + + + + diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd deleted file mode 100644 index ca8cc66..0000000 --- a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd +++ /dev/null @@ -1,365 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -library unisim; -use unisim.vcomponents.all; - -entity gth_xcku_quad_x0y2_top is - port ( - CLK_100 : in std_logic; - GTREFCLK : in std_logic; - RXOUTCLK : out std_logic_vector(3 downto 0); - TXOUTCLK : out std_logic_vector(3 downto 0); - RXUSRCLK : in std_logic_vector(3 downto 0); - RXUSRCLK_DOUBLE : in std_logic_vector(3 downto 0); - TXUSRCLK : in std_logic_vector(3 downto 0); - TXUSRCLK_DOUBLE : in std_logic_vector(3 downto 0); - - RXUSRCLK_ACTIVE : in std_logic; - TXUSRCLK_ACTIVE : in std_logic; - RESET_ALL : in std_logic; - RXPMARESET : in std_logic_vector(3 downto 0); - RXPCSRESET : in std_logic_vector(3 downto 0); - TXPMARESET : in std_logic_vector(3 downto 0); - TXPCSRESET : in std_logic_vector(3 downto 0); - - INIT_DONE : out std_logic; - RXRESETDONE : out std_logic_vector(3 downto 0); - TXRESETDONE : out std_logic_vector(3 downto 0); - RXPMARESETDONE : out std_logic_vector(3 downto 0); - TXPMARESETDONE : out std_logic_vector(3 downto 0); - RXBYTEISALIGNED : out std_logic_vector(3 downto 0); - - RXN : in std_logic_vector(3 downto 0); - RXP : in std_logic_vector(3 downto 0); - TXN : out std_logic_vector(3 downto 0); - TXP : out std_logic_vector(3 downto 0); - - TXDATA : in std_logic_vector(31 downto 0); - TXCHARISK : in std_logic_vector(3 downto 0); - TXCHARDISPMODE : in std_logic_vector(3 downto 0); - TXCHARDISPVAL : in std_logic_vector(3 downto 0); - - RXDATA : out std_logic_vector(31 downto 0); - RXCHARISK : out std_logic_vector(3 downto 0); - RXCHARISCOMMA : out std_logic_vector(3 downto 0); - RXNOTINTABLE : out std_logic_vector(3 downto 0); - RXDISPERR : out std_logic_vector(3 downto 0); - - DRPADDR : in std_logic_vector(35 downto 0); - DRPCLK : in std_logic_vector(3 downto 0); - DRPDI : in std_logic_vector(63 downto 0); - DRPEN : in std_logic_vector(3 downto 0); - DRPWE : in std_logic_vector(3 downto 0); - DRPDO : out std_logic_vector(63 downto 0); - DRPRDY : out std_logic_vector(3 downto 0); - - EYESCANRESET : in std_logic_vector(3 downto 0); - RXLPMEN : in std_logic_vector(3 downto 0); - RXRATE : in std_logic_vector(11 downto 0); - TXDIFFCTRL : in std_logic_vector(15 downto 0); - TXPOSTCURSOR : in std_logic_vector(19 downto 0); - TXPRECURSOR : in std_logic_vector(19 downto 0) - ); -end entity gth_xcku_quad_x0y2_top; - -architecture behavioral of gth_xcku_quad_x0y2_top is - component gth_xcku_init is - generic ( - P_FREERUN_FREQUENCY : integer := 100; - P_TX_TIMER_DURATION_US : integer := 30000; - P_RX_TIMER_DURATION_US : integer := 130000 - ); - port ( - clk_freerun_in : in std_logic; - reset_all_in : in std_logic; - tx_init_done_in : in std_logic; - rx_init_done_in : in std_logic; - rx_data_good_in : in std_logic; - reset_all_out : out std_logic := '0'; - reset_rx_out : out std_logic := '0'; - init_done_out : out std_logic := '0'; - retry_ctr_out : out std_logic_vector(3 downto 0) := x"0" - ); - end component; - - component gth_xcku_quad_x0y2 - port ( - gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); - gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); - gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); - gtwiz_reset_all_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); - gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_userdata_tx_in : in std_logic_vector(63 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(63 downto 0); - gtrefclk00_in : in std_logic_vector(0 downto 0); - qpll0outclk_out : out std_logic_vector(0 downto 0); - qpll0outrefclk_out : out std_logic_vector(0 downto 0); - drpaddr_in : in std_logic_vector(35 downto 0); - drpclk_in : in std_logic_vector(3 downto 0); - drpdi_in : in std_logic_vector(63 downto 0); - drpen_in : in std_logic_vector(3 downto 0); - drpwe_in : in std_logic_vector(3 downto 0); - eyescanreset_in : in std_logic_vector(3 downto 0); - gthrxn_in : in std_logic_vector(3 downto 0); - gthrxp_in : in std_logic_vector(3 downto 0); - rx8b10ben_in : in std_logic_vector(3 downto 0); - rxbufreset_in : in std_logic_vector(3 downto 0); - rxcdrreset_in : in std_logic_vector(3 downto 0); - rxcommadeten_in : in std_logic_vector(3 downto 0); - rxlpmen_in : in std_logic_vector(3 downto 0); - rxmcommaalignen_in : in std_logic_vector(3 downto 0); - rxpcommaalignen_in : in std_logic_vector(3 downto 0); - rxpcsreset_in : in std_logic_vector(3 downto 0); - rxpmareset_in : in std_logic_vector(3 downto 0); - rxrate_in : in std_logic_vector(11 downto 0); - rxusrclk_in : in std_logic_vector(3 downto 0); - rxusrclk2_in : in std_logic_vector(3 downto 0); - tx8b10ben_in : in std_logic_vector(3 downto 0); - txctrl0_in : in std_logic_vector(63 downto 0); - txctrl1_in : in std_logic_vector(63 downto 0); - txctrl2_in : in std_logic_vector(31 downto 0); - txdiffctrl_in : in std_logic_vector(15 downto 0); - txpcsreset_in : in std_logic_vector(3 downto 0); - txpmareset_in : in std_logic_vector(3 downto 0); - txpostcursor_in : in std_logic_vector(19 downto 0); - txprecursor_in : in std_logic_vector(19 downto 0); - txusrclk_in : in std_logic_vector(3 downto 0); - txusrclk2_in : in std_logic_vector(3 downto 0); - drpdo_out : out std_logic_vector(63 downto 0); - drprdy_out : out std_logic_vector(3 downto 0); - gthtxn_out : out std_logic_vector(3 downto 0); - gthtxp_out : out std_logic_vector(3 downto 0); - gtpowergood_out : out std_logic_vector(3 downto 0); - rxbufstatus_out : out std_logic_vector(11 downto 0); - rxbyteisaligned_out : out std_logic_vector(3 downto 0); - rxbyterealign_out : out std_logic_vector(3 downto 0); - rxclkcorcnt_out : out std_logic_vector(7 downto 0); - rxcommadet_out : out std_logic_vector(3 downto 0); - rxctrl0_out : out std_logic_vector(63 downto 0); - rxctrl1_out : out std_logic_vector(63 downto 0); - rxctrl2_out : out std_logic_vector(31 downto 0); - rxctrl3_out : out std_logic_vector(31 downto 0); - rxoutclk_out : out std_logic_vector(3 downto 0); - rxpmaresetdone_out : out std_logic_vector(3 downto 0); - rxresetdone_out : out std_logic_vector(3 downto 0); - txoutclk_out : out std_logic_vector(3 downto 0); - txpmaresetdone_out : out std_logic_vector(3 downto 0); - txresetdone_out : out std_logic_vector(3 downto 0) - ); - end component; - - signal reset_tx_done_i : std_logic; - signal reset_rx_done_i : std_logic; - signal reset_all_i : std_logic; - - signal gtwiz_userdata_rx : std_logic_vector(63 downto 0); - signal rxctrl0 : std_logic_vector(63 downto 0); - signal rxctrl1 : std_logic_vector(63 downto 0); - signal rxctrl2 : std_logic_vector(31 downto 0); - signal rxctrl3 : std_logic_vector(31 downto 0); - - signal gtwiz_userdata_tx : std_logic_vector(63 downto 0); - signal txctrl0 : std_logic_vector(63 downto 0) := (others => '0'); - signal txctrl1 : std_logic_vector(63 downto 0) := (others => '0'); - signal txctrl2 : std_logic_vector(31 downto 0) := (others => '0'); -begin - THE_INIT : gth_xcku_init - port map ( - clk_freerun_in => CLK_100, - reset_all_in => RESET_ALL, - tx_init_done_in => reset_tx_done_i, - rx_init_done_in => reset_rx_done_i, - rx_data_good_in => '1', - reset_all_out => reset_all_i, - reset_rx_out => open, - init_done_out => INIT_DONE, - retry_ctr_out => open - ); - - - generate_lanes: - for i in 0 to 3 generate - signal rx16data : std_logic_vector(15 downto 0); - signal rx16charisk : std_logic_vector(1 downto 0); - signal rx16chariscomma : std_logic_vector(1 downto 0); - signal rx16notintable : std_logic_vector(1 downto 0); - signal rx16disperr : std_logic_vector(1 downto 0); - - signal rx16data_reg : std_logic_vector(15 downto 0) := x"0000"; - signal rx16charisk_reg : std_logic_vector(1 downto 0) := "00"; - signal rx16chariscomma_reg : std_logic_vector(1 downto 0) := "00"; - signal rx16notintable_reg : std_logic_vector(1 downto 0) := "00"; - signal rx16disperr_reg : std_logic_vector(1 downto 0) := "00"; - - signal rxusrclk_toggle : std_logic := '0'; - signal rxusrclk_toggle_reg : std_logic := '0'; - signal rxusrclk_phase : std_logic := '0'; - - signal txdata_reg : std_logic_vector(7 downto 0) := x"00"; - signal txcharisk_reg : std_logic := '0'; - signal txchardispmode_reg : std_logic := '0'; - signal txchardispval_reg : std_logic := '0'; - - signal tx16data : std_logic_vector(15 downto 0); - signal tx16charisk : std_logic_vector(1 downto 0); - signal tx16chardispmode : std_logic_vector(1 downto 0); - signal tx16chardispval : std_logic_vector(1 downto 0); - begin - rx16data <= gtwiz_userdata_rx(16 * i + 15 downto 16 * i); - rx16charisk <= rxctrl0(16 * i + 1 downto 16 * i); - rx16disperr <= rxctrl1(16 * i + 1 downto 16 * i); - rx16chariscomma <= rxctrl2(8 * i + 1 downto 8 * i); - rx16notintable <= rxctrl3(8 * i + 1 downto 8 * i); - - process (RXUSRCLK) is - begin - if rising_edge(RXUSRCLK(i)) then - rx16data_reg <= rx16data; - rx16charisk_reg <= rx16charisk; - rx16chariscomma_reg <= rx16chariscomma; - rx16notintable_reg <= rx16notintable; - rx16disperr_reg <= rx16disperr; - - rxusrclk_toggle <= not rxusrclk_toggle; - end if; - end process; - - process (RXUSRCLK_DOUBLE) is - begin - if rising_edge(RXUSRCLK_DOUBLE(i)) then - rxusrclk_toggle_reg <= rxusrclk_toggle; - rxusrclk_phase <= rxusrclk_toggle xor rxusrclk_toggle_reg; - - if rxusrclk_phase = '0' then - RXDATA(8 * i + 7 downto 8 * i) <= rx16data_reg(7 downto 0); - RXCHARISK(i) <= rx16charisk_reg(0); - RXCHARISCOMMA(i) <= rx16chariscomma_reg(0); - RXNOTINTABLE(i) <= rx16notintable_reg(0); - RXDISPERR(i) <= rx16disperr_reg(0); - else - RXDATA(8 * i + 7 downto 8 * i) <= rx16data_reg(15 downto 8); - RXCHARISK(i) <= rx16charisk_reg(1); - RXCHARISCOMMA(i) <= rx16chariscomma_reg(1); - RXNOTINTABLE(i) <= rx16notintable_reg(1); - RXDISPERR(i) <= rx16disperr_reg(1); - end if; - end if; - end process; - - process (TXUSRCLK_DOUBLE) is - begin - if rising_edge(TXUSRCLK_DOUBLE(i)) then - txdata_reg <= TXDATA(8 * i + 7 downto 8 * i); - txcharisk_reg <= TXCHARISK(i); - txchardispmode_reg <= TXCHARDISPMODE(i); - txchardispval_reg <= TXCHARDISPVAL(i); - end if; - end process; - - process (TXUSRCLK) is - begin - if rising_edge(TXUSRCLK(i)) then - tx16data <= TXDATA(8 * i + 7 downto 8 * i) & txdata_reg; - tx16charisk <= TXCHARISK(i) & txcharisk_reg; - tx16chardispmode <= TXCHARDISPMODE(i) & txchardispmode_reg; - tx16chardispval <= TXCHARDISPVAL(i) & txchardispval_reg; - end if; - end process; - - gtwiz_userdata_tx(16 * i + 15 downto 16 * i) <= tx16data; - txctrl0(16 * i + 1 downto 16 * i) <= tx16chardispval; - txctrl1(16 * i + 1 downto 16 * i) <= tx16chardispmode; - txctrl2(8 * i + 1 downto 8 * i) <= tx16charisk; - end generate generate_lanes; - - - THE_GTH : gth_xcku_quad_x0y2 - port map ( - gtwiz_userclk_tx_active_in(0) => TXUSRCLK_ACTIVE, - gtwiz_userclk_rx_active_in(0) => RXUSRCLK_ACTIVE, - gtwiz_reset_clk_freerun_in(0) => CLK_100, - gtwiz_reset_all_in(0) => reset_all_i, - gtwiz_reset_tx_pll_and_datapath_in(0) => '0', - gtwiz_reset_tx_datapath_in(0) => '0', - gtwiz_reset_rx_pll_and_datapath_in(0) => '0', - gtwiz_reset_rx_datapath_in(0) => '0', - gtwiz_reset_rx_cdr_stable_out => open, - gtwiz_reset_tx_done_out(0) => reset_tx_done_i, - gtwiz_reset_rx_done_out(0) => reset_rx_done_i, - gtwiz_userdata_tx_in => gtwiz_userdata_tx, - gtwiz_userdata_rx_out => gtwiz_userdata_rx, - gtrefclk00_in(0) => GTREFCLK, - qpll0outclk_out => open, - qpll0outrefclk_out => open, - drpaddr_in => DRPADDR, - drpclk_in => DRPCLK, - drpdi_in => DRPDI, - drpen_in => DRPEN, - drpwe_in => DRPWE, - eyescanreset_in => EYESCANRESET, - gthrxn_in => RXN, - gthrxp_in => RXP, - rx8b10ben_in => "1111", - rxbufreset_in => "0000", - rxcdrreset_in => "0000", - rxcommadeten_in => "1111", - rxlpmen_in => RXLPMEN, - rxmcommaalignen_in => "1111", - rxpcommaalignen_in => "1111", - rxpcsreset_in => RXPCSRESET, - rxpmareset_in => RXPMARESET, - rxrate_in => RXRATE, - rxusrclk_in(0) => RXUSRCLK(0), - rxusrclk_in(1) => RXUSRCLK(1), - rxusrclk_in(2) => RXUSRCLK(2), - rxusrclk_in(3) => RXUSRCLK(3), - rxusrclk2_in(0) => RXUSRCLK(0), - rxusrclk2_in(1) => RXUSRCLK(1), - rxusrclk2_in(2) => RXUSRCLK(2), - rxusrclk2_in(3) => RXUSRCLK(3), - tx8b10ben_in => "1111", - txctrl0_in => txctrl0, - txctrl1_in => txctrl1, - txctrl2_in => txctrl2, - txdiffctrl_in => TXDIFFCTRL, - txpcsreset_in => TXPCSRESET, - txpmareset_in => TXPMARESET, - txpostcursor_in => TXPOSTCURSOR, - txprecursor_in => TXPRECURSOR, - txusrclk_in(0) => TXUSRCLK(0), - txusrclk_in(1) => TXUSRCLK(1), - txusrclk_in(2) => TXUSRCLK(2), - txusrclk_in(3) => TXUSRCLK(3), - txusrclk2_in(0) => TXUSRCLK(0), - txusrclk2_in(1) => TXUSRCLK(1), - txusrclk2_in(2) => TXUSRCLK(2), - txusrclk2_in(3) => TXUSRCLK(3), - drpdo_out => DRPDO, - drprdy_out => DRPRDY, - gthtxn_out => TXN, - gthtxp_out => TXP, - gtpowergood_out => open, - rxbufstatus_out => open, - rxbyteisaligned_out => RXBYTEISALIGNED, - rxbyterealign_out => open, - rxclkcorcnt_out => open, - rxcommadet_out => open, - rxctrl0_out => rxctrl0, - rxctrl1_out => rxctrl1, - rxctrl2_out => rxctrl2, - rxctrl3_out => rxctrl3, - rxoutclk_out => RXOUTCLK, - rxpmaresetdone_out => RXPMARESETDONE, - rxresetdone_out => RXRESETDONE, - txoutclk_out => TXOUTCLK, - txpmaresetdone_out => TXPMARESETDONE, - txresetdone_out => TXRESETDONE - ); -end architecture behavioral; diff --git a/media_interfaces/xcku/gth_xcku_top.vhd b/media_interfaces/xcku/gth_xcku_top.vhd new file mode 100644 index 0000000..0c0187d --- /dev/null +++ b/media_interfaces/xcku/gth_xcku_top.vhd @@ -0,0 +1,611 @@ +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.all; + +entity gth_xcku_top is + generic ( + LINE_RATE_KBPS : integer := 2000000; + REFCLK_FREQ_HZ : integer := 100000000 + ); + port ( + CLK_100 : in std_logic; + GTREFCLK : in std_logic; + RXOUTCLK : out std_logic; + TXOUTCLK : out std_logic; + RXUSRCLK : in std_logic; + RXUSRCLK_DOUBLE : in std_logic; + TXUSRCLK : in std_logic; + TXUSRCLK_DOUBLE : in std_logic; + + RXUSRCLK_ACTIVE : in std_logic; + TXUSRCLK_ACTIVE : in std_logic; + RESET_ALL : in std_logic; + RXPMARESET : in std_logic; + RXPCSRESET : in std_logic; + TXPMARESET : in std_logic; + TXPCSRESET : in std_logic; + + INIT_DONE : out std_logic; + RXRESETDONE : out std_logic; + TXRESETDONE : out std_logic; + RXPMARESETDONE : out std_logic; + TXPMARESETDONE : out std_logic; + RXBYTEISALIGNED : out std_logic; + + RXN : in std_logic; + RXP : in std_logic; + TXN : out std_logic; + TXP : out std_logic; + + TXDATA : in std_logic_vector(7 downto 0); + TXCHARISK : in std_logic; + TXCHARDISPMODE : in std_logic; + TXCHARDISPVAL : in std_logic; + + RXDATA : out std_logic_vector(7 downto 0); + RXCHARISK : out std_logic; + RXCHARISCOMMA : out std_logic; + RXNOTINTABLE : out std_logic; + RXDISPERR : out std_logic; + + DRPADDR : in std_logic_vector(8 downto 0); + DRPCLK : in std_logic; + DRPDI : in std_logic_vector(15 downto 0); + DRPEN : in std_logic; + DRPWE : in std_logic; + DRPDO : out std_logic_vector(15 downto 0); + DRPRDY : out std_logic; + + EYESCANRESET : in std_logic; + RXLPMEN : in std_logic; + RXRATE : in std_logic_vector(2 downto 0); + TXDIFFCTRL : in std_logic_vector(3 downto 0); + TXPOSTCURSOR : in std_logic_vector(4 downto 0); + TXPRECURSOR : in std_logic_vector(4 downto 0) + ); +end entity gth_xcku_top; + +architecture behavioral of gth_xcku_top is + component gth_xcku_2gbps0_100mhz + port ( + gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); + gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); + gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); + gtwiz_reset_all_in : in std_logic_vector(0 downto 0); + gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); + gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); + gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); + gtwiz_userdata_tx_in : in std_logic_vector(15 downto 0); + gtwiz_userdata_rx_out : out std_logic_vector(15 downto 0); + drpaddr_in : in std_logic_vector(8 downto 0); + drpclk_in : in std_logic_vector(0 downto 0); + drpdi_in : in std_logic_vector(15 downto 0); + drpen_in : in std_logic_vector(0 downto 0); + drpwe_in : in std_logic_vector(0 downto 0); + eyescanreset_in : in std_logic_vector(0 downto 0); + gthrxn_in : in std_logic_vector(0 downto 0); + gthrxp_in : in std_logic_vector(0 downto 0); + gtrefclk0_in : in std_logic_vector(0 downto 0); + rx8b10ben_in : in std_logic_vector(0 downto 0); + rxbufreset_in : in std_logic_vector(0 downto 0); + rxcdrreset_in : in std_logic_vector(0 downto 0); + rxcommadeten_in : in std_logic_vector(0 downto 0); + rxlpmen_in : in std_logic_vector(0 downto 0); + rxmcommaalignen_in : in std_logic_vector(0 downto 0); + rxpcommaalignen_in : in std_logic_vector(0 downto 0); + rxpcsreset_in : in std_logic_vector(0 downto 0); + rxpmareset_in : in std_logic_vector(0 downto 0); + rxrate_in : in std_logic_vector(2 downto 0); + rxusrclk_in : in std_logic_vector(0 downto 0); + rxusrclk2_in : in std_logic_vector(0 downto 0); + tx8b10ben_in : in std_logic_vector(0 downto 0); + txctrl0_in : in std_logic_vector(15 downto 0); + txctrl1_in : in std_logic_vector(15 downto 0); + txctrl2_in : in std_logic_vector(7 downto 0); + txdiffctrl_in : in std_logic_vector(3 downto 0); + txpcsreset_in : in std_logic_vector(0 downto 0); + txpmareset_in : in std_logic_vector(0 downto 0); + txpostcursor_in : in std_logic_vector(4 downto 0); + txprecursor_in : in std_logic_vector(4 downto 0); + txusrclk_in : in std_logic_vector(0 downto 0); + txusrclk2_in : in std_logic_vector(0 downto 0); + drpdo_out : out std_logic_vector(15 downto 0); + drprdy_out : out std_logic_vector(0 downto 0); + gthtxn_out : out std_logic_vector(0 downto 0); + gthtxp_out : out std_logic_vector(0 downto 0); + gtpowergood_out : out std_logic_vector(0 downto 0); + rxbufstatus_out : out std_logic_vector(2 downto 0); + rxbyteisaligned_out : out std_logic_vector(0 downto 0); + rxbyterealign_out : out std_logic_vector(0 downto 0); + rxclkcorcnt_out : out std_logic_vector(1 downto 0); + rxcommadet_out : out std_logic_vector(0 downto 0); + rxctrl0_out : out std_logic_vector(15 downto 0); + rxctrl1_out : out std_logic_vector(15 downto 0); + rxctrl2_out : out std_logic_vector(7 downto 0); + rxctrl3_out : out std_logic_vector(7 downto 0); + rxoutclk_out : out std_logic_vector(0 downto 0); + rxpmaresetdone_out : out std_logic_vector(0 downto 0); + rxresetdone_out : out std_logic_vector(0 downto 0); + txoutclk_out : out std_logic_vector(0 downto 0); + txpmaresetdone_out : out std_logic_vector(0 downto 0); + txresetdone_out : out std_logic_vector(0 downto 0) + ); + end component; + + component gth_xcku_2gbps0_200mhz + port ( + gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); + gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); + gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); + gtwiz_reset_all_in : in std_logic_vector(0 downto 0); + gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); + gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); + gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); + gtwiz_userdata_tx_in : in std_logic_vector(15 downto 0); + gtwiz_userdata_rx_out : out std_logic_vector(15 downto 0); + drpaddr_in : in std_logic_vector(8 downto 0); + drpclk_in : in std_logic_vector(0 downto 0); + drpdi_in : in std_logic_vector(15 downto 0); + drpen_in : in std_logic_vector(0 downto 0); + drpwe_in : in std_logic_vector(0 downto 0); + eyescanreset_in : in std_logic_vector(0 downto 0); + gthrxn_in : in std_logic_vector(0 downto 0); + gthrxp_in : in std_logic_vector(0 downto 0); + gtrefclk0_in : in std_logic_vector(0 downto 0); + rx8b10ben_in : in std_logic_vector(0 downto 0); + rxbufreset_in : in std_logic_vector(0 downto 0); + rxcdrreset_in : in std_logic_vector(0 downto 0); + rxcommadeten_in : in std_logic_vector(0 downto 0); + rxlpmen_in : in std_logic_vector(0 downto 0); + rxmcommaalignen_in : in std_logic_vector(0 downto 0); + rxpcommaalignen_in : in std_logic_vector(0 downto 0); + rxpcsreset_in : in std_logic_vector(0 downto 0); + rxpmareset_in : in std_logic_vector(0 downto 0); + rxrate_in : in std_logic_vector(2 downto 0); + rxusrclk_in : in std_logic_vector(0 downto 0); + rxusrclk2_in : in std_logic_vector(0 downto 0); + tx8b10ben_in : in std_logic_vector(0 downto 0); + txctrl0_in : in std_logic_vector(15 downto 0); + txctrl1_in : in std_logic_vector(15 downto 0); + txctrl2_in : in std_logic_vector(7 downto 0); + txdiffctrl_in : in std_logic_vector(3 downto 0); + txpcsreset_in : in std_logic_vector(0 downto 0); + txpmareset_in : in std_logic_vector(0 downto 0); + txpostcursor_in : in std_logic_vector(4 downto 0); + txprecursor_in : in std_logic_vector(4 downto 0); + txusrclk_in : in std_logic_vector(0 downto 0); + txusrclk2_in : in std_logic_vector(0 downto 0); + drpdo_out : out std_logic_vector(15 downto 0); + drprdy_out : out std_logic_vector(0 downto 0); + gthtxn_out : out std_logic_vector(0 downto 0); + gthtxp_out : out std_logic_vector(0 downto 0); + gtpowergood_out : out std_logic_vector(0 downto 0); + rxbufstatus_out : out std_logic_vector(2 downto 0); + rxbyteisaligned_out : out std_logic_vector(0 downto 0); + rxbyterealign_out : out std_logic_vector(0 downto 0); + rxclkcorcnt_out : out std_logic_vector(1 downto 0); + rxcommadet_out : out std_logic_vector(0 downto 0); + rxctrl0_out : out std_logic_vector(15 downto 0); + rxctrl1_out : out std_logic_vector(15 downto 0); + rxctrl2_out : out std_logic_vector(7 downto 0); + rxctrl3_out : out std_logic_vector(7 downto 0); + rxoutclk_out : out std_logic_vector(0 downto 0); + rxpmaresetdone_out : out std_logic_vector(0 downto 0); + rxresetdone_out : out std_logic_vector(0 downto 0); + txoutclk_out : out std_logic_vector(0 downto 0); + txpmaresetdone_out : out std_logic_vector(0 downto 0); + txresetdone_out : out std_logic_vector(0 downto 0) + ); + end component; + + component gth_xcku_2gbps4_120mhz + port ( + gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); + gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); + gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); + gtwiz_reset_all_in : in std_logic_vector(0 downto 0); + gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); + gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); + gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); + gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); + gtwiz_userdata_tx_in : in std_logic_vector(15 downto 0); + gtwiz_userdata_rx_out : out std_logic_vector(15 downto 0); + drpaddr_in : in std_logic_vector(8 downto 0); + drpclk_in : in std_logic_vector(0 downto 0); + drpdi_in : in std_logic_vector(15 downto 0); + drpen_in : in std_logic_vector(0 downto 0); + drpwe_in : in std_logic_vector(0 downto 0); + eyescanreset_in : in std_logic_vector(0 downto 0); + gthrxn_in : in std_logic_vector(0 downto 0); + gthrxp_in : in std_logic_vector(0 downto 0); + gtrefclk0_in : in std_logic_vector(0 downto 0); + rx8b10ben_in : in std_logic_vector(0 downto 0); + rxbufreset_in : in std_logic_vector(0 downto 0); + rxcdrreset_in : in std_logic_vector(0 downto 0); + rxcommadeten_in : in std_logic_vector(0 downto 0); + rxlpmen_in : in std_logic_vector(0 downto 0); + rxmcommaalignen_in : in std_logic_vector(0 downto 0); + rxpcommaalignen_in : in std_logic_vector(0 downto 0); + rxpcsreset_in : in std_logic_vector(0 downto 0); + rxpmareset_in : in std_logic_vector(0 downto 0); + rxrate_in : in std_logic_vector(2 downto 0); + rxusrclk_in : in std_logic_vector(0 downto 0); + rxusrclk2_in : in std_logic_vector(0 downto 0); + tx8b10ben_in : in std_logic_vector(0 downto 0); + txctrl0_in : in std_logic_vector(15 downto 0); + txctrl1_in : in std_logic_vector(15 downto 0); + txctrl2_in : in std_logic_vector(7 downto 0); + txdiffctrl_in : in std_logic_vector(3 downto 0); + txpcsreset_in : in std_logic_vector(0 downto 0); + txpmareset_in : in std_logic_vector(0 downto 0); + txpostcursor_in : in std_logic_vector(4 downto 0); + txprecursor_in : in std_logic_vector(4 downto 0); + txusrclk_in : in std_logic_vector(0 downto 0); + txusrclk2_in : in std_logic_vector(0 downto 0); + drpdo_out : out std_logic_vector(15 downto 0); + drprdy_out : out std_logic_vector(0 downto 0); + gthtxn_out : out std_logic_vector(0 downto 0); + gthtxp_out : out std_logic_vector(0 downto 0); + gtpowergood_out : out std_logic_vector(0 downto 0); + rxbufstatus_out : out std_logic_vector(2 downto 0); + rxbyteisaligned_out : out std_logic_vector(0 downto 0); + rxbyterealign_out : out std_logic_vector(0 downto 0); + rxclkcorcnt_out : out std_logic_vector(1 downto 0); + rxcommadet_out : out std_logic_vector(0 downto 0); + rxctrl0_out : out std_logic_vector(15 downto 0); + rxctrl1_out : out std_logic_vector(15 downto 0); + rxctrl2_out : out std_logic_vector(7 downto 0); + rxctrl3_out : out std_logic_vector(7 downto 0); + rxoutclk_out : out std_logic_vector(0 downto 0); + rxpmaresetdone_out : out std_logic_vector(0 downto 0); + rxresetdone_out : out std_logic_vector(0 downto 0); + txoutclk_out : out std_logic_vector(0 downto 0); + txpmaresetdone_out : out std_logic_vector(0 downto 0); + txresetdone_out : out std_logic_vector(0 downto 0) + ); + end component; + + signal reset_tx_done_i : std_logic; + signal reset_rx_done_i : std_logic; + + signal rxctrl0 : std_logic_vector(15 downto 0); + signal rxctrl1 : std_logic_vector(15 downto 0); + signal rxctrl2 : std_logic_vector(7 downto 0); + signal rxctrl3 : std_logic_vector(7 downto 0); + + signal txctrl0 : std_logic_vector(15 downto 0) := (others => '0'); + signal txctrl1 : std_logic_vector(15 downto 0) := (others => '0'); + signal txctrl2 : std_logic_vector(7 downto 0) := (others => '0'); + + signal rx16data : std_logic_vector(15 downto 0); + signal rx16charisk : std_logic_vector(1 downto 0); + signal rx16chariscomma : std_logic_vector(1 downto 0); + signal rx16notintable : std_logic_vector(1 downto 0); + signal rx16disperr : std_logic_vector(1 downto 0); + + signal rx16data_reg : std_logic_vector(15 downto 0) := x"0000"; + signal rx16charisk_reg : std_logic_vector(1 downto 0) := "00"; + signal rx16chariscomma_reg : std_logic_vector(1 downto 0) := "00"; + signal rx16notintable_reg : std_logic_vector(1 downto 0) := "00"; + signal rx16disperr_reg : std_logic_vector(1 downto 0) := "00"; + + signal rxusrclk_toggle : std_logic := '0'; + signal rxusrclk_toggle_reg : std_logic := '0'; + signal rxusrclk_phase : std_logic := '0'; + + signal txdata_reg : std_logic_vector(7 downto 0) := x"00"; + signal txcharisk_reg : std_logic := '0'; + signal txchardispmode_reg : std_logic := '0'; + signal txchardispval_reg : std_logic := '0'; + + signal tx16data : std_logic_vector(15 downto 0); + signal tx16charisk : std_logic_vector(1 downto 0); + signal tx16chardispmode : std_logic_vector(1 downto 0); + signal tx16chardispval : std_logic_vector(1 downto 0); +begin + INIT_DONE <= reset_tx_done_i and reset_rx_done_i; + + rx16charisk <= rxctrl0(1 downto 0); + rx16disperr <= rxctrl1(1 downto 0); + rx16chariscomma <= rxctrl2(1 downto 0); + rx16notintable <= rxctrl3(1 downto 0); + + process (RXUSRCLK) is + begin + if rising_edge(RXUSRCLK) then + rx16data_reg <= rx16data; + rx16charisk_reg <= rx16charisk; + rx16chariscomma_reg <= rx16chariscomma; + rx16notintable_reg <= rx16notintable; + rx16disperr_reg <= rx16disperr; + + rxusrclk_toggle <= not rxusrclk_toggle; + end if; + end process; + + process (RXUSRCLK_DOUBLE) is + begin + if rising_edge(RXUSRCLK_DOUBLE) then + rxusrclk_toggle_reg <= rxusrclk_toggle; + rxusrclk_phase <= rxusrclk_toggle xor rxusrclk_toggle_reg; + + if rxusrclk_phase = '0' then + RXDATA <= rx16data_reg(7 downto 0); + RXCHARISK <= rx16charisk_reg(0); + RXCHARISCOMMA <= rx16chariscomma_reg(0); + RXNOTINTABLE <= rx16notintable_reg(0); + RXDISPERR <= rx16disperr_reg(0); + else + RXDATA <= rx16data_reg(15 downto 8); + RXCHARISK <= rx16charisk_reg(1); + RXCHARISCOMMA <= rx16chariscomma_reg(1); + RXNOTINTABLE <= rx16notintable_reg(1); + RXDISPERR <= rx16disperr_reg(1); + end if; + end if; + end process; + + process (TXUSRCLK_DOUBLE) is + begin + if rising_edge(TXUSRCLK_DOUBLE) then + txdata_reg <= TXDATA; + txcharisk_reg <= TXCHARISK; + txchardispmode_reg <= TXCHARDISPMODE; + txchardispval_reg <= TXCHARDISPVAL; + end if; + end process; + + process (TXUSRCLK) is + begin + if rising_edge(TXUSRCLK) then + tx16data <= TXDATA & txdata_reg; + tx16charisk <= TXCHARISK & txcharisk_reg; + tx16chardispmode <= TXCHARDISPMODE & txchardispmode_reg; + tx16chardispval <= TXCHARDISPVAL & txchardispval_reg; + end if; + end process; + + txctrl0(1 downto 0) <= tx16chardispval; + txctrl1(1 downto 0) <= tx16chardispmode; + txctrl2(1 downto 0) <= tx16charisk; + + + assert (LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 100000000) + or (LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 200000000) + or (LINE_RATE_KBPS = 2400000 and REFCLK_FREQ_HZ = 120000000) + report "Unsupported line rate/reference-clock frequency." + severity failure; + + + generate_2gbps0_100mhz: + if LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 100000000 generate + begin + THE_GTH : gth_xcku_2gbps0_100mhz + port map ( + gtwiz_userclk_tx_active_in(0) => TXUSRCLK_ACTIVE, + gtwiz_userclk_rx_active_in(0) => RXUSRCLK_ACTIVE, + gtwiz_reset_clk_freerun_in(0) => CLK_100, + gtwiz_reset_all_in(0) => RESET_ALL, + gtwiz_reset_tx_pll_and_datapath_in(0) => '0', + gtwiz_reset_tx_datapath_in(0) => '0', + gtwiz_reset_rx_pll_and_datapath_in(0) => '0', + gtwiz_reset_rx_datapath_in(0) => '0', + gtwiz_reset_rx_cdr_stable_out => open, + gtwiz_reset_tx_done_out(0) => reset_tx_done_i, + gtwiz_reset_rx_done_out(0) => reset_rx_done_i, + gtwiz_userdata_tx_in => tx16data, + gtwiz_userdata_rx_out => rx16data, + drpaddr_in => DRPADDR, + drpclk_in(0) => DRPCLK, + drpdi_in => DRPDI, + drpen_in(0) => DRPEN, + drpwe_in(0) => DRPWE, + eyescanreset_in(0) => EYESCANRESET, + gthrxn_in(0) => RXN, + gthrxp_in(0) => RXP, + gtrefclk0_in(0) => GTREFCLK, + rx8b10ben_in => "1", + rxbufreset_in => "0", + rxcdrreset_in => "0", + rxcommadeten_in => "1", + rxlpmen_in(0) => RXLPMEN, + rxmcommaalignen_in => "1", + rxpcommaalignen_in => "1", + rxpcsreset_in(0) => RXPCSRESET, + rxpmareset_in(0) => RXPMARESET, + rxrate_in => RXRATE, + rxusrclk_in(0) => RXUSRCLK, + rxusrclk2_in(0) => RXUSRCLK, + tx8b10ben_in => "1", + txctrl0_in => txctrl0, + txctrl1_in => txctrl1, + txctrl2_in => txctrl2, + txdiffctrl_in => TXDIFFCTRL, + txpcsreset_in(0) => TXPCSRESET, + txpmareset_in(0) => TXPMARESET, + txpostcursor_in => TXPOSTCURSOR, + txprecursor_in => TXPRECURSOR, + txusrclk_in(0) => TXUSRCLK, + txusrclk2_in(0) => TXUSRCLK, + drpdo_out => DRPDO, + drprdy_out(0) => DRPRDY, + gthtxn_out(0) => TXN, + gthtxp_out(0) => TXP, + gtpowergood_out => open, + rxbufstatus_out => open, + rxbyteisaligned_out(0) => RXBYTEISALIGNED, + rxbyterealign_out => open, + rxclkcorcnt_out => open, + rxcommadet_out => open, + rxctrl0_out => rxctrl0, + rxctrl1_out => rxctrl1, + rxctrl2_out => rxctrl2, + rxctrl3_out => rxctrl3, + rxoutclk_out(0) => RXOUTCLK, + rxpmaresetdone_out(0) => RXPMARESETDONE, + rxresetdone_out(0) => RXRESETDONE, + txoutclk_out(0) => TXOUTCLK, + txpmaresetdone_out(0) => TXPMARESETDONE, + txresetdone_out(0) => TXRESETDONE + ); + end generate generate_2gbps0_100mhz; + + generate_2gbps0_200mhz: + if LINE_RATE_KBPS = 2000000 and REFCLK_FREQ_HZ = 200000000 generate + begin + THE_GTH : gth_xcku_2gbps0_200mhz + port map ( + gtwiz_userclk_tx_active_in(0) => TXUSRCLK_ACTIVE, + gtwiz_userclk_rx_active_in(0) => RXUSRCLK_ACTIVE, + gtwiz_reset_clk_freerun_in(0) => CLK_100, + gtwiz_reset_all_in(0) => RESET_ALL, + gtwiz_reset_tx_pll_and_datapath_in(0) => '0', + gtwiz_reset_tx_datapath_in(0) => '0', + gtwiz_reset_rx_pll_and_datapath_in(0) => '0', + gtwiz_reset_rx_datapath_in(0) => '0', + gtwiz_reset_rx_cdr_stable_out => open, + gtwiz_reset_tx_done_out(0) => reset_tx_done_i, + gtwiz_reset_rx_done_out(0) => reset_rx_done_i, + gtwiz_userdata_tx_in => tx16data, + gtwiz_userdata_rx_out => rx16data, + drpaddr_in => DRPADDR, + drpclk_in(0) => DRPCLK, + drpdi_in => DRPDI, + drpen_in(0) => DRPEN, + drpwe_in(0) => DRPWE, + eyescanreset_in(0) => EYESCANRESET, + gthrxn_in(0) => RXN, + gthrxp_in(0) => RXP, + gtrefclk0_in(0) => GTREFCLK, + rx8b10ben_in => "1", + rxbufreset_in => "0", + rxcdrreset_in => "0", + rxcommadeten_in => "1", + rxlpmen_in(0) => RXLPMEN, + rxmcommaalignen_in => "1", + rxpcommaalignen_in => "1", + rxpcsreset_in(0) => RXPCSRESET, + rxpmareset_in(0) => RXPMARESET, + rxrate_in => RXRATE, + rxusrclk_in(0) => RXUSRCLK, + rxusrclk2_in(0) => RXUSRCLK, + tx8b10ben_in => "1", + txctrl0_in => txctrl0, + txctrl1_in => txctrl1, + txctrl2_in => txctrl2, + txdiffctrl_in => TXDIFFCTRL, + txpcsreset_in(0) => TXPCSRESET, + txpmareset_in(0) => TXPMARESET, + txpostcursor_in => TXPOSTCURSOR, + txprecursor_in => TXPRECURSOR, + txusrclk_in(0) => TXUSRCLK, + txusrclk2_in(0) => TXUSRCLK, + drpdo_out => DRPDO, + drprdy_out(0) => DRPRDY, + gthtxn_out(0) => TXN, + gthtxp_out(0) => TXP, + gtpowergood_out => open, + rxbufstatus_out => open, + rxbyteisaligned_out(0) => RXBYTEISALIGNED, + rxbyterealign_out => open, + rxclkcorcnt_out => open, + rxcommadet_out => open, + rxctrl0_out => rxctrl0, + rxctrl1_out => rxctrl1, + rxctrl2_out => rxctrl2, + rxctrl3_out => rxctrl3, + rxoutclk_out(0) => RXOUTCLK, + rxpmaresetdone_out(0) => RXPMARESETDONE, + rxresetdone_out(0) => RXRESETDONE, + txoutclk_out(0) => TXOUTCLK, + txpmaresetdone_out(0) => TXPMARESETDONE, + txresetdone_out(0) => TXRESETDONE + ); + end generate generate_2gbps0_200mhz; + + generate_2gbps4_120mhz: + if LINE_RATE_KBPS = 2400000 and REFCLK_FREQ_HZ = 120000000 generate + begin + THE_GTH : gth_xcku_2gbps4_120mhz + port map ( + gtwiz_userclk_tx_active_in(0) => TXUSRCLK_ACTIVE, + gtwiz_userclk_rx_active_in(0) => RXUSRCLK_ACTIVE, + gtwiz_reset_clk_freerun_in(0) => CLK_100, + gtwiz_reset_all_in(0) => RESET_ALL, + gtwiz_reset_tx_pll_and_datapath_in(0) => '0', + gtwiz_reset_tx_datapath_in(0) => '0', + gtwiz_reset_rx_pll_and_datapath_in(0) => '0', + gtwiz_reset_rx_datapath_in(0) => '0', + gtwiz_reset_rx_cdr_stable_out => open, + gtwiz_reset_tx_done_out(0) => reset_tx_done_i, + gtwiz_reset_rx_done_out(0) => reset_rx_done_i, + gtwiz_userdata_tx_in => tx16data, + gtwiz_userdata_rx_out => rx16data, + drpaddr_in => DRPADDR, + drpclk_in(0) => DRPCLK, + drpdi_in => DRPDI, + drpen_in(0) => DRPEN, + drpwe_in(0) => DRPWE, + eyescanreset_in(0) => EYESCANRESET, + gthrxn_in(0) => RXN, + gthrxp_in(0) => RXP, + gtrefclk0_in(0) => GTREFCLK, + rx8b10ben_in => "1", + rxbufreset_in => "0", + rxcdrreset_in => "0", + rxcommadeten_in => "1", + rxlpmen_in(0) => RXLPMEN, + rxmcommaalignen_in => "1", + rxpcommaalignen_in => "1", + rxpcsreset_in(0) => RXPCSRESET, + rxpmareset_in(0) => RXPMARESET, + rxrate_in => RXRATE, + rxusrclk_in(0) => RXUSRCLK, + rxusrclk2_in(0) => RXUSRCLK, + tx8b10ben_in => "1", + txctrl0_in => txctrl0, + txctrl1_in => txctrl1, + txctrl2_in => txctrl2, + txdiffctrl_in => TXDIFFCTRL, + txpcsreset_in(0) => TXPCSRESET, + txpmareset_in(0) => TXPMARESET, + txpostcursor_in => TXPOSTCURSOR, + txprecursor_in => TXPRECURSOR, + txusrclk_in(0) => TXUSRCLK, + txusrclk2_in(0) => TXUSRCLK, + drpdo_out => DRPDO, + drprdy_out(0) => DRPRDY, + gthtxn_out(0) => TXN, + gthtxp_out(0) => TXP, + gtpowergood_out => open, + rxbufstatus_out => open, + rxbyteisaligned_out(0) => RXBYTEISALIGNED, + rxbyterealign_out => open, + rxclkcorcnt_out => open, + rxcommadet_out => open, + rxctrl0_out => rxctrl0, + rxctrl1_out => rxctrl1, + rxctrl2_out => rxctrl2, + rxctrl3_out => rxctrl3, + rxoutclk_out(0) => RXOUTCLK, + rxpmaresetdone_out(0) => RXPMARESETDONE, + rxresetdone_out(0) => RXRESETDONE, + txoutclk_out(0) => TXOUTCLK, + txpmaresetdone_out(0) => TXPMARESETDONE, + txresetdone_out(0) => TXRESETDONE + ); + end generate generate_2gbps4_120mhz; +end architecture behavioral; diff --git a/media_interfaces/xcku/gtwizard_options.txt b/media_interfaces/xcku/gtwizard_options.txt index 2a74596..5026bb0 100644 --- a/media_interfaces/xcku/gtwizard_options.txt +++ b/media_interfaces/xcku/gtwizard_options.txt @@ -1,16 +1,18 @@ Tab "Basic": Columns "Transmitter" and "Receiver": - Line rate (Gb/s): 2 - Actual Reference Clock (MHz): 100 + Line rate (Gb/s): 2 [2.4] + PLL type: CPLL + Actual Reference Clock (MHz): 100 [120] Decoding: 8B/10B User data width: 16 + Receiver Advanced: + Equalization mode: LPM Tab "Physical Resources": Channel table: Quad X0Y2 in SLR 0: GTHE3_CHANNEL_X0Y8: (X), MGTREFCLK0 - (for quad version also GTHE3_CHANNEL_X0Y9 -- GTHE3_CHANNEL_X0Y11) Tab "Optional Features": Receiver comma detection and alignment: @@ -25,20 +27,30 @@ Tab "Optional Features": Enable and select number of sequences to use: 2 Length of each sequence: - 2 + 4 Sequence 0, pattern 0: - 01010000 + 10111100, K character Sequence 0, pattern 1: + 11000101 + Sequence 0, pattern 2: 10111100, K character + Sequence 0, pattern 3: + 01010000 Sequence 1, pattern 0: - 11000101 + 10111100, K character Sequence 1, pattern 1: + 01010000 + Sequence 1, pattern 2: 10111100, K character + Sequence 1, pattern 3: + 01010000 Keep Idle Enable Tab "Structural Options" - Expose additional ports by functionality, for advanced feature usage + Simplify transceiver usage by organizing resources and helper blocks: + Include In-System IBERT core: Yes (include in Example Design) + Expose additional ports by functionality, for advanced feature usage: TX Initialization and Reset Ports txpcsreset_in txpmareset_in