From: hadeshyp Date: Mon, 23 Apr 2012 17:48:14 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=11d927654188ebd84930818979f3ef1cea4f2963;p=daqdocu.git *** empty log message *** --- diff --git a/trb3/DesignComponents.tex b/trb3/DesignComponents.tex new file mode 100644 index 0000000..dc02657 --- /dev/null +++ b/trb3/DesignComponents.tex @@ -0,0 +1 @@ +List all available components and design blocks here diff --git a/trb3/MultiTestAddOn.tex b/trb3/MultiTestAddOn.tex new file mode 100644 index 0000000..145dc5c --- /dev/null +++ b/trb3/MultiTestAddOn.tex @@ -0,0 +1,5 @@ + +\begin{itemize} + \item Schematics \href{http://hades-wiki.gsi.de/pub/DaqSlowControl/TDCReadoutBoardV3/MultiTestAddon1_alles.pdf}{MultiTestAddon1\_alles.pdf} + \item Pin-out file for the FPGA \href{cvs://:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_periph_multitest.lpf}{cvsroot/trb3/base/trb3\_periph\_multitest.lpf} +\end{itemize} \ No newline at end of file diff --git a/trb3/MvdAddOn.tex b/trb3/MvdAddOn.tex new file mode 100644 index 0000000..86d561c --- /dev/null +++ b/trb3/MvdAddOn.tex @@ -0,0 +1,5 @@ + +\begin{itemize} + \item Schematics %\url{http://hades-wiki.gsi.de/pub/DaqSlowControl/TDCReadoutBoardV3/MvdAddon1_alles.pdf} + \item Pin-out file for the FPGA %\url{:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_periph_mvd.lpf} +\end{itemize} diff --git a/trb3/SfpAddOn.tex b/trb3/SfpAddOn.tex new file mode 100644 index 0000000..1e76760 --- /dev/null +++ b/trb3/SfpAddOn.tex @@ -0,0 +1,6 @@ + + +\begin{itemize} + \item Schematics \href{http://hades-wiki.gsi.de/pub/DaqSlowControl/TDCReadoutBoardV3/SFP-Addon1_alles.pdf}{SFP-Addon1\_alles.pdf} + \item Pin-out file for the FPGA \href{cvs://:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_periph_sfp.lpf}{cvsroot/trb3/base/trb3\_periph\_sfp.lpf} +\end{itemize} diff --git a/trb3/TdcAddOn.tex b/trb3/TdcAddOn.tex new file mode 100644 index 0000000..dff82af --- /dev/null +++ b/trb3/TdcAddOn.tex @@ -0,0 +1,6 @@ + +\begin{itemize} + \item Schematics \href{http://hades-wiki.gsi.de/pub/DaqSlowControl/TDCReadoutBoardV3/ADDON1ADA1_alles.pdf}{ADDON1ADA1\_alles.pdf} + \item Pin-out file for the FPGA \href{cvs://:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_periph_ada.lpf}{cvsroot/trb3/base/trb3\_periph\_ada.lpf} +\end{itemize} + diff --git a/trb3/TdcBuildingBlocks.tex b/trb3/TdcBuildingBlocks.tex new file mode 100644 index 0000000..e69de29 diff --git a/trb3/TdcDataFormat.tex b/trb3/TdcDataFormat.tex new file mode 100644 index 0000000..e69de29 diff --git a/trb3/TdcFeatures.tex b/trb3/TdcFeatures.tex new file mode 100644 index 0000000..e69de29 diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex new file mode 100644 index 0000000..e69de29 diff --git a/trb3/Trb3ClockTriggerDistribution.tex b/trb3/Trb3ClockTriggerDistribution.tex new file mode 100644 index 0000000..7f7ee4d --- /dev/null +++ b/trb3/Trb3ClockTriggerDistribution.tex @@ -0,0 +1,7 @@ + +\begin{figure} + \centering + \includegraphics[width=.9\textheight,angle=90]{trb3_clock_distribution.png} + \caption{Clock and Trigger Distribution Network on TRB3.} + \label{trb3_clock_distribution} +\end{figure} diff --git a/trb3/Trb3KnownBugs.tex b/trb3/Trb3KnownBugs.tex new file mode 100644 index 0000000..8beb092 --- /dev/null +++ b/trb3/Trb3KnownBugs.tex @@ -0,0 +1,13 @@ +\begin{itemize} +\item The SFPs are missing LEDs - so no information about link status +\item The outputs of the CLK5410 chips are not independent: Two outputs share some settings - regarding this the connection is far from optimal, e.g. the clock to the serdes from FPGA1 is not independent from clock to GPLL input on FPGA4 etc. +\item SFP cages could have been distributed differently. Now, all TrbNet links (SFP1-4) are on one side and all GbE capable links on the other two (SFP5-8). Usually only few ports are in use, so a mix would be better. +\item TRB\_TO\_ADDON\_CLOCK is located on a port that does not support LVDS output +\item All pins connected to a DLL and PLL are Input only and can not be used as outputs! On the central FPGA, these are pins FS\_PE 4,5,7,8 and ADO\_TTL 23,26,30,46 +\item SPARE\_LINE between FPGA and AddOn-Connector are connected to Feedback input of PLL, not the normal input to PLL +\item On peripheral FPGA lines 8 and 9 of DQUR0 are input only - they are removed from the LPF for now. +\item Both GPLL inputs to peripheral FPGA are not usable - they are connected to Feedback input instead of normal input of PLL. They can still be used through normal routing, but source synchronous operation is not possible. +\item The JTAG Connector is wrong. The line labeled TDI is TDO and vice versa. +\item The 48V-to-6V converter gets quite hot without air-flow. When AddOns are mounted, the fan must be installed on the short side of the TRB, not on the long one. +\end{itemize} + diff --git a/trb3/main.tex b/trb3/main.tex new file mode 100755 index 0000000..f0bff2e --- /dev/null +++ b/trb3/main.tex @@ -0,0 +1,153 @@ +\documentclass[11pt,a4paper,twoside]{scrartcl} %twoside + +%Einstellungen der Seitenr?nder +\usepackage[left=3.5cm,right=3cm,top=2.5cm,bottom=2.5cm,includeheadfoot]{geometry} + +\usepackage[utf8]{inputenc} +\usepackage{amsfonts} +\usepackage[american]{babel} +\usepackage[T1]{fontenc} +\usepackage[pdftex]{graphicx} +\usepackage{pslatex} +\usepackage{xcolor} +\usepackage{array} +\usepackage{rotating} +\usepackage{multirow} +\usepackage{tabularx} +\usepackage{url} +\linespread{1.15} +\usepackage{booktabs} +\usepackage{longtable} +\usepackage{ltxtable} +\usepackage{upgreek} +\usepackage{listings} +\usepackage{scrtime} +\usepackage{lscape} +\usepackage{enumerate} + + +\definecolor{darkblue}{rgb}{.1,.1,.6} +\usepackage[linkbordercolor={0 0 0}, + pdfborder={0 0 0}, + bookmarks, + citecolor=blue, + linkcolor=darkblue, + colorlinks=true, + urlcolor=darkblue]{hyperref} +\usepackage{cite} + + +\newcolumntype{C}{>{\centering\arraybackslash}X} + +\usepackage{fancyhdr} +\pagestyle{headings}%{fancy} +\fancyhf{} +\fancyhead[R]{\nouppercase{\leftmark}} +\renewcommand{\headrulewidth}{0.5pt} +\fancyfoot[C]{\thepage} +%\renewcommand{\footrulewidth}{0} +%\usepackage[sort,square]{natbib} +%\usepackage{mathptmx} +%\usepackage{pslatex} + +\title{A Users Guide\\to the TRB3 \\and FPGA-TDC Based Platforms} +\date{\today ~-~\thistime} +\author{Grzegorz Korcyl, Ludwig Maier, Jan Michel, Marek Palka, \\Pawel Strzempek, Michael Traxler, Cahit Ugur} + + +\newcommand{\filename}[1]{\textit{#1}} +\newcommand{\portname}[1]{\textsc{#1}} +\newcommand{\genericname}[1]{\textsc{#1}} +\newcommand{\constname}[1]{\textsc{#1}} +\newcommand{\netname}[1]{\textsc{#1}} +\newcommand{\cmdname}[1]{\texttt{#1}} +\bibliographystyle{alpha} + +\usepackage{remreset} +\makeatletter\@removefromreset{footnote}{chapter}\makeatother + +% \lstset{ language = VHDL, +% numbers =left, +% stepnumber =1, +% frame =single, +% captionpos=b, +% breaklines=true +% basicstyle=\small, +% identifierstyle=\small, +% stringstyle=\small, +% numberstyle=\small, +% fontadjust=false} + +\begin{document} +\newcounter{line} +\newcounter{ct} + +\maketitle +\clearpage +\tableofcontents + + +\cleardoublepage +\part{Hardware} + \section{Measurements} + \subsection{FPGA I/O Performance} + + \section{TRB3 Platform} + \subsection{Known Bugs and Limitations} + \input{Trb3KnownBugs} + \subsection{Clock and Trigger Distribution} + \input{Trb3ClockTriggerDistribution} + + \clearpage + \section{AddOns} + \subsection{TDC AddOn} + \input{TdcAddOn} + \subsection{Multi-Test-AddOn} + \input{MultiTestAddOn} + \subsection{Hub AddOn} + \input{SfpAddOn} + \subsection{MVD AddOn} + \input{MvdAddOn} + \cleardoublepage + +\part{Design Components} + \input{DesignComponents} + \clearpage + \section{TDC} + \subsection{Features} + \input{TdcFeatures} + \subsection{Building Blocks} + \input{TdcBuildingBlocks} + \subsection{Data Format} + \input{TdcDataFormat} + \subsection{Slow Control Registers} + \input{TdcSlowControl} + + \clearpage + \section{GbE Data Read-out} + \subsection{Building Blocks} + \subsection{Slow Control Registers} + + \clearpage + \section{GbE Slow-Control} + \subsection{Building Blocks} + \subsection{Slow Control Registers} + + \clearpage + \section{uCTS} + \subsection{Features} + \subsection{Building Blocks} + \subsection{Slow Control Registers} + \cleardoublepage + + +\part{Experimental Setups and Configurations} + + + + + \cleardoublepage + +\bibliography{biblio} + +\end{document} diff --git a/trb3/trb3.kilepr b/trb3/trb3.kilepr new file mode 100644 index 0000000..0cffb3a --- /dev/null +++ b/trb3/trb3.kilepr @@ -0,0 +1,4 @@ +[General] +kileprversion=2 +kileversion=2.1.0 +name=trb3 diff --git a/trb3/trb3_clock_distribution.png b/trb3/trb3_clock_distribution.png new file mode 100644 index 0000000..c8ccf52 Binary files /dev/null and b/trb3/trb3_clock_distribution.png differ