From: Jan Michel Date: Wed, 14 Feb 2024 11:50:49 +0000 (+0100) Subject: few recent TDC updates X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=11e4db79e7bb294d86b328b1f77fb8ff8cb48d83;p=tdc.git few recent TDC updates - add enable signal to channels to reset edge fifo --- diff --git a/releases/tdc_v2.3.1/TDC.vhd b/releases/old/TDC.vhd similarity index 100% rename from releases/tdc_v2.3.1/TDC.vhd rename to releases/old/TDC.vhd diff --git a/releases/tdc_v2.3.1/Adder_304.ngo b/releases/old/tdc_v2.3.1/Adder_304.ngo similarity index 100% rename from releases/tdc_v2.3.1/Adder_304.ngo rename to releases/old/tdc_v2.3.1/Adder_304.ngo diff --git a/releases/tdc_v2.3.1/BusHandler.vhd b/releases/old/tdc_v2.3.1/BusHandler.vhd similarity index 100% rename from releases/tdc_v2.3.1/BusHandler.vhd rename to releases/old/tdc_v2.3.1/BusHandler.vhd diff --git a/releases/tdc_v2.3.1/BusHandler_record.vhd b/releases/old/tdc_v2.3.1/BusHandler_record.vhd similarity index 100% rename from releases/tdc_v2.3.1/BusHandler_record.vhd rename to releases/old/tdc_v2.3.1/BusHandler_record.vhd diff --git a/releases/tdc_v2.3.1/Channel.vhd b/releases/old/tdc_v2.3.1/Channel.vhd similarity index 100% rename from releases/tdc_v2.3.1/Channel.vhd rename to releases/old/tdc_v2.3.1/Channel.vhd diff --git a/releases/tdc_v2.3.1/Channel_200.vhd b/releases/old/tdc_v2.3.1/Channel_200.vhd similarity index 100% rename from releases/tdc_v2.3.1/Channel_200.vhd rename to releases/old/tdc_v2.3.1/Channel_200.vhd diff --git a/releases/tdc_v2.3.1/Channel_200.vhd.304 b/releases/old/tdc_v2.3.1/Channel_200.vhd.304 similarity index 100% rename from releases/tdc_v2.3.1/Channel_200.vhd.304 rename to releases/old/tdc_v2.3.1/Channel_200.vhd.304 diff --git a/releases/tdc_v2.3.1/Encoder_288_Bit.vhd b/releases/old/tdc_v2.3.1/Encoder_288_Bit.vhd similarity index 100% rename from releases/tdc_v2.3.1/Encoder_288_Bit.vhd rename to releases/old/tdc_v2.3.1/Encoder_288_Bit.vhd diff --git a/releases/tdc_v2.3.1/Encoder_304_Bit.vhd b/releases/old/tdc_v2.3.1/Encoder_304_Bit.vhd similarity index 100% rename from releases/tdc_v2.3.1/Encoder_304_Bit.vhd rename to releases/old/tdc_v2.3.1/Encoder_304_Bit.vhd diff --git a/releases/tdc_v2.3.1/LogicAnalyser.vhd b/releases/old/tdc_v2.3.1/LogicAnalyser.vhd similarity index 100% rename from releases/tdc_v2.3.1/LogicAnalyser.vhd rename to releases/old/tdc_v2.3.1/LogicAnalyser.vhd diff --git a/releases/tdc_v2.3.1/ROM_encoder_ecp3.vhd b/releases/old/tdc_v2.3.1/ROM_encoder_ecp3.vhd similarity index 100% rename from releases/tdc_v2.3.1/ROM_encoder_ecp3.vhd rename to releases/old/tdc_v2.3.1/ROM_encoder_ecp3.vhd diff --git a/releases/tdc_v2.3.1/ROM_encoder_ecp5.vhd b/releases/old/tdc_v2.3.1/ROM_encoder_ecp5.vhd similarity index 100% rename from releases/tdc_v2.3.1/ROM_encoder_ecp5.vhd rename to releases/old/tdc_v2.3.1/ROM_encoder_ecp5.vhd diff --git a/releases/tdc_v2.3.1/Readout.vhd b/releases/old/tdc_v2.3.1/Readout.vhd similarity index 100% rename from releases/tdc_v2.3.1/Readout.vhd rename to releases/old/tdc_v2.3.1/Readout.vhd diff --git a/releases/tdc_v2.3.1/Readout_record.vhd b/releases/old/tdc_v2.3.1/Readout_record.vhd similarity index 100% rename from releases/tdc_v2.3.1/Readout_record.vhd rename to releases/old/tdc_v2.3.1/Readout_record.vhd diff --git a/releases/tdc_v2.3.1/Readout_record_noDecode.vhd b/releases/old/tdc_v2.3.1/Readout_record_noDecode.vhd similarity index 100% rename from releases/tdc_v2.3.1/Readout_record_noDecode.vhd rename to releases/old/tdc_v2.3.1/Readout_record_noDecode.vhd diff --git a/releases/tdc_v2.3.1/ShiftRegisterSISO.vhd b/releases/old/tdc_v2.3.1/ShiftRegisterSISO.vhd similarity index 100% rename from releases/tdc_v2.3.1/ShiftRegisterSISO.vhd rename to releases/old/tdc_v2.3.1/ShiftRegisterSISO.vhd diff --git a/releases/tdc_v2.3.1/Stretcher.vhd b/releases/old/tdc_v2.3.1/Stretcher.vhd similarity index 100% rename from releases/tdc_v2.3.1/Stretcher.vhd rename to releases/old/tdc_v2.3.1/Stretcher.vhd diff --git a/releases/tdc_v2.3.1/Stretcher_A.vhd b/releases/old/tdc_v2.3.1/Stretcher_A.vhd similarity index 100% rename from releases/tdc_v2.3.1/Stretcher_A.vhd rename to releases/old/tdc_v2.3.1/Stretcher_A.vhd diff --git a/releases/tdc_v2.3.1/Stretcher_B.vhd b/releases/old/tdc_v2.3.1/Stretcher_B.vhd similarity index 100% rename from releases/tdc_v2.3.1/Stretcher_B.vhd rename to releases/old/tdc_v2.3.1/Stretcher_B.vhd diff --git a/releases/tdc_v2.3/TDC.vhd b/releases/old/tdc_v2.3.1/TDC.vhd similarity index 100% rename from releases/tdc_v2.3/TDC.vhd rename to releases/old/tdc_v2.3.1/TDC.vhd diff --git a/releases/tdc_v2.3.1/TDC_record.vhd b/releases/old/tdc_v2.3.1/TDC_record.vhd similarity index 100% rename from releases/tdc_v2.3.1/TDC_record.vhd rename to releases/old/tdc_v2.3.1/TDC_record.vhd diff --git a/releases/tdc_v2.3.1/TriggerHandler.vhd b/releases/old/tdc_v2.3.1/TriggerHandler.vhd similarity index 100% rename from releases/tdc_v2.3.1/TriggerHandler.vhd rename to releases/old/tdc_v2.3.1/TriggerHandler.vhd diff --git a/releases/tdc_v2.3.1/TriggerHandler_noDecode.vhd b/releases/old/tdc_v2.3.1/TriggerHandler_noDecode.vhd similarity index 100% rename from releases/tdc_v2.3.1/TriggerHandler_noDecode.vhd rename to releases/old/tdc_v2.3.1/TriggerHandler_noDecode.vhd diff --git a/releases/tdc_v2.3.1/bit_sync.vhd b/releases/old/tdc_v2.3.1/bit_sync.vhd similarity index 100% rename from releases/tdc_v2.3.1/bit_sync.vhd rename to releases/old/tdc_v2.3.1/bit_sync.vhd diff --git a/releases/tdc_v2.3.1/cbmtof.vhd b/releases/old/tdc_v2.3.1/cbmtof.vhd similarity index 100% rename from releases/tdc_v2.3.1/cbmtof.vhd rename to releases/old/tdc_v2.3.1/cbmtof.vhd diff --git a/releases/tdc_v2.3.1/dirich.vhd b/releases/old/tdc_v2.3.1/dirich.vhd similarity index 100% rename from releases/tdc_v2.3.1/dirich.vhd rename to releases/old/tdc_v2.3.1/dirich.vhd diff --git a/releases/tdc_v2.3.1/dirich_tdc_constraints.lpf b/releases/old/tdc_v2.3.1/dirich_tdc_constraints.lpf similarity index 100% rename from releases/tdc_v2.3.1/dirich_tdc_constraints.lpf rename to releases/old/tdc_v2.3.1/dirich_tdc_constraints.lpf diff --git a/releases/tdc_v2.3.1/dirich_trbnet_constraints.lpf b/releases/old/tdc_v2.3.1/dirich_trbnet_constraints.lpf similarity index 100% rename from releases/tdc_v2.3.1/dirich_trbnet_constraints.lpf rename to releases/old/tdc_v2.3.1/dirich_trbnet_constraints.lpf diff --git a/releases/tdc_v2.3.1/fallingEdgeDetect.vhd b/releases/old/tdc_v2.3.1/fallingEdgeDetect.vhd similarity index 100% rename from releases/tdc_v2.3.1/fallingEdgeDetect.vhd rename to releases/old/tdc_v2.3.1/fallingEdgeDetect.vhd diff --git a/releases/tdc_v2.3.1/hit_mux.vhd b/releases/old/tdc_v2.3.1/hit_mux.vhd similarity index 100% rename from releases/tdc_v2.3.1/hit_mux.vhd rename to releases/old/tdc_v2.3.1/hit_mux.vhd diff --git a/releases/tdc_v2.3.1/risingEdgeDetect.vhd b/releases/old/tdc_v2.3.1/risingEdgeDetect.vhd similarity index 100% rename from releases/tdc_v2.3.1/risingEdgeDetect.vhd rename to releases/old/tdc_v2.3.1/risingEdgeDetect.vhd diff --git a/releases/tdc_v2.3.1/rom_encoder/ecp3/ROM_encoder_3.ipx b/releases/old/tdc_v2.3.1/rom_encoder/ecp3/ROM_encoder_3.ipx similarity index 100% rename from releases/tdc_v2.3.1/rom_encoder/ecp3/ROM_encoder_3.ipx rename to releases/old/tdc_v2.3.1/rom_encoder/ecp3/ROM_encoder_3.ipx diff --git a/releases/tdc_v2.3.1/rom_encoder/ecp3/ROM_encoder_3.vhd b/releases/old/tdc_v2.3.1/rom_encoder/ecp3/ROM_encoder_3.vhd similarity index 100% rename from releases/tdc_v2.3.1/rom_encoder/ecp3/ROM_encoder_3.vhd rename to releases/old/tdc_v2.3.1/rom_encoder/ecp3/ROM_encoder_3.vhd diff --git a/releases/tdc_v2.3.1/rom_encoder/ecp5/ROM_encoder_3/ROM_encoder_3.sbx b/releases/old/tdc_v2.3.1/rom_encoder/ecp5/ROM_encoder_3/ROM_encoder_3.sbx similarity index 100% rename from releases/tdc_v2.3.1/rom_encoder/ecp5/ROM_encoder_3/ROM_encoder_3.sbx rename to releases/old/tdc_v2.3.1/rom_encoder/ecp5/ROM_encoder_3/ROM_encoder_3.sbx diff --git a/releases/tdc_v2.3.1/rom_encoder/ecp5/ROM_encoder_3/ROM_encoder_3.vhd b/releases/old/tdc_v2.3.1/rom_encoder/ecp5/ROM_encoder_3/ROM_encoder_3.vhd similarity index 100% rename from releases/tdc_v2.3.1/rom_encoder/ecp5/ROM_encoder_3/ROM_encoder_3.vhd rename to releases/old/tdc_v2.3.1/rom_encoder/ecp5/ROM_encoder_3/ROM_encoder_3.vhd diff --git a/releases/tdc_v2.3.1/rom_encoder/rom_encoder.mem b/releases/old/tdc_v2.3.1/rom_encoder/rom_encoder.mem similarity index 100% rename from releases/tdc_v2.3.1/rom_encoder/rom_encoder.mem rename to releases/old/tdc_v2.3.1/rom_encoder/rom_encoder.mem diff --git a/releases/tdc_v2.3.1/tdc_components.vhd b/releases/old/tdc_v2.3.1/tdc_components.vhd similarity index 100% rename from releases/tdc_v2.3.1/tdc_components.vhd rename to releases/old/tdc_v2.3.1/tdc_components.vhd diff --git a/releases/tdc_v2.3.1/tdc_constraints_64.lpf b/releases/old/tdc_v2.3.1/tdc_constraints_64.lpf similarity index 100% rename from releases/tdc_v2.3.1/tdc_constraints_64.lpf rename to releases/old/tdc_v2.3.1/tdc_constraints_64.lpf diff --git a/releases/tdc_v2.3.1/tdc_version.vhd b/releases/old/tdc_v2.3.1/tdc_version.vhd similarity index 100% rename from releases/tdc_v2.3.1/tdc_version.vhd rename to releases/old/tdc_v2.3.1/tdc_version.vhd diff --git a/releases/tdc_v2.3.1/trb3_periph_32PinAddOn.vhd b/releases/old/tdc_v2.3.1/trb3_periph_32PinAddOn.vhd similarity index 100% rename from releases/tdc_v2.3.1/trb3_periph_32PinAddOn.vhd rename to releases/old/tdc_v2.3.1/trb3_periph_32PinAddOn.vhd diff --git a/releases/tdc_v2.3.1/trb3_periph_ADA.vhd b/releases/old/tdc_v2.3.1/trb3_periph_ADA.vhd similarity index 100% rename from releases/tdc_v2.3.1/trb3_periph_ADA.vhd rename to releases/old/tdc_v2.3.1/trb3_periph_ADA.vhd diff --git a/releases/tdc_v2.3.1/trb3_periph_gpin.vhd b/releases/old/tdc_v2.3.1/trb3_periph_gpin.vhd similarity index 100% rename from releases/tdc_v2.3.1/trb3_periph_gpin.vhd rename to releases/old/tdc_v2.3.1/trb3_periph_gpin.vhd diff --git a/releases/tdc_v2.3.1/trb3_periph_padiwa.vhd b/releases/old/tdc_v2.3.1/trb3_periph_padiwa.vhd similarity index 100% rename from releases/tdc_v2.3.1/trb3_periph_padiwa.vhd rename to releases/old/tdc_v2.3.1/trb3_periph_padiwa.vhd diff --git a/releases/tdc_v2.3.1/trbnet_constraints.lpf b/releases/old/tdc_v2.3.1/trbnet_constraints.lpf similarity index 100% rename from releases/tdc_v2.3.1/trbnet_constraints.lpf rename to releases/old/tdc_v2.3.1/trbnet_constraints.lpf diff --git a/releases/tdc_v2.3.1/trbnet_constraints_dirich.lpf b/releases/old/tdc_v2.3.1/trbnet_constraints_dirich.lpf similarity index 100% rename from releases/tdc_v2.3.1/trbnet_constraints_dirich.lpf rename to releases/old/tdc_v2.3.1/trbnet_constraints_dirich.lpf diff --git a/releases/tdc_v2.3.1/unimportant_lines_constraints.lpf b/releases/old/tdc_v2.3.1/unimportant_lines_constraints.lpf similarity index 100% rename from releases/tdc_v2.3.1/unimportant_lines_constraints.lpf rename to releases/old/tdc_v2.3.1/unimportant_lines_constraints.lpf diff --git a/releases/tdc_v2.3.1/up_counter.vhd b/releases/old/tdc_v2.3.1/up_counter.vhd similarity index 100% rename from releases/tdc_v2.3.1/up_counter.vhd rename to releases/old/tdc_v2.3.1/up_counter.vhd diff --git a/releases/tdc_v2.3/Channel.vhd b/releases/tdc_v2.3/Channel.vhd index f29d995..0ad37d7 100644 --- a/releases/tdc_v2.3/Channel.vhd +++ b/releases/tdc_v2.3/Channel.vhd @@ -41,7 +41,8 @@ entity Channel is ENCODER_START_NUMBER : out std_logic_vector(23 downto 0) := (others => '0'); ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0) := (others => '0'); FIFO_WRITE_NUMBER : out std_logic_vector(23 downto 0) := (others => '0'); --- + CHANNEL_ENABLE_IN : in std_logic; + Channel_200_DEBUG_OUT : out std_logic_vector(31 downto 0); Channel_DEBUG_OUT : out std_logic_vector(31 downto 0) ); @@ -124,6 +125,7 @@ begin ENCODER_START_OUT => encoder_start, ENCODER_FINISHED_OUT => encoder_finished, FIFO_WRITE_OUT => fifo_write, + CHANNEL_ENABLE_IN => CHANNEL_ENABLE_IN, CHANNEL_200_DEBUG_OUT => channel_200_debug); Buffer_128 : if RING_BUFFER_SIZE = 3 or RING_BUFFER_SIZE = 7 generate diff --git a/releases/tdc_v2.3/Channel_200.vhd b/releases/tdc_v2.3/Channel_200.vhd index 9bca469..2fb52af 100644 --- a/releases/tdc_v2.3/Channel_200.vhd +++ b/releases/tdc_v2.3/Channel_200.vhd @@ -49,6 +49,7 @@ entity Channel_200 is ENCODER_START_OUT : out std_logic; ENCODER_FINISHED_OUT : out std_logic; FIFO_WRITE_OUT : out std_logic; + CHANNEL_ENABLE_IN : in std_logic; CHANNEL_200_DEBUG_OUT : out std_logic_vector(31 downto 0) ); @@ -284,6 +285,10 @@ begin -- Channel_200 rd_ptr <= rd_ptr + 1; end if; end if; + if CHANNEL_ENABLE_IN = '0' then + rd_ptr <= 0; + wr_ptr <= 0; + end if; end if; end process EdgeTypeCapture; end generate isChannelEdge; diff --git a/releases/tdc_v2.3/TDC_record.vhd b/releases/tdc_v2.3/TDC_record.vhd index d0c59be..d9f3652 100644 --- a/releases/tdc_v2.3/TDC_record.vhd +++ b/releases/tdc_v2.3/TDC_record.vhd @@ -307,7 +307,7 @@ begin The_Stretcher : entity work.Stretcher generic map ( CHANNEL => CHANNEL_NUMBER-1, - DEPTH => 4+(FPGA_TYPE/4)) --4 for ECP3, 5 for ECP5 + DEPTH => 4+1*(FPGA_TYPE/4)) --3 for ECP3, 5 for ECP5 port map ( PULSE_IN => edge_falling(CHANNEL_NUMBER-1 downto 1), PULSE_OUT => edge_falling_d(CHANNEL_NUMBER-1 downto 1)); @@ -361,9 +361,12 @@ begin end generate GEN_HitBlock; GEN_hit_mux : for i in 1 to CHANNEL_NUMBER-1 generate + signal real_enable : std_logic_vector(CHANNEL_NUMBER downto 0); + begin + real_enable(i) <= ch_en(i);-- or calibration_on; hit_mux_ch : hit_mux port map ( - CH_EN_IN => ch_en(i), + CH_EN_IN => real_enable(i), CALIBRATION_EN_IN => '0', HIT_CALIBRATION_IN => '0', HIT_PHYSICAL_IN => hit_latch(i), @@ -423,8 +426,10 @@ begin ENCODER_START_NUMBER => ch_encoder_start_number(0), ENCODER_FINISHED_NUMBER => ch_encoder_finished_number(0), FIFO_WRITE_NUMBER => ch_fifo_write_number(0), + CHANNEL_ENABLE_IN => '1', Channel_200_DEBUG_OUT => ch_200_debug(0), - Channel_DEBUG_OUT => ch_debug(0)); + Channel_DEBUG_OUT => ch_debug(0) + ); -- TDC Channels GEN_Channels : for i in 1 to CHANNEL_NUMBER-1 generate @@ -458,8 +463,10 @@ begin ENCODER_START_NUMBER => ch_encoder_start_number(i), ENCODER_FINISHED_NUMBER => ch_encoder_finished_number(i), FIFO_WRITE_NUMBER => ch_fifo_write_number(i), + CHANNEL_ENABLE_IN => ch_en(i), Channel_200_DEBUG_OUT => ch_200_debug(i), - Channel_DEBUG_OUT => ch_debug(i)); + Channel_DEBUG_OUT => ch_debug(i) + ); end generate GEN_Channels; -- ch_data(CHANNEL_NUMBER) <= (others => '1'); diff --git a/releases/tdc_v2.3/tdc_components.vhd b/releases/tdc_v2.3/tdc_components.vhd index d637ed9..0387de6 100644 --- a/releases/tdc_v2.3/tdc_components.vhd +++ b/releases/tdc_v2.3/tdc_components.vhd @@ -142,6 +142,7 @@ package tdc_components is ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0); FIFO_WRITE_NUMBER : out std_logic_vector(23 downto 0); + CHANNEL_ENABLE_IN : in std_logic; Channel_200_DEBUG_OUT : out std_logic_vector(31 downto 0); Channel_DEBUG_OUT : out std_logic_vector(31 downto 0)); end component; @@ -171,6 +172,7 @@ package tdc_components is ENCODER_START_OUT : out std_logic; ENCODER_FINISHED_OUT : out std_logic; FIFO_WRITE_OUT : out std_logic; + CHANNEL_ENABLE_IN : in std_logic; CHANNEL_200_DEBUG_OUT : out std_logic_vector(31 downto 0)); end component Channel_200; diff --git a/releases/tdc_v2.3/tdc_constraints_64.lpf b/releases/tdc_v2.3/tdc_constraints_64.lpf index ff6c89a..5bda2e8 120000 --- a/releases/tdc_v2.3/tdc_constraints_64.lpf +++ b/releases/tdc_v2.3/tdc_constraints_64.lpf @@ -1 +1 @@ -tdc_constraints_64_orig.lpf \ No newline at end of file +tdc_constraints_64_rearranged.lpf \ No newline at end of file diff --git a/releases/tdc_v2.3/tdc_constraints_64_rearranged.lpf b/releases/tdc_v2.3/tdc_constraints_64_rearranged.lpf index 62ee907..9445caa 100644 --- a/releases/tdc_v2.3/tdc_constraints_64_rearranged.lpf +++ b/releases/tdc_v2.3/tdc_constraints_64_rearranged.lpf @@ -1129,11 +1129,11 @@ LOCATE UGROUP "EF_X3Y7" SITE "R105C131D" ; # X3Y7 UGROUP "Stretcher_A" BBOX 6 8 BLKNAME THE_TDC/gen_double_withStretcher.The_Stretcher/Stretcher_A_1 ; -LOCATE UGROUP "Stretcher_A" SITE "R2C174D"; +LOCATE UGROUP "Stretcher_A" SITE "R2C154D"; UGROUP "Stretcher_B" BBOX 6 8 BLKNAME THE_TDC/gen_double_withStretcher.The_Stretcher/Stretcher_B_1 ; -LOCATE UGROUP "Stretcher_B" SITE "R2C2D"; +LOCATE UGROUP "Stretcher_B" SITE "R2C22D"; diff --git a/releases/tdc_v2.3/trb3_periph_ADA.vhd b/releases/tdc_v2.3/trb3_periph_ADA.vhd index 8f373eb..a2062a5 100644 --- a/releases/tdc_v2.3/trb3_periph_ADA.vhd +++ b/releases/tdc_v2.3/trb3_periph_ADA.vhd @@ -35,7 +35,9 @@ entity trb3_periph_ADA is --Bit 2/3 output, serial link TX active --Connection to ADA AddOn -- SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only - INP : in std_logic_vector(63 downto 0); + ADDON_TEST : out std_logic_vector(4 downto 1); + ADDON_TEMP : inout std_logic_vector(2 downto 1); + INP : in std_logic_vector(63 downto 0); --DAC DAC_IN_L_SDI : in std_logic; DAC_OUT_L_SDO : out std_logic; @@ -127,8 +129,8 @@ architecture trb3_periph_ADA_arch of trb3_periph_ADA is --Slow Control channel signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal ctrlbus_rx, bustdc_rx, bustools_rx, bus_master_out, bustrigger_rx : CTRLBUS_RX; - signal ctrlbus_tx, bustdc_tx, bustools_tx, bus_master_in, bustrigger_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bustools_rx, bus_master_out, busfee_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustdc_tx, bustools_tx, bus_master_in, busfee_tx : CTRLBUS_TX; signal bus_master_active : std_logic; signal timer : TIMERS; signal lcd_data : std_logic_vector(511 downto 0); @@ -288,7 +290,7 @@ pll_calibration: entity work.pll_in125_out33 generic map( PORT_NUMBER => 3, PORT_ADDRESSES => (0 => x"d000", 1 => x"c000", 2 => x"e000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 12, 2 => 12, others => 0), + PORT_ADDR_MASK => (0 => 12, 1 => 12, 2 => 5, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -300,10 +302,10 @@ pll_calibration: entity work.pll_in125_out33 BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED BUS_RX(1) => bustdc_rx, --TDC config - BUS_RX(2) => bustrigger_rx, + BUS_RX(2) => busfee_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bustdc_tx, - BUS_TX(2) => bustrigger_tx, + BUS_TX(2) => busfee_tx, STAT_DEBUG => open ); @@ -354,29 +356,50 @@ pll_calibration: entity work.pll_in125_out33 ); -THE_TRIGGER_LOGIC : entity work.trigger_logic - generic map( - INPUTS => 24, - OUTPUTS => 8 - ) - port map( - CLK => clk_100_i, - RESET => reset_i, +--THE_TRIGGER_LOGIC : entity work.trigger_logic + --generic map( + --INPUTS => 24, + --OUTPUTS => 8 + --) + --port map( + --CLK => clk_100_i, + --RESET => reset_i, - --Slowcontrol - BUS_RX => bustrigger_rx, - BUS_TX => bustrigger_tx, + ----Slowcontrol + --BUS_RX => bustrigger_rx, + --BUS_TX => bustrigger_tx, - --Inputs and Outputs - INPUT => hit_in_i(24 downto 1), - OUTPUT => triggerlogic_out(7 downto 0) - ); - FPGA5_COMM(10 downto 7) <= trig_gen_out_i or triggerlogic_out(3 downto 0); + ----Inputs and Outputs + --INPUT => hit_in_i(24 downto 1), + --OUTPUT => triggerlogic_out(7 downto 0) + --); + --FPGA5_COMM(10 downto 7) <= trig_gen_out_i or triggerlogic_out(3 downto 0); - --FPGA5_COMM(10 downto 7) <= trig_gen_out_i; + FPGA5_COMM(10 downto 7) <= trig_gen_out_i; +--------------------------------------------------------------------------- +-- FEE test signals and temperature sensors +--------------------------------------------------------------------------- +gen_fee_test : if USE_TEST_SIGNALS = 1 generate + THE_FEE_TEST : entity work.fee_signals + port map( + CLK => clk_100_i, + RESET => reset_i, + BUS_RX => busfee_rx, + BUS_TX => busfee_tx, + TEST_SIG_OUT(3 downto 0) => ADDON_TEST, + FEETEMP(1 downto 0) => ADDON_TEMP + ); +end generate; + +gen_no_fee_test : if USE_TEST_SIGNALS = 0 generate + busfee_tx.unknown <= busfee_rx.write or busfee_rx.read; + busfee_tx.ack <= '0'; + busfee_tx.nack <= '0'; +end generate; + --------------------------------------------------------------------------- -- Feature I/O --------------------------------------------------------------------------- diff --git a/releases/tdc_v2.3/unimportant_lines_constraints.lpf b/releases/tdc_v2.3/unimportant_lines_constraints.lpf index 052a624..e1950c8 100644 --- a/releases/tdc_v2.3/unimportant_lines_constraints.lpf +++ b/releases/tdc_v2.3/unimportant_lines_constraints.lpf @@ -3,6 +3,7 @@ ############################################################################# BLOCK PATH FROM CLKNET "THE_TDC/edge_rising[*]"; BLOCK NET "THE_TDC/hit_in_s*"; +BLOCK NET "THE_TDC/GEN*hit_in_s*"; BLOCK PATH FROM CLKNET "THE_TDC/hit_in_s*"; BLOCK PATH FROM CLKNET "THE_TDC/*hit_in_s*" ; @@ -36,10 +37,12 @@ MULTICYCLE FROM CELL "THE_TDC/hit_edge[*]" TO CELL "THE_TDC/GEN_Channels.*.Chann MULTICYCLE TO CELL "THE_TDC/edge_rising_100_r[*]" 4 x; MULTICYCLE FROM CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/ringBuffer_almost_full_flag*" TO CELL "THE_TDC/TheReadout/data_out_r[*]" 2 x; + #MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*" 4x; #MULTICYCLE TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/SimAdderNo.FC/FF*" 4x; #MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo5.FC/FF*" 4x; #MULTICYCLE TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/SimAdderNo5.FC/FF*" 4x; +MULTICYCLE FROM CELL "THE_TDC/calibration_on" 4x; MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/CHANNEL_200_DEBUG_OUT_1[*]" 4x; MULTICYCLE TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/CHANNEL_200_DEBUG_OUT_1[*]" 4x;