From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Mon, 6 Dec 2021 15:20:17 +0000 (+0100)
Subject: fixed missing TX_DLM signal
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=127e422a31730e485ed3a2fd7488960000b54d87;p=trbnet.git

fixed missing TX_DLM signal
---

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 2520265..427e944 100644
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -122,7 +122,6 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is
   signal tx_ref_clk_i       : std_logic;
 
   signal tx_dlm_word_i      : std_logic_vector(7 downto 0);
-  signal tx_dlm_i           : std_logic;
 
   signal tx_rst_word_i      : std_logic_vector(4*8-1 downto 0);
   signal tx_rst_i           : std_logic_vector(3 downto 0);
@@ -137,6 +136,9 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is
   signal link_rx_ready_i    : std_logic_vector(3 downto 0);
   signal tx_clk_avail_sel   : std_logic;
   
+  signal word_sync_i        : std_logic_vector(3 downto 0);
+  signal word_sync_sel      : std_logic;
+  
   signal quad_mode : integer range 0 to 100;
 
 begin
@@ -210,7 +212,18 @@ begin
                       '1';
 
   TX_CLK_AVAIL_OUT <= tx_clk_avail_sel;
-  
+
+-------------------------------------------------      
+-- byte/word alignment
+-------------------------------------------------      
+  word_sync_sel <= word_sync_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
+                   word_sync_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
+                   word_sync_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
+                   word_sync_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
+                   '1';
+
+  WORD_SYNC_OUT <= word_sync_sel;
+
 -------------------------------------------------      
 -- reset komma receive
 -- output only if a slave port is available in QUAD
@@ -424,13 +437,13 @@ gen_control : for i in 0 to 3 generate
         RX_K_IN            => rx_k(i),
         -- ports for synchronous operation
         WORD_SYNC_IN       => WORD_SYNC_IN,
-        WORD_SYNC_OUT      => WORD_SYNC_OUT, 
+        WORD_SYNC_OUT      => word_sync_i(i), 
         GLOBAL_RESET_IN    => GLOBAL_RESET_IN,
         GLOBAL_RESET_OUT   => global_reset_i(i),
         LINK_TX_READY_IN   => LINK_TX_READY_IN,
         LINK_RX_READY_OUT  => link_rx_ready_i(i),
         -- komma operation
-        TX_DLM_IN          => tx_dlm_i,
+        TX_DLM_IN          => TX_DLM_IN,
         TX_DLM_WORD_IN     => tx_dlm_word_i,
         TX_RST_IN          => tx_rst_i(i),
         TX_RST_WORD_IN     => tx_rst_word_i(i*8+7 downto i*8),
@@ -498,10 +511,10 @@ end generate;
   
 --  DEBUG_OUT <= debug_i(3*32+31 downto 3*32);
   DEBUG_OUT(11 downto 0)  <= debug_i(3*32+11 downto 3*32);
-  DEBUG_OUT(12)           <= wa_read_i;
-  DEBUG_OUT(13)           <= tx_clk_avail_sel;
-  DEBUG_OUT(14)           <= GLOBAL_RESET_IN;
-  DEBUG_OUT(15)           <= '0';
+  DEBUG_OUT(12)           <= debug_tx_control_i(3*32+4);
+  DEBUG_OUT(13)           <= debug_tx_control_i(3*32+5);
+  DEBUG_OUT(14)           <= debug_tx_control_i(3*32+30);
+  DEBUG_OUT(15)           <= debug_tx_control_i(3*32+31);
   DEBUG_OUT(31 downto 16) <= debug_i(3*32+31 downto 3*32+16);
   
 end architecture;