From: Peter Lemmens Date: Wed, 25 Feb 2015 13:48:38 +0000 (+0100) Subject: Cu trb + fiber soda working. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=134f35344727df79626905395bc878457ec9da0d;p=soda.git Cu trb + fiber soda working. Basic functionality: superbursts are transmitted from quad-source to a hub and down to a client. Proper replies are generated and received. Calibration from quad-source to hub works, from hub to client does not work yet. ToDo: debug hub2client calibration. Check 'dead-channel' detection/registration. --- diff --git a/SODA_addressmap b/SODA_addressmap index 673248b..28b89ba 100644 --- a/SODA_addressmap +++ b/SODA_addressmap @@ -56,6 +56,15 @@ DEBUG_STATUS(2) <= CLK_EN; DEBUG_STATUS(1) <= CLEAR; DEBUG_STATUS(0) <= RESET; - +------------------------------------------------------------------- +constant K_IDLE : std_logic_vector(7 downto 0) := x"BC"; +constant D_IDLE0 : std_logic_vector(7 downto 0) := x"C5"; +constant D_IDLE1 : std_logic_vector(7 downto 0) := x"50"; +constant K_SOP : std_logic_vector(7 downto 0) := x"FB"; +constant K_EOP : std_logic_vector(7 downto 0) := x"FD"; +constant K_BGN : std_logic_vector(7 downto 0) := x"1C"; +constant K_REQ : std_logic_vector(7 downto 0) := x"7C"; +constant K_RST : std_logic_vector(7 downto 0) := x"FE"; +constant K_DLM : std_logic_vector(7 downto 0) := x"DC"; diff --git a/SODA_quadsource_addressmap b/SODA_quadsource_addressmap new file mode 100644 index 0000000..5a788cb --- /dev/null +++ b/SODA_quadsource_addressmap @@ -0,0 +1,70 @@ +SODA_QUAD_SOURCE (0xF358) ++++++++++++++++++++++++++ +WRITE_REG: + +BE00 soda_cmd_word_S +BE01 CTRL_STATUS_register_i[0](15..0) +BE02 CTRL_STATUS_register_i[1](15..0) +BE03 CTRL_STATUS_register_i[2](15..0) +BE04 CTRL_STATUS_register_i[3](15..0) + +READ_REG: + +BE00 soda_cmd_word_S +BE01 super_burst_nr_S +BE04 calib_register_S[0] +BE05 calib_register_S[1] +BE06 calib_register_S[2] +BE07 calib_register_S[3] +BE08 CTRL_STATUS_register_i[0] +BE09 CTRL_STATUS_register_i[0] +BE10 CTRL_STATUS_register_i[0] +BE11 CTRL_STATUS_register_i[0] + +control(read & write): +CTRL_STATUS_register_i[3..0] : LEDs +CTRL_STATUS_register_i[8] : dead_channel +CTRL_STATUS_register_i[15] : reset errors +status(read-only): +CTRL_STATUS_register_i[17] : timeout-error +CTRL_STATUS_register_i[18] : downstream-error +CTRL_STATUS_register_i[31] : report error + + +SODA_CLIENT (0xF356) +++++++++++++++++++++ +WRITE_REG: + +BE00 LEDregister_i + +READ_REG: + +BE00 soda_cmd_word_S +BE01 super_burst_nr_S +BE02 LEDregister_i +BE03 Debug_status +BE04 Debug_RX_count +BE05 Debug_TX_count +BE06 Debug_SOS_count +BE07 Debug_CMD_count + + + + +DEBUG_STATUS(31) <= send_link_reset_i when rising_edge(SYSCLK); +DEBUG_STATUS(30) <= '0'; +DEBUG_STATUS(29) <= internal_make_link_reset_out when rising_edge(SYSCLK); +DEBUG_STATUS(28) <= '0'; +DEBUG_STATUS(27) <= '0'; +DEBUG_STATUS(26) <= rx_allow; +DEBUG_STATUS(25) <= tx_allow; +DEBUG_STATUS(24:20) <= (others => '0'); +DEBUG_STATUS(19:16) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7"; +DEBUG_STATUS(15:3) <= (others => '0'); +DEBUG_STATUS(2) <= CLK_EN; +DEBUG_STATUS(1) <= CLEAR; +DEBUG_STATUS(0) <= RESET; + + + + diff --git a/code/Cu_trb3_periph_soda_client.vhd b/code/Cu_trb3_periph_soda_client.vhd index fa43d4f..b10a703 100644 --- a/code/Cu_trb3_periph_soda_client.vhd +++ b/code/Cu_trb3_periph_soda_client.vhd @@ -217,7 +217,7 @@ THE_MAIN_PLL : pll_in200_out100 --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) --------------------------------------------------------------------------- - TRB_MEDIA_AND_SODA_SYNC_UPLINK : Cu_trb_net16_soda_sync_ecp3_sfp + TRB_MEDIA_AND_SODA_SYNC_UPLINK : Cu_trb_net16_soda_syncUP_ecp3_sfp port map( OSCCLK => clk_200_osc, SYSCLK => clk_100_osc, @@ -252,10 +252,10 @@ THE_MAIN_PLL : pll_in200_out100 SYNC_RXD_N_IN => SERDES_ADDON_RX(5), SYNC_TXD_P_OUT => SERDES_ADDON_TX(4), SYNC_TXD_N_OUT => SERDES_ADDON_TX(5), - SYNC_DLM_IN => soda_tx_dlm_S, - SYNC_DLM_WORD_IN => soda_tx_dlm_word_S, - SYNC_DLM_OUT => soda_rx_dlm_S, - SYNC_DLM_WORD_OUT => soda_rx_dlm_word_S, + SYNC_TX_DLM_IN => soda_tx_dlm_S, + SYNC_TX_DLM_WORD_IN => soda_tx_dlm_word_S, + SYNC_RX_DLM_OUT => soda_rx_dlm_S, + SYNC_RX_DLM_WORD_OUT => soda_rx_dlm_word_S, SYNC_PRSNT_N_IN => SFP_MOD0(3), SYNC_LOS_IN => SFP_LOS(3), SYNC_TXDIS_OUT => sfp_txdis_S(3), diff --git a/code/Cu_trb3_periph_soda_hub.vhd b/code/Cu_trb3_periph_soda_hub.vhd new file mode 100644 index 0000000..c0ec61c --- /dev/null +++ b/code/Cu_trb3_periph_soda_hub.vhd @@ -0,0 +1,706 @@ +--------------- +-- TOP LEVEL -- +--------------- +-- TAB=3 !! + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.trb3_components.all; +use work.soda_components.all; +use work.med_sync_define.all; +use work.version.all; + +entity Cu_trb3_periph_soda_hub is + generic( + SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests! + USE_125_MHZ : integer := c_NO; + CLOCK_FREQUENCY : integer := 100; + NUM_INTERFACES : integer := 6 + 1 + ); + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + --serdes I/O - connect as you like, no real use + CU_SERDES_TX : out std_logic_vector(3 downto 0); + CU_SERDES_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(15 downto 0); + SERDES_ADDON_RX : in std_logic_vector(15 downto 0); + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --others yet undefined + --Connection to AddOn + LED_LINKOK : out std_logic_vector(6 downto 1); + LED_RX : out std_logic_vector(6 downto 1); + LED_TX : out std_logic_vector(6 downto 1); + SFP_MOD0 : in std_logic_vector(6 downto 1); + SFP_TXDIS : out std_logic_vector(6 downto 1); + SFP_LOS : in std_logic_vector(6 downto 1); + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); +end Cu_trb3_periph_soda_hub; + +architecture Cu_trb3_periph_soda_hub_arch of Cu_trb3_periph_soda_hub is + -- Constants + constant REGIO_NUM_STAT_REGS : integer := 0; + constant REGIO_NUM_CTRL_REGS : integer := 2; + + constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa + + --Clock / Reset + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal downlink_clear : std_logic; + signal downlink_reset : std_logic; + signal GSR_N : std_logic; + + signal clk_100_osc : std_logic; + signal clk_200_osc : std_logic; + signal time_counter : unsigned(31 downto 0); + + --Media Interface + signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0); + signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0); + signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0); + signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); + signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); + signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0); + signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); + signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal my_address : std_logic_vector (15 downto 0); + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(8 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_dataready_out : std_logic; + signal spimem_no_more_data_out : std_logic; + signal spimem_unknown_addr_out : std_logic; + signal spimem_write_ack_out : std_logic; + + --Cu media interface + signal sci1_ack : std_logic; + signal sci1_write : std_logic; + signal sci1_read : std_logic; + signal sci1_data_in : std_logic_vector(7 downto 0); + signal sci1_data_out : std_logic_vector(7 downto 0); + signal sci1_addr : std_logic_vector(8 downto 0); + signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1'); + + signal sci2_ack : std_logic; + signal sci2_nack : std_logic; + signal sci2_write : std_logic; + signal sci2_read : std_logic; + signal sci2_data_in : std_logic_vector(7 downto 0); + signal sci2_data_out : std_logic_vector(7 downto 0); + signal sci2_addr : std_logic_vector(8 downto 0); + + + --SODA + signal soda_rxup_full_clk : std_logic; + signal soda_rxup_half_clk : std_logic; + signal soda_txup_full_clk : std_logic; + signal soda_txup_half_clk : std_logic; + + signal soda_txup_dlm_S : std_logic; + signal soda_txup_dlm_word_S : std_logic_vector(7 downto 0); + signal soda_rxup_dlm_S : std_logic; + signal soda_rxup_dlm_word_S : std_logic_vector(7 downto 0); + signal soda_txup_dlm_preview_S : std_logic; + signal soda_uplink_phase_S : std_logic; + + --SODA downlink + signal soda_rxdn_half_clk : t_HUB_BIT; + signal soda_rxdn_full_clk : t_HUB_BIT; + signal soda_txdn_half_clk : t_HUB_BIT; + signal soda_txdn_full_clk : t_HUB_BIT; + + signal soda_txdn_dlm_S : t_HUB_BIT; + signal soda_txdn_dlm_word_S : t_HUB_BYTE; + signal soda_rxdn_dlm_S : t_HUB_BIT; + signal soda_rxdn_dlm_word_S : t_HUB_BYTE; + signal soda_txdn_dlm_preview_S : t_HUB_BIT; + signal soda_dnlink_phase_S : t_HUB_BIT; + + -- SODA slow controll + signal soda_ack : std_logic; + signal soda_write : std_logic; + signal soda_read : std_logic; + signal soda_data_in : std_logic_vector(31 downto 0); + signal soda_data_out : std_logic_vector(31 downto 0); + signal soda_addr : std_logic_vector(3 downto 0); + signal soda_leds : std_logic_vector(3 downto 0); + + signal link_debug_in_S : std_logic_vector(31 downto 0); + signal general_reset_i : std_logic := '1'; + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + + LED_RX <= (others => '0'); -- otherwise it is floating + LED_TX <= (others => '0'); -- otherwise it is floating + LED_LINKOK <= (others => '0'); -- otherwise it is floating + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_osc, --clk_raw_internal, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_osc, --rx_half_clk, PL 111114, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + +------------------------------------------------------------------------- +-- Clock Handling +------------------------------------------------------------------------- +THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_100_osc, + CLKOK => clk_200_osc, + LOCK => pll_lock + ); + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- + TRB_MEDIA_AND_SODA_SYNC_UPLINK : Cu_trb_net16_soda_syncUP_ecp3_sfp + port map( + OSCCLK => clk_200_osc, + SYSCLK => clk_100_osc, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MED_DATA_IN => med_data_out(15 downto 0), + MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0), + MED_DATAREADY_IN => med_dataready_out(0), + MED_READ_OUT => med_read_in(0), + MED_DATA_OUT => med_data_in(15 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0), + MED_DATAREADY_OUT => med_dataready_in(0), + MED_READ_IN => med_read_out(0), + + --Copper SFP Connection + CU_RXD_P_IN => CU_SERDES_RX(0), + CU_RXD_N_IN => CU_SERDES_RX(1), + CU_TXD_P_OUT => CU_SERDES_TX(0), + CU_TXD_N_OUT => CU_SERDES_TX(1), + CU_PRSNT_N_IN => FPGA5_COMM(0), + CU_LOS_IN => FPGA5_COMM(0), + CU_TXDIS_OUT => FPGA5_COMM(2), + + -- sync clocks + SYNC_RX_HALF_CLK_OUT => soda_rxup_half_clk, + SYNC_RX_FULL_CLK_OUT => soda_rxup_full_clk, + SYNC_TX_HALF_CLK_OUT => soda_txup_half_clk, + SYNC_TX_FULL_CLK_OUT => soda_txup_full_clk, + + SYNC_RXD_P_IN => SERDES_ADDON_RX(4), + SYNC_RXD_N_IN => SERDES_ADDON_RX(5), + SYNC_TXD_P_OUT => SERDES_ADDON_TX(4), + SYNC_TXD_N_OUT => SERDES_ADDON_TX(5), + SYNC_TX_DLM_IN => soda_txup_dlm_S, + SYNC_TX_DLM_WORD_IN => soda_txup_dlm_word_S, + SYNC_RX_DLM_OUT => soda_rxup_dlm_S, + SYNC_RX_DLM_WORD_OUT => soda_rxup_dlm_word_S, + SYNC_PRSNT_N_IN => SFP_MOD0(3), + SYNC_LOS_IN => SFP_LOS(3), + SYNC_TXDIS_OUT => sfp_txdis_S(3), + + SCI_DATA_IN => sci1_data_in, + SCI_DATA_OUT => sci1_data_out, + SCI_ADDR => sci1_addr, + SCI_READ => sci1_read, + SCI_WRITE => sci1_write, + SCI_ACK => sci1_ack, + -- Status and control port + STAT_OP => med_stat_op(15 downto 0), + CTRL_OP => med_ctrl_op(15 downto 0), + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => (others => '0') + ); + + +------------------------------------------------------------------------- +-- Endpoint +------------------------------------------------------------------------- + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler + generic map( + --USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES), + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + BROADCAST_SPECIAL_ADDR => x"45", + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => x"9100b000", + REGIO_INIT_ADDRESS => x"f35b", + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 9, --13 + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 256, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 256 + ) + port map( + CLK => clk_100_osc, --rx_half_clk, PL 111114 + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out(0), + MED_DATA_OUT => med_data_out(15 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_out(2 downto 0), + MED_READ_IN => med_read_in(0), + MED_DATAREADY_IN => med_dataready_in(0), + MED_DATA_IN => med_data_in(15 downto 0), + MED_PACKET_NUM_IN => med_packet_num_in(2 downto 0), + MED_READ_OUT => med_read_out(0), + MED_STAT_OP_IN => med_stat_op(15 downto 0), + MED_CTRL_OP_OUT => med_ctrl_op(15 downto 0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => '0', + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => open, + LVL1_VALID_TIMING_TRG_OUT => open, + LVL1_VALID_NOTIMING_TRG_OUT => open, + LVL1_INVALID_TRG_OUT => open, + + LVL1_TRG_TYPE_OUT => open, + LVL1_TRG_NUMBER_OUT => open, + LVL1_TRG_CODE_OUT => open, + LVL1_TRG_INFORMATION_OUT => open, + LVL1_INT_TRG_NUMBER_OUT => open, + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => open, + TRG_TIMEOUT_DETECTED_OUT => open, + TRG_SPURIOUS_TRG_OUT => open, + TRG_MISSING_TMG_TRG_OUT => open, + TRG_SPIKE_DETECTED_OUT => open, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => '1', + FEE_TRG_STATUSBITS_IN => (others => '0'), + FEE_DATA_IN => (others => '0'), + FEE_DATA_WRITE_IN(0) => '0', + FEE_DATA_FINISHED_IN(0) => '1', + FEE_DATA_ALMOST_FULL_OUT(0) => open, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => stat_reg, --start 0x80 + REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT => open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + STAT_TRIGGER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => open + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 3, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"be00", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 4, others => 0) + ) + port map( + CLK => clk_100_osc, --rx_half_clk, PL 111114 + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + BUS_READ_ENABLE_OUT(0) => spimem_read_en, + BUS_READ_ENABLE_OUT(1) => sci1_read, + BUS_READ_ENABLE_OUT(2) => soda_read, + + BUS_WRITE_ENABLE_OUT(0) => spimem_write_en, + BUS_WRITE_ENABLE_OUT(1) => sci1_write, + BUS_WRITE_ENABLE_OUT(2) => soda_write, + + BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in, + BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in, + BUS_DATA_OUT(1*32+31 downto 1*32+8) => open, + BUS_DATA_OUT(2*32+31 downto 2*32) => soda_data_in, + + BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open, + BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open, + BUS_ADDR_OUT(2*16+3 downto 2*16) => soda_addr, + BUS_ADDR_OUT(2*16+15 downto 2*16+4) => open, + + BUS_TIMEOUT_OUT(0) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_TIMEOUT_OUT(2) => open, + + BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out, + BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out, + BUS_DATA_IN(1*32+31 downto 1*32+8) => open, + BUS_DATA_IN(2*32+31 downto 2*32) => soda_data_out, + + BUS_DATAREADY_IN(0) => spimem_dataready_out, + BUS_DATAREADY_IN(1) => sci1_ack, + BUS_DATAREADY_IN(2) => soda_ack, + + BUS_WRITE_ACK_IN(0) => spimem_write_ack_out, + BUS_WRITE_ACK_IN(1) => sci1_ack, + BUS_WRITE_ACK_IN(2) => soda_ack, + + BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_NO_MORE_DATA_IN(2) => '0', + + BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out, + BUS_UNKNOWN_ADDR_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(2) => '0', + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + +THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch + port map( + CLK_IN => clk_100_osc, + RESET_IN => reset_i, + + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_DATAREADY_OUT => spimem_dataready_out, + BUS_WRITE_ACK_OUT => spimem_write_ack_out, + BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out, + BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + + DO_REBOOT_IN => common_ctrl_reg(15), + PROGRAMN => PROGRAMN, + + SPI_CS_OUT => FLASH_CS, + SPI_SCK_OUT => FLASH_CLK, + SPI_SDO_OUT => FLASH_DIN, + SPI_SDI_IN => FLASH_DOUT + ); + + +-- SFP_TXDIS(1) <= sfp_txdis_S(1); + SFP_TXDIS <= sfp_txdis_S; + + ----------------------------------------------------------------------- + -- Since there is nomore trb on this link, link-phase does not need to + -- be controlled. To avoid changing code, link-phase is faked here. + ----------------------------------------------------------------------- + DUMMY_LINK_PHASE_PROC : process (soda_rxup_full_clk) + begin + if rising_edge(soda_rxup_full_clk) then + if (reset_i='1') then + soda_uplink_phase_S <='0'; + elsif (soda_uplink_phase_S='0') then + soda_uplink_phase_S <='1'; + else + soda_uplink_phase_S <='0'; + end if; + end if; + end process; + + +--------------------------------------------------------------------------- +-- The Soda Central +--------------------------------------------------------------------------- + + A_SODA_HUB : soda_hub + port map( + SYSCLK => soda_rxup_half_clk, + SODACLK => soda_rxup_full_clk, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + + -- SINGLE DUBPLEX UP-LINK TO THE TOP + RXUP_DLM_WORD_IN => soda_rxup_dlm_word_S, + RXUP_DLM_IN => soda_rxup_dlm_S, + TXUP_DLM_OUT => soda_txup_dlm_S, + TXUP_DLM_WORD_OUT => soda_txup_dlm_word_S, + TXUP_DLM_PREVIEW_OUT => soda_txup_dlm_preview_S, + UPLINK_PHASE_IN => soda_uplink_phase_S, + -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM + RXDN_DLM_WORD_IN => soda_rxdn_dlm_word_S, + RXDN_DLM_IN => soda_rxdn_dlm_S, + TXDN_DLM_OUT => soda_txdn_dlm_S, + TXDN_DLM_WORD_OUT => soda_txdn_dlm_word_S, + TXDN_DLM_PREVIEW_OUT => soda_txdn_dlm_preview_S, + DNLINK_PHASE_IN => soda_dnlink_phase_S, + + SODA_DATA_IN => soda_data_in, + SODA_DATA_OUT => soda_data_out, + SODA_ADDR_IN => soda_addr, + SODA_READ_IN => soda_read, + SODA_WRITE_IN => soda_write, + SODA_ACK_OUT => soda_ack, + LEDS_OUT => soda_leds, + LINK_DEBUG_IN => link_debug_in_S + ); + + + downlink_reset <= reset_i; --'1' when (reset_i = '1' or uplink_ready_S = '0') else '0'; + downlink_clear <= clear_i; --'1' when (clear_i = '1' or uplink_ready_S = '0') else '0'; + + + THE_SODA_HUB_SYNC_DOWNLINK : soda_only_ecp3_sfp_4_sync_down + generic map( + SERDES_NUM => 0, --number of serdes in quad + IS_SYNC_SLAVE => c_NO + ) + port map( + OSC_CLK => clk_200_osc, + TX_DATACLK => soda_rxup_full_clk, + SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd + RESET => downlink_reset, + CLEAR => downlink_clear, + --------------------------------------------------------------------------------------------------------------------------------------------------------- +-- LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. + --------------------------------------------------------------------------------------------------------------------------------------------------------- + RX_HALF_CLK_OUT(0) => soda_rxdn_half_clk(0), + RX_HALF_CLK_OUT(1) => soda_rxdn_half_clk(1), + RX_HALF_CLK_OUT(2) => soda_rxdn_half_clk(2), + RX_HALF_CLK_OUT(3) => soda_rxdn_half_clk(3), + + RX_FULL_CLK_OUT(0) => soda_rxdn_full_clk(0), -- needed for sync replies i.e. calibration + RX_FULL_CLK_OUT(1) => soda_rxdn_full_clk(1), -- needed for sync replies i.e. calibration + RX_FULL_CLK_OUT(2) => soda_rxdn_full_clk(2), -- needed for sync replies i.e. calibration + RX_FULL_CLK_OUT(3) => soda_rxdn_full_clk(3), -- needed for sync replies i.e. calibration + + TX_HALF_CLK_OUT(0) => soda_txdn_half_clk(0), + TX_HALF_CLK_OUT(1) => soda_txdn_half_clk(1), + TX_HALF_CLK_OUT(2) => soda_txdn_half_clk(2), + TX_HALF_CLK_OUT(3) => soda_txdn_half_clk(3), + + TX_FULL_CLK_OUT(0) => soda_txdn_full_clk(0), + TX_FULL_CLK_OUT(1) => soda_txdn_full_clk(1), + TX_FULL_CLK_OUT(2) => soda_txdn_full_clk(2), + TX_FULL_CLK_OUT(3) => soda_txdn_full_clk(3), + + RX_DLM_OUT(0) => soda_rxdn_dlm_S(0), + RX_DLM_OUT(1) => soda_rxdn_dlm_S(1), + RX_DLM_OUT(2) => soda_rxdn_dlm_S(2), + RX_DLM_OUT(3) => soda_rxdn_dlm_S(3), + + RX_DLM_WORD_OUT(0) => soda_rxdn_dlm_word_S(0), + RX_DLM_WORD_OUT(1) => soda_rxdn_dlm_word_S(1), + RX_DLM_WORD_OUT(2) => soda_rxdn_dlm_word_S(2), + RX_DLM_WORD_OUT(3) => soda_rxdn_dlm_word_S(3), + + TX_DLM_IN(0) => soda_txdn_dlm_S(0), + TX_DLM_IN(1) => soda_txdn_dlm_S(1), + TX_DLM_IN(2) => soda_txdn_dlm_S(2), + TX_DLM_IN(3) => soda_txdn_dlm_S(3), + + TX_DLM_WORD_IN(0) => soda_txdn_dlm_word_S(0), + TX_DLM_WORD_IN(1) => soda_txdn_dlm_word_S(1), + TX_DLM_WORD_IN(2) => soda_txdn_dlm_word_S(2), + TX_DLM_WORD_IN(3) => soda_txdn_dlm_word_S(3), + + TX_DLM_PREVIEW_IN(0) => soda_txdn_dlm_preview_S(0), --PL! + TX_DLM_PREVIEW_IN(1) => soda_txdn_dlm_preview_S(1), --PL! + TX_DLM_PREVIEW_IN(2) => soda_txdn_dlm_preview_S(2), --PL! + TX_DLM_PREVIEW_IN(3) => soda_txdn_dlm_preview_S(3), --PL! + + LINK_PHASE_OUT(0) => soda_dnlink_phase_S(0), --PL! + LINK_PHASE_OUT(1) => soda_dnlink_phase_S(1), --PL! + LINK_PHASE_OUT(2) => soda_dnlink_phase_S(2), --PL! + LINK_PHASE_OUT(3) => soda_dnlink_phase_S(3), --PL! + + --SFP Connection + SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0 + SD_RXD_P_IN(1) => SERDES_ADDON_RX(1), + SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1 + SD_RXD_P_IN(3) => SERDES_ADDON_RX(11), + SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2 + SD_RXD_N_IN(1) => SERDES_ADDON_RX(3), + SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3 + SD_RXD_N_IN(3) => SERDES_ADDON_RX(7), + SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0 + SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1), + SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1 + SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11), + SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2 + SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3), + SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3 + SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7), + SD_REFCLK_P_IN => (others => '0'), + SD_REFCLK_N_IN => ('0','0','0','0'), + SD_PRSNT_N_IN(0) => SFP_MOD0(1), + SD_PRSNT_N_IN(1) => SFP_MOD0(6), + SD_PRSNT_N_IN(2) => SFP_MOD0(2), + SD_PRSNT_N_IN(3) => SFP_MOD0(4), + SD_LOS_IN(0) => SFP_LOS(1), + SD_LOS_IN(1) => SFP_LOS(6), + SD_LOS_IN(2) => SFP_LOS(2), + SD_LOS_IN(3) => SFP_LOS(4), + SD_TXDIS_OUT(0) => sfp_txdis_S(1), + SD_TXDIS_OUT(1) => sfp_txdis_S(6), + SD_TXDIS_OUT(2) => sfp_txdis_S(2), + SD_TXDIS_OUT(3) => sfp_txdis_S(4), + + SCI_DATA_IN => sci2_data_in, + SCI_DATA_OUT => sci2_data_out, + SCI_ADDR => sci2_addr, + SCI_READ => sci2_read, + SCI_WRITE => sci2_write, + SCI_ACK => sci2_ack, + SCI_NACK => sci2_nack + ); + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_ORANGE <= time_counter(26); + LED_YELLOW <= time_counter(26); + LED_GREEN <= time_counter(26); + LED_RED <= time_counter(26); +--------------------------------------------------------------------------- +-- DEBUG +--------------------------------------------------------------------------- + link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0); + link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0'); +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + blink : process (clk_100_osc) + begin + if rising_edge(clk_100_osc) then + if (time_counter = x"FFFFFFFF") then + time_counter <= x"00000000"; + else + time_counter <= time_counter + 1; + end if; + end if; + end process; + +end Cu_trb3_periph_soda_hub_arch; \ No newline at end of file diff --git a/code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd b/code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd new file mode 100644 index 0000000..a646ea3 --- /dev/null +++ b/code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd @@ -0,0 +1,1052 @@ +--Media interface for Lattice ECP3 using PCS at 2GHz + + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; + +entity Cu_trb_net16_soda_syncUP_ecp3_sfp is + port( + OSCCLK : in std_logic; -- 200 MHz reference clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + --Internal Connection TX + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic := '0'; + --Internal Connection RX + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); + MED_DATAREADY_OUT : out std_logic := '0'; + MED_READ_IN : in std_logic; + + --Copper SFP Connection + CU_RXD_P_IN : in std_logic; + CU_RXD_N_IN : in std_logic; + CU_TXD_P_OUT : out std_logic; + CU_TXD_N_OUT : out std_logic; + CU_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + CU_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + CU_TXDIS_OUT : out std_logic := '0'; -- SFP disable + --Fiber/sync SFP Connection + SYNC_RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + SYNC_TX_DLM_IN : in std_logic; + SYNC_TX_DLM_WORD_IN : in std_logic_vector(7 downto 0); + SYNC_RX_DLM_OUT : out std_logic; + SYNC_RX_DLM_WORD_OUT : out std_logic_vector(7 downto 0); + SYNC_RXD_P_IN : in std_logic; + SYNC_RXD_N_IN : in std_logic; + SYNC_TXD_P_OUT : out std_logic; + SYNC_TXD_N_OUT : out std_logic; + SYNC_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SYNC_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SYNC_TXDIS_OUT : out std_logic := '0'; -- SFP disable + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; + SCI_NACK : out std_logic := '0'; + + TX_READY_CH3 : out std_logic; + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); +end entity; + +architecture Cu_trb_net16_soda_syncUP_ecp3_sfp_arch of Cu_trb_net16_soda_syncUP_ecp3_sfp is + + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of Cu_trb_net16_soda_syncUP_ecp3_sfp_arch : architecture is "media_interface_group"; + attribute syn_sharing : string; + attribute syn_sharing of Cu_trb_net16_soda_syncUP_ecp3_sfp_arch : architecture is "off"; + + component sfp_2_200_int + port + ( + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + sci_sel_ch1 : in std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (15 downto 0); + tx_k_ch1 : in std_logic_vector (1 downto 0); + tx_force_disp_ch1 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); + rxdata_ch1 : out std_logic_vector (15 downto 0); + rx_k_ch1 : out std_logic_vector (1 downto 0); + rx_disp_err_ch1 : out std_logic_vector (1 downto 0); + rx_cv_err_ch1 : out std_logic_vector (1 downto 0); + rx_serdes_rst_ch1_c : in std_logic; + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pcs_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pcs_rst_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; + tx_div2_mode_ch1_c : in std_logic; + rx_div2_mode_ch1_c : in std_logic; + + hdinp_ch3, hdinn_ch3 : in std_logic; + hdoutp_ch3, hdoutn_ch3 : out std_logic; + sci_sel_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + fpga_rxrefclk_ch3 : in std_logic; + txdata_ch3 : in std_logic_vector (7 downto 0); + tx_k_ch3 : in std_logic; + tx_force_disp_ch3 : in std_logic; + tx_disp_sel_ch3 : in std_logic; + rxdata_ch3 : out std_logic_vector (7 downto 0); + rx_k_ch3 : out std_logic; + rx_disp_err_ch3 : out std_logic; + rx_cv_err_ch3 : out std_logic; + rx_serdes_rst_ch3_c : in std_logic; + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + tx_pcs_rst_ch3_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pcs_rst_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch3_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; + tx_div2_mode_ch3_c : in std_logic; + rx_div2_mode_ch3_c : in std_logic; + ---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + tx_sync_qd_c : in std_logic; + rst_qd_c : in std_logic; + refclk2fpga : out std_logic; + serdes_rst_qd_c : in std_logic + ); + end component; + + type t_sync_tx_proc_state is (cSEND_IDLE,cSEND_DLM); --,cFIFO_READ); + signal sync_tx_proc_state : t_sync_tx_proc_state; + + + signal refck2core : std_logic; + -- signal clock : std_logic; + --reset signals + signal ffc_quad_rst : std_logic; + signal ffc_lane_tx_rst : std_logic; + signal ffc_lane_rx_rst : std_logic; + --serdes connections + signal tx_data : std_logic_vector(15 downto 0); + signal tx_k : std_logic_vector(1 downto 0); + signal rx_data : std_logic_vector(15 downto 0); -- delayed signals + signal rx_k : std_logic_vector(1 downto 0); -- delayed signals + signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP + signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP + signal link_ok : std_logic_vector(0 downto 0); + signal link_error : std_logic_vector(8 downto 0); + signal ff_txhalfclk : std_logic; + signal ff_rxhalfclk : std_logic; + signal ff_rxfullclk : std_logic; + --rx fifo signals + signal fifo_rx_rd_en : std_logic; + signal fifo_rx_wr_en : std_logic; + signal fifo_rx_reset : std_logic; + signal fifo_rx_din : std_logic_vector(17 downto 0); + signal fifo_rx_dout : std_logic_vector(17 downto 0); + signal fifo_rx_full : std_logic; + signal fifo_rx_empty : std_logic; + --tx fifo signals + signal fifo_tx_rd_en : std_logic; + signal fifo_tx_wr_en : std_logic; + signal fifo_tx_reset : std_logic; + signal fifo_tx_din : std_logic_vector(17 downto 0); + signal fifo_tx_dout : std_logic_vector(17 downto 0); + signal fifo_tx_full : std_logic; + signal fifo_tx_empty : std_logic; + signal fifo_tx_almost_full : std_logic; + --rx path + signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal buf_med_dataready_out : std_logic; + signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal last_rx : std_logic_vector(8 downto 0); + signal last_fifo_rx_empty : std_logic; + --tx path + signal last_fifo_tx_empty : std_logic; + --link status + signal rx_k_q : std_logic_vector(1 downto 0); + + signal quad_rst : std_logic; + signal lane_rst : std_logic; + signal tx_allow : std_logic; + signal rx_allow : std_logic; + signal tx_allow_qtx : std_logic; + + signal rx_allow_q : std_logic; -- clock domain changed signal + signal tx_allow_q : std_logic; + signal swap_bytes : std_logic; + signal buf_stat_debug : std_logic_vector(31 downto 0); + + -- status inputs from SFP + signal sfp_prsnt_n : std_logic; -- synchronized input signals + signal sfp_los : std_logic; -- synchronized input signals + + signal buf_STAT_OP : std_logic_vector(15 downto 0); + + signal led_counter : unsigned(16 downto 0); + signal rx_led : std_logic; + signal tx_led : std_logic; + + + signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion + signal first_idle : std_logic; -- tag the first IDLE2 after data + + signal reset_word_cnt : unsigned(4 downto 0); + signal make_trbnet_reset : std_logic; + signal make_trbnet_reset_q : std_logic; + signal send_reset_words : std_logic; + signal send_reset_words_q : std_logic; + signal send_reset_in : std_logic; + signal send_reset_in_qtx : std_logic; + signal reset_i : std_logic; + signal reset_i_rx : std_logic; + signal pwr_up : std_logic; + + signal clk_sys : std_logic; + signal clk_tx : std_logic; + signal clk_rx : std_logic; + signal clk_rxref : std_logic; + signal clk_txref : std_logic; + + -- Peter Schakel 3-dec-2014 + + signal sci_timer : unsigned(12 downto 0) := (others => '0'); + signal reset_n : std_logic; + signal trb_rx_serdes_rst : std_logic; + signal trb_rx_cdr_lol : std_logic; + signal trb_rx_los_low : std_logic; + signal trb_rx_pcs_rst : std_logic; + signal trb_tx_pcs_rst : std_logic; + signal rst_qd : std_logic; + signal rst_qd1 : std_logic; + signal rst_qd3 : std_logic; + signal link_OK_S : std_logic; + signal trb_rx_fsm_state : std_logic_vector(3 downto 0); + signal trb_tx_fsm_state : std_logic_vector(3 downto 0); + signal sync_rx_fsm_state : std_logic_vector(3 downto 0); + signal sync_tx_fsm_state : std_logic_vector(3 downto 0); + signal clk_200_osc : std_logic; + signal sync_rx_full_clk : std_logic; + signal sync_rx_half_clk : std_logic; + signal sync_tx_full_clk : std_logic; + signal sync_tx_half_clk : std_logic; + + signal sync_tx_data : std_logic_vector(7 downto 0); + signal sync_tx_k : std_logic; + signal SYNC_TX_DLM_IN_S : std_logic; + signal sync_rx_data : std_logic_vector(7 downto 0); + signal sync_rx_k : std_logic; + signal sync_rx_error : std_logic; + signal sync_rx_serdes_rst : std_logic; + signal sync_tx_pcs_rst : std_logic; + signal sync_rx_pcs_rst : std_logic; + signal sync_rx_los_low : std_logic; + signal sync_lsm_status : std_logic; + signal sync_rx_cdr_lol : std_logic; + signal dlm_fifo_rd_en : std_logic; + signal dlm_fifo_empty : std_logic; + signal dlm_fifo_reading : std_logic; + signal dlm_received_S : std_logic; + + signal syncfifo_din : std_logic_vector(17 downto 0); + signal syncfifo_dout : std_logic_vector(17 downto 0); + + type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); + signal sci_state : sci_ctrl; + + signal sci_ch_i : std_logic_vector(3 downto 0); + signal sci_qd_i : std_logic; + signal sci_reg_i : std_logic; + signal sci_addr_i : std_logic_vector(8 downto 0); + signal sci_data_in_i : std_logic_vector(7 downto 0); + signal sci_data_out_i : std_logic_vector(7 downto 0); + signal sci_read_i : std_logic; + signal sci_write_i : std_logic; + signal sci_write_shift_i : std_logic_vector(2 downto 0); + signal sci_read_shift_i : std_logic_vector(2 downto 0); + + signal tx_pll_lol_qd_i : std_logic; + + signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; + signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF"; + signal sync_wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF"; + signal sync_tx_allow : std_logic; + signal sync_rx_allow : std_logic; + signal sync_tx_allow_q : std_logic; + signal sync_rx_allow_q : std_logic; + signal link_phase_S : std_logic; --PL! + signal request_retr_i : std_logic; + signal start_retr_i : std_logic; + signal request_retr_position_i : std_logic_vector(7 downto 0); + signal start_retr_position_i : std_logic_vector(7 downto 0); + signal send_link_reset_i : std_logic; + signal make_link_reset_i : std_logic; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + attribute syn_keep of led_counter : signal is true; + attribute syn_keep of send_reset_in : signal is true; + attribute syn_keep of reset_i : signal is true; + attribute syn_preserve of reset_i : signal is true; + attribute syn_preserve of sci_ch_i : signal is true;-- + attribute syn_keep of sci_ch_i : signal is true;-- + attribute syn_preserve of sci_addr_i : signal is true;-- + attribute syn_keep of sci_addr_i : signal is true;-- + attribute syn_preserve of sci_data_in_i : signal is true;-- + attribute syn_keep of sci_data_in_i : signal is true;-- + attribute syn_preserve of sci_data_out_i : signal is true;-- + attribute syn_keep of sci_data_out_i : signal is true;-- + attribute syn_preserve of sci_read_i : signal is true;-- + attribute syn_keep of sci_read_i : signal is true;-- + attribute syn_preserve of sci_write_i : signal is true;-- + attribute syn_keep of sci_write_i : signal is true;-- + attribute syn_preserve of sci_write_shift_i : signal is true;-- + attribute syn_keep of sci_write_shift_i : signal is true;-- + attribute syn_preserve of sci_read_shift_i : signal is true;-- + attribute syn_keep of sci_read_shift_i : signal is true;-- + attribute syn_preserve of wa_position : signal is true;-- + attribute syn_keep of wa_position : signal is true;-- + attribute syn_preserve of wa_position_rx : signal is true;-- + attribute syn_keep of wa_position_rx : signal is true;-- + +begin + +clk_200_osc <= OSCCLK; + +SYNC_RX_HALF_CLK_OUT <= sync_rx_half_clk; +SYNC_RX_FULL_CLK_OUT <= sync_rx_full_clk; +SYNC_TX_HALF_CLK_OUT <= sync_tx_half_clk; +SYNC_TX_FULL_CLK_OUT <= sync_tx_full_clk; +--RX_CDR_LOL_OUT <= rx_cdr_lol; + +clk_sys <= SYSCLK; +clk_tx <= SYSCLK; +clk_rx <= ff_rxhalfclk; +clk_rxref <= OSCCLK; +clk_txref <= OSCCLK; + +--sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL! + +-------------------------------------------------------------------------- +-- Internal Lane Resets +-------------------------------------------------------------------------- + PROC_RESET : process(clk_sys) + begin + if rising_edge(clk_sys) then + reset_i <= RESET; + send_reset_in <= ctrl_op(15); + pwr_up <= '1'; --not CTRL_OP(i*16+14); + end if; + end process; + +-------------------------------------------------------------------------- +-- Synchronizer stages +-------------------------------------------------------------------------- + +-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP) +THE_SFP_STATUS_SYNC: signal_sync + generic map( + DEPTH => 3, + WIDTH => 2 + ) + port map( + RESET => '0', + D_IN(0) => sync_prsnt_n_in, + D_IN(1) => sync_los_in, + CLK0 => clk_sys, + CLK1 => clk_sys, + D_OUT(0) => sfp_prsnt_n, + D_OUT(1) => sfp_los + ); + + +THE_RX_K_SYNC: signal_sync + generic map( + DEPTH => 1, + WIDTH => 4 + ) + port map( + RESET => reset_i, + D_IN(1 downto 0) => comb_rx_k, + D_IN(2) => send_reset_words, + D_IN(3) => make_trbnet_reset, + CLK0 => clk_rx, -- CHANGED + CLK1 => clk_sys, + D_OUT(1 downto 0) => rx_k_q, + D_OUT(2) => send_reset_words_q, + D_OUT(3) => make_trbnet_reset_q + ); + +THE_RX_DATA_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 16 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_data, + CLK0 => clk_rx, + CLK1 => clk_rx, + D_OUT => rx_data + ); + +THE_RX_K_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_k, + CLK0 => clk_rx, + CLK1 => clk_rx, + D_OUT => rx_k + ); + +THE_RX_RESET: signal_sync + generic map( + DEPTH => 1, + WIDTH => 1 + ) + port map( + RESET => '0', + D_IN(0) => reset_i, + CLK0 => clk_rx, + CLK1 => clk_rx, + D_OUT(0) => reset_i_rx + ); + +-- Delay for ALLOW signals +THE_RX_ALLOW_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset_i, + D_IN(0) => rx_allow, + D_IN(1) => tx_allow, + CLK0 => clk_sys, + CLK1 => clk_sys, + D_OUT(0) => rx_allow_q, + D_OUT(1) => tx_allow_q + ); + +THE_TX_SYNC: signal_sync + generic map( + DEPTH => 1, + WIDTH => 2 + ) + port map( + RESET => '0', + D_IN(0) => send_reset_in, + D_IN(1) => tx_allow, + CLK0 => clk_tx, + CLK1 => clk_tx, + D_OUT(0) => send_reset_in_qtx, + D_OUT(1) => tx_allow_qtx + ); + +--THE_DLM_IN_DELAY: signal_sync +-- generic map( +-- DEPTH => 1, +-- WIDTH => 1 +-- ) +-- port map( +-- RESET => '0', +-- D_IN(0) => SYNC_TX_DLM_IN, +-- CLK0 => sync_rx_full_clk, +-- CLK1 => sync_rx_full_clk, +-- D_OUT(0) => SYNC_TX_DLM_IN_S +-- ); +-------------------------------------------------------------------------- +-- Main control state machine, startup control for SFP +-------------------------------------------------------------------------- + +THE_SFP_LSM: trb_net16_lsm_sfp + generic map ( + HIGHSPEED_STARTUP => c_YES + ) + port map( + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear, + SFP_MISSING_IN => sfp_prsnt_n, + SFP_LOS_IN => sfp_los, + SD_LINK_OK_IN => link_ok(0), + SD_LOS_IN => link_error(8), + SD_TXCLK_BAD_IN => link_error(5), + SD_RXCLK_BAD_IN => link_error(4), + SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN => rx_k_q, + SD_CV_IN => link_error(7 downto 6), + FULL_RESET_OUT => quad_rst, + LANE_RESET_OUT => lane_rst, + TX_ALLOW_OUT => tx_allow, + RX_ALLOW_OUT => rx_allow, + SWAP_BYTES_OUT => swap_bytes, + STAT_OP => buf_stat_op, + CTRL_OP => ctrl_op, + STAT_DEBUG => buf_stat_debug + ); + +SYNC_TXDIS_OUT <= quad_rst or reset_i; + +-------------------------------------------------------------------------- +-------------------------------------------------------------------------- + +ffc_quad_rst <= quad_rst; +ffc_lane_tx_rst <= lane_rst; + + +ffc_lane_rx_rst <= lane_rst; + + + +-- Instantiation of serdes module + + THE_SERDES: sfp_2_200_int + port map( + HDINP_CH1 => CU_RXD_P_IN, + HDINN_CH1 => CU_RXD_N_IN, + HDOUTP_CH1 => CU_TXD_P_OUT, + HDOUTN_CH1 => CU_TXD_N_OUT, + SCI_SEL_CH1 => sci_ch_i(1), + RXICLK_CH1 => clk_rx, + TXICLK_CH1 => clk_tx, + RX_FULL_CLK_CH1 => ff_rxfullclk, + RX_HALF_CLK_CH1 => ff_rxhalfclk, + TX_FULL_CLK_CH1 => open, + TX_HALF_CLK_CH1 => ff_txhalfclk, + FPGA_RXREFCLK_CH1 => clk_rxref, + TXDATA_CH1 => tx_data, + TX_K_CH1 => tx_k, + TX_FORCE_DISP_CH1 => tx_correct, + TX_DISP_SEL_CH1 => "00", + RXDATA_CH1 => comb_rx_data, + RX_K_CH1 => comb_rx_k, + RX_DISP_ERR_CH1 => open, + RX_CV_ERR_CH1 => link_error(7 downto 6), + RX_SERDES_RST_CH1_C => trb_rx_serdes_rst, + SB_FELB_CH1_C => '0', --loopback enable + SB_FELB_RST_CH1_C => '0', --loopback reset + TX_PCS_RST_CH1_C => trb_tx_pcs_rst, --'1', --tx power up + TX_PWRUP_CH1_C => '1', --tx power up + RX_PCS_RST_CH1_C => trb_rx_pcs_rst, --'1', --rx power up + RX_PWRUP_CH1_C => '1', --rx power up + RX_LOS_LOW_CH1_S => trb_rx_los_low, --link_error(8), + LSM_STATUS_CH1_S => link_ok(0), + RX_CDR_LOL_CH1_S => trb_rx_cdr_lol, --link_error(4), + TX_DIV2_MODE_CH1_C => '0', --full rate + RX_DIV2_MODE_CH1_C => '0', --full rate + + HDINP_CH3 => SYNC_RXD_P_IN, + HDINN_CH3 => SYNC_RXD_N_IN, + HDOUTP_CH3 => SYNC_TXD_P_OUT, + HDOUTN_CH3 => SYNC_TXD_N_OUT, + SCI_SEL_CH3 => sci_ch_i(3), + TXICLK_CH3 => sync_rx_full_clk, + RX_FULL_CLK_CH3 => sync_rx_full_clk, + RX_HALF_CLK_CH3 => sync_rx_half_clk, + TX_FULL_CLK_CH3 => sync_tx_full_clk, + TX_HALF_CLK_CH3 => sync_tx_half_clk, + FPGA_RXREFCLK_CH3 => clk_200_osc, + TXDATA_CH3 => sync_tx_data, + TX_K_CH3 => sync_tx_k, + TX_FORCE_DISP_CH3 => '0', + TX_DISP_SEL_CH3 => '0', + RXDATA_CH3 => sync_rx_data, + RX_K_CH3 => sync_rx_k, + RX_DISP_ERR_CH3 => open, + RX_CV_ERR_CH3 => sync_rx_error, + RX_SERDES_RST_CH3_C => sync_rx_serdes_rst, + SB_FELB_CH3_C => '0', --loopback enable + SB_FELB_RST_CH3_C => '0', --loopback reset + TX_PCS_RST_CH3_C => sync_tx_pcs_rst, + TX_PWRUP_CH3_C => '1', + RX_PCS_RST_CH3_C => sync_rx_pcs_rst, + RX_PWRUP_CH3_C => '1', + RX_LOS_LOW_CH3_S => sync_rx_los_low, + LSM_STATUS_CH3_S => sync_lsm_status, + RX_CDR_LOL_CH3_S => sync_rx_cdr_lol, + TX_DIV2_MODE_CH3_C => '0', + RX_DIV2_MODE_CH3_C => '0', + + SCI_WRDATA => sci_data_in_i, + SCI_ADDR => sci_addr_i(5 downto 0), + SCI_RDDATA => sci_data_out_i, + SCI_SEL_QUAD => sci_addr_i(8), + SCI_RD => sci_read_i, + SCI_WRN => sci_write_i, + FPGA_TXREFCLK => clk_txref, +-- FPGA_TXREFCLK => rx_full_clk, + TX_SERDES_RST_C => CLEAR, + TX_PLL_LOL_QD_S => link_error(5), + TX_SYNC_QD_C => '0', + RST_QD_C => rst_qd, + REFCLK2FPGA => open, + SERDES_RST_QD_C => ffc_quad_rst + ); + +------------------------------------------------------------------------- +-- RX Fifo & Data output +------------------------------------------------------------------------- +THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport +generic map( + USE_STATUS_FLAGS => c_NO + ) +port map( read_clock_in => clk_sys, + write_clock_in => clk_rx, -- CHANGED + read_enable_in => fifo_rx_rd_en, + write_enable_in => fifo_rx_wr_en, + fifo_gsr_in => fifo_rx_reset, + write_data_in => fifo_rx_din, + read_data_out => fifo_rx_dout, + full_out => fifo_rx_full, + empty_out => fifo_rx_empty + ); + +fifo_rx_reset <= reset_i or not rx_allow_q; +fifo_rx_rd_en <= not fifo_rx_empty; + +-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path +THE_BYTE_SWAP_PROC: process + begin + wait until rising_edge(clk_rx); --CHANGED + last_rx <= rx_k(1) & rx_data(15 downto 8); + if( swap_bytes = '0' ) then + fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0); + fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0); + else + fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0); + fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0); + end if; + end process THE_BYTE_SWAP_PROC; + +buf_med_data_out <= fifo_rx_dout(15 downto 0); +buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q; +buf_med_packet_num_out <= rx_counter; +med_read_out <= tx_allow_q and not fifo_tx_almost_full; + + +THE_CNT_RESET_PROC : process + begin + wait until rising_edge(clk_rx); --CHANGED + if reset_i_rx = '1' then + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + reset_word_cnt <= (others => '0'); + else + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + if fifo_rx_din = "11" & x"FEFE" then + if reset_word_cnt(4) = '0' then + reset_word_cnt <= reset_word_cnt + to_unsigned(1,1); + else + send_reset_words <= '1'; + end if; + else + reset_word_cnt <= (others => '0'); + make_trbnet_reset <= reset_word_cnt(4); + end if; + end if; + end process; + + +THE_SYNC_PROC: process + begin + wait until rising_edge(clk_sys); + med_dataready_out <= buf_med_dataready_out; + med_data_out <= buf_med_data_out; + med_packet_num_out <= buf_med_packet_num_out; + if reset_i = '1' then + med_dataready_out <= '0'; + end if; + end process; + + +--rx packet counter +--------------------- +THE_RX_PACKETS_PROC: process( clk_sys ) + begin + if( rising_edge(clk_sys) ) then + last_fifo_rx_empty <= fifo_rx_empty; + if reset_i = '1' or rx_allow_q = '0' then + rx_counter <= c_H0; + else + if( buf_med_dataready_out = '1' ) then + if( rx_counter = c_max_word_number ) then + rx_counter <= (others => '0'); + else + rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1)); + end if; + end if; + end if; + end if; + end process; + +--TX Fifo & Data output to Serdes +--------------------- +THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( read_clock_in => clk_tx, + write_clock_in => clk_sys, + read_enable_in => fifo_tx_rd_en, + write_enable_in => fifo_tx_wr_en, + fifo_gsr_in => fifo_tx_reset, + write_data_in => fifo_tx_din, + read_data_out => fifo_tx_dout, + full_out => fifo_tx_full, + empty_out => fifo_tx_empty, + almost_full_out => fifo_tx_almost_full + ); + +fifo_tx_reset <= reset_i or not tx_allow_q; +fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in; +fifo_tx_wr_en <= med_dataready_in and tx_allow_q; +fifo_tx_rd_en <= tx_allow_qtx; + + +THE_SERDES_INPUT_PROC: process( clk_tx ) + begin + if( rising_edge(clk_tx) ) then + last_fifo_tx_empty <= fifo_tx_empty; + first_idle <= not last_fifo_tx_empty and fifo_tx_empty; + if send_reset_in = '1' then + tx_data <= x"FEFE"; + tx_k <= "11"; + elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then + tx_data <= x"50bc"; + tx_k <= "01"; + tx_correct <= first_idle & '0'; + else + tx_data <= fifo_tx_dout(15 downto 0); + tx_k <= "00"; + tx_correct <= "00"; + end if; + end if; + end process THE_SERDES_INPUT_PROC; + + +sync_rx_proc : process(sync_rx_full_clk) +begin + if rising_edge(sync_rx_full_clk) then + SYNC_RX_DLM_OUT <= '0'; + if dlm_received_S='1' then + dlm_received_S <= '0'; + SYNC_RX_DLM_OUT <= '1'; + SYNC_RX_DLM_WORD_OUT <= sync_rx_data; + elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then + dlm_received_S <= '1'; + end if; + end if; +end process; + +sync_tx_fsm : process(sync_tx_full_clk) +begin + if rising_edge(sync_tx_full_clk) then + case sync_tx_proc_state is + when cSEND_IDLE => + if (SYNC_TX_DLM_IN='0') then + sync_tx_proc_state <= cSEND_IDLE; +-- dlm_fifo_rd_en <= '0'; + sync_tx_data <= x"BC"; -- idle + sync_tx_k <= '1'; + else + sync_tx_proc_state <= cSEND_DLM; +-- dlm_fifo_rd_en <= '1'; + sync_tx_data <= x"DC"; -- dlm + sync_tx_k <= '1'; + end if; +-- when cFIFO_READ => +-- sync_tx_proc_state <= cSEND_DLM; +-- dlm_fifo_rd_en <= '0'; +-- sync_tx_data <= x"DC"; -- dlm +-- sync_tx_k <= '1'; + when cSEND_DLM => + sync_tx_proc_state <= cSEND_IDLE; +-- dlm_fifo_rd_en <= '0'; + sync_tx_data <= SYNC_TX_DLM_WORD_IN; --syncfifo_dout(7 downto 0); + sync_tx_k <= '0'; + when others => + sync_tx_proc_state <= cSEND_IDLE; + dlm_fifo_rd_en <= '0'; + sync_tx_data <= x"BC"; -- idle + sync_tx_k <= '1'; + end case; + end if; +end process; + + +--sync_tx_proc : process(sync_tx_full_clk) +--begin + --if rising_edge(sync_tx_full_clk) then + --if dlm_fifo_rd_en='1' then + --dlm_fifo_rd_en <= '0'; + --sync_tx_data <= syncfifo_dout(7 downto 0); + --sync_tx_k <= '0'; + --elsif (dlm_fifo_empty='0') and (dlm_fifo_reading='1') then + --dlm_fifo_rd_en <= '1'; + --sync_tx_data <= x"DC"; + --sync_tx_k <= '1'; + --elsif dlm_fifo_empty='0' then + --dlm_fifo_reading <= '1'; + --dlm_fifo_rd_en <= '0'; + --sync_tx_data <= x"BC"; -- idle + --sync_tx_k <= '1'; + --else + --dlm_fifo_reading <= '0'; + --dlm_fifo_rd_en <= '0'; + --sync_tx_data <= x"BC"; -- idle + --sync_tx_k <= '1'; + --end if; + --end if; +--end process; + +link_error(8) <= trb_rx_los_low; -- loss of signal +link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock +link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock + +reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1'; + +------------------------------------------------- +-- Reset FSM & Link states +------------------------------------------------- +THE_RX_FSM1: rx_reset_fsm + port map( + RST_N => reset_n, + RX_REFCLK => OSCCLK, + TX_PLL_LOL_QD_S => tx_pll_lol_qd_i, + RX_SERDES_RST_CH_C => trb_rx_serdes_rst, + RX_CDR_LOL_CH_S => trb_rx_cdr_lol, + RX_LOS_LOW_CH_S => trb_rx_los_low, + RX_PCS_RST_CH_C => trb_rx_pcs_rst, + WA_POSITION => "0000", + STATE_OUT => trb_rx_fsm_state + ); + +link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0'; + +THE_TX_FSM1: tx_reset_fsm + port map( + RST_N => reset_n, + TX_REFCLK => OSCCLK, + TX_PLL_LOL_QD_S => tx_pll_lol_qd_i, + RST_QD_C => rst_qd1, + TX_PCS_RST_CH_C => trb_tx_pcs_rst, + STATE_OUT => trb_tx_fsm_state --open + ); + +THE_RX_FSM3: rx_reset_fsm + port map( + RST_N => reset_n, + RX_REFCLK => sync_rx_full_clk, + TX_PLL_LOL_QD_S => tx_pll_lol_qd_i, + RX_SERDES_RST_CH_C => sync_rx_serdes_rst, + RX_CDR_LOL_CH_S => sync_rx_cdr_lol, + RX_LOS_LOW_CH_S => sync_rx_los_low, + RX_PCS_RST_CH_C => sync_rx_pcs_rst, + WA_POSITION => sync_wa_position_rx(11 downto 8), + STATE_OUT => sync_rx_fsm_state + ); + +SYNC_WA_POSITION : process(sync_rx_full_clk) --??CLK) +begin + if rising_edge(sync_rx_full_clk) then + sync_wa_position_rx <= wa_position; + end if; +end process; + +THE_TX_FSM3 : tx_reset_fsm + port map( + RST_N => reset_n, + TX_REFCLK => OSCCLK, + TX_PLL_LOL_QD_S => tx_pll_lol_qd_i, + RST_QD_C => rst_qd3, + TX_PCS_RST_CH_C => sync_tx_pcs_rst, + STATE_OUT => sync_tx_fsm_state + ); + +--rst_qd <= '1' when (rst_qd1='1') or (rst_qd3='1') else '0'; +rst_qd <= RESET; + +TX_READY_CH3 <= '1' when (sync_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0'; + +----------------------------------------------------------------------------------------------------- +-- SCI --gives access to serdes config port from slow control and reads word alignment every ~ 40 us +----------------------------------------------------------------------------------------------------- +PROC_SCI_CTRL: process(clk_sys) + variable cnt : integer range 0 to 4 := 0; +begin + if( rising_edge(clk_sys) ) then + SCI_ACK <= '0'; + case sci_state is + when IDLE => + sci_ch_i <= x"0"; + sci_qd_i <= '0'; + sci_reg_i <= '0'; + sci_read_i <= '0'; + sci_write_i <= '0'; + sci_timer <= sci_timer + 1; + if SCI_READ = '1' or SCI_WRITE = '1' then + sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); + sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); + sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); + sci_addr_i <= SCI_ADDR; + sci_data_in_i <= SCI_DATA_IN; + sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); + sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); + sci_state <= SCTRL; + elsif sci_timer(sci_timer'left) = '1' then + sci_timer <= (others => '0'); + sci_state <= GET_WA; + end if; + when SCTRL => + if sci_reg_i = '1' then + --// SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))); + SCI_DATA_OUT <= (others => '0'); + SCI_ACK <= '1'; + sci_write_i <= '0'; + sci_read_i <= '0'; + sci_state <= IDLE; + else + sci_state <= SCTRL_WAIT; + end if; + when SCTRL_WAIT => + sci_state <= SCTRL_WAIT2; + when SCTRL_WAIT2 => + sci_state <= SCTRL_FINISH; + when SCTRL_FINISH => + SCI_DATA_OUT <= sci_data_out_i; + SCI_ACK <= '1'; + sci_write_i <= '0'; + sci_read_i <= '0'; + sci_state <= IDLE; + + when GET_WA => + if cnt = 4 then + cnt := 0; + sci_state <= IDLE; + else + sci_state <= GET_WA_WAIT; + sci_addr_i <= '0' & x"22"; + sci_ch_i <= x"0"; + sci_ch_i(cnt) <= '1'; + sci_read_i <= '1'; + end if; + when GET_WA_WAIT => + sci_state <= GET_WA_WAIT2; + when GET_WA_WAIT2 => + sci_state <= GET_WA_FINISH; + when GET_WA_FINISH => + wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0); + sci_state <= GET_WA; + cnt := cnt + 1; + end case; + + if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then + SCI_NACK <= '1'; + else + SCI_NACK <= '0'; + end if; + end if; +end process PROC_SCI_CTRL; + +---------------------- +--Generate LED signals +---------------------- +LED_PROC : process( clk_sys ) + begin + if rising_edge(clk_sys) then + led_counter <= led_counter + to_unsigned(1,1); + if buf_med_dataready_out = '1' then + rx_led <= '1'; + elsif led_counter = 0 then + rx_led <= '0'; + end if; + if tx_k(0) = '0' then + tx_led <= '1'; + elsif led_counter = 0 then + tx_led <= '0'; + end if; + end if; + end process LED_PROC; + + +stat_op(15) <= send_reset_words_q; +stat_op(14) <= buf_stat_op(14); +stat_op(13) <= make_trbnet_reset_q; +stat_op(12) <= '0'; +stat_op(11) <= tx_led; --tx led +stat_op(10) <= rx_led; --rx led +stat_op(9 downto 0) <= buf_stat_op(9 downto 0); + +-- Debug output +stat_debug(15 downto 0) <= rx_data; +stat_debug(17 downto 16) <= rx_k; +stat_debug(19 downto 18) <= (others => '0'); +stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0); +stat_debug(24) <= fifo_rx_rd_en; +stat_debug(25) <= fifo_rx_wr_en; +stat_debug(26) <= fifo_rx_reset; +stat_debug(27) <= fifo_rx_empty; +stat_debug(28) <= fifo_rx_full; +stat_debug(29) <= last_rx(8); +stat_debug(30) <= rx_allow_q; +stat_debug(41 downto 31) <= (others => '0'); +stat_debug(42) <= clk_sys; +stat_debug(43) <= clk_sys; +stat_debug(59 downto 44) <= (others => '0'); +stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0); + + +end Cu_trb_net16_soda_syncUP_ecp3_sfp_arch; \ No newline at end of file diff --git a/code/Cu_trb_net16_soda_sync_ecp3_sfp.vhd b/code/Cu_trb_net16_soda_sync_ecp3_sfp.vhd new file mode 100644 index 0000000..7eb154e --- /dev/null +++ b/code/Cu_trb_net16_soda_sync_ecp3_sfp.vhd @@ -0,0 +1,1073 @@ +--Media interface for Lattice ECP3 using PCS at 2GHz + + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; + +entity Cu_trb_net16_soda_sync_ecp3_sfp is + port( + OSCCLK : in std_logic; -- 200 MHz reference clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + --Internal Connection TX + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic := '0'; + --Internal Connection RX + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); + MED_DATAREADY_OUT : out std_logic := '0'; + MED_READ_IN : in std_logic; + + --Copper SFP Connection + CU_RXD_P_IN : in std_logic; + CU_RXD_N_IN : in std_logic; + CU_TXD_P_OUT : out std_logic; + CU_TXD_N_OUT : out std_logic; + CU_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + CU_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + CU_TXDIS_OUT : out std_logic := '0'; -- SFP disable + --Fiber/sync SFP Connection + SYNC_RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + SYNC_DLM_IN : in std_logic; + SYNC_DLM_WORD_IN : in std_logic_vector(7 downto 0); + SYNC_DLM_OUT : out std_logic; + SYNC_DLM_WORD_OUT : out std_logic_vector(7 downto 0); + SYNC_RXD_P_IN : in std_logic; + SYNC_RXD_N_IN : in std_logic; + SYNC_TXD_P_OUT : out std_logic; + SYNC_TXD_N_OUT : out std_logic; + SYNC_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SYNC_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SYNC_TXDIS_OUT : out std_logic := '0'; -- SFP disable + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; + SCI_NACK : out std_logic := '0'; + + TX_READY_CH3 : out std_logic; + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); +end entity; + +architecture Cu_trb_net16_soda_sync_ecp3_sfp_arch of Cu_trb_net16_soda_sync_ecp3_sfp is + + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture is "media_interface_group"; + attribute syn_sharing : string; + attribute syn_sharing of Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture is "off"; + + component sfp_2_200_int + port + ( + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + sci_sel_ch1 : in std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (15 downto 0); + tx_k_ch1 : in std_logic_vector (1 downto 0); + tx_force_disp_ch1 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch1 : in std_logic_vector (1 downto 0); + rxdata_ch1 : out std_logic_vector (15 downto 0); + rx_k_ch1 : out std_logic_vector (1 downto 0); + rx_disp_err_ch1 : out std_logic_vector (1 downto 0); + rx_cv_err_ch1 : out std_logic_vector (1 downto 0); + rx_serdes_rst_ch1_c : in std_logic; + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pcs_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pcs_rst_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; + tx_div2_mode_ch1_c : in std_logic; + rx_div2_mode_ch1_c : in std_logic; + + hdinp_ch3, hdinn_ch3 : in std_logic; + hdoutp_ch3, hdoutn_ch3 : out std_logic; + sci_sel_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + fpga_rxrefclk_ch3 : in std_logic; + txdata_ch3 : in std_logic_vector (7 downto 0); + tx_k_ch3 : in std_logic; + tx_force_disp_ch3 : in std_logic; + tx_disp_sel_ch3 : in std_logic; + rxdata_ch3 : out std_logic_vector (7 downto 0); + rx_k_ch3 : out std_logic; + rx_disp_err_ch3 : out std_logic; + rx_cv_err_ch3 : out std_logic; + rx_serdes_rst_ch3_c : in std_logic; + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + tx_pcs_rst_ch3_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pcs_rst_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch3_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; + tx_div2_mode_ch3_c : in std_logic; + rx_div2_mode_ch3_c : in std_logic; + ---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + tx_sync_qd_c : in std_logic; + rst_qd_c : in std_logic; + refclk2fpga : out std_logic; + serdes_rst_qd_c : in std_logic + ); + end component; + + type t_sync_tx_proc_state is (cSEND_IDLE,cSEND_DLM,cFIFO_READ); + signal sync_tx_proc_state : t_sync_tx_proc_state; + + + signal refck2core : std_logic; + -- signal clock : std_logic; + --reset signals + signal ffc_quad_rst : std_logic; + signal ffc_lane_tx_rst : std_logic; + signal ffc_lane_rx_rst : std_logic; + --serdes connections + signal tx_data : std_logic_vector(15 downto 0); + signal tx_k : std_logic_vector(1 downto 0); + signal rx_data : std_logic_vector(15 downto 0); -- delayed signals + signal rx_k : std_logic_vector(1 downto 0); -- delayed signals + signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP + signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP + signal link_ok : std_logic_vector(0 downto 0); + signal link_error : std_logic_vector(8 downto 0); + signal ff_txhalfclk : std_logic; + signal ff_rxhalfclk : std_logic; + signal ff_rxfullclk : std_logic; + --rx fifo signals + signal fifo_rx_rd_en : std_logic; + signal fifo_rx_wr_en : std_logic; + signal fifo_rx_reset : std_logic; + signal fifo_rx_din : std_logic_vector(17 downto 0); + signal fifo_rx_dout : std_logic_vector(17 downto 0); + signal fifo_rx_full : std_logic; + signal fifo_rx_empty : std_logic; + --tx fifo signals + signal fifo_tx_rd_en : std_logic; + signal fifo_tx_wr_en : std_logic; + signal fifo_tx_reset : std_logic; + signal fifo_tx_din : std_logic_vector(17 downto 0); + signal fifo_tx_dout : std_logic_vector(17 downto 0); + signal fifo_tx_full : std_logic; + signal fifo_tx_empty : std_logic; + signal fifo_tx_almost_full : std_logic; + --rx path + signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal buf_med_dataready_out : std_logic; + signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal last_rx : std_logic_vector(8 downto 0); + signal last_fifo_rx_empty : std_logic; + --tx path + signal last_fifo_tx_empty : std_logic; + --link status + signal rx_k_q : std_logic_vector(1 downto 0); + + signal quad_rst : std_logic; + signal lane_rst : std_logic; + signal tx_allow : std_logic; + signal rx_allow : std_logic; + signal tx_allow_qtx : std_logic; + + signal rx_allow_q : std_logic; -- clock domain changed signal + signal tx_allow_q : std_logic; + signal swap_bytes : std_logic; + signal buf_stat_debug : std_logic_vector(31 downto 0); + + -- status inputs from SFP + signal sfp_prsnt_n : std_logic; -- synchronized input signals + signal sfp_los : std_logic; -- synchronized input signals + + signal buf_STAT_OP : std_logic_vector(15 downto 0); + + signal led_counter : unsigned(16 downto 0); + signal rx_led : std_logic; + signal tx_led : std_logic; + + + signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion + signal first_idle : std_logic; -- tag the first IDLE2 after data + + signal reset_word_cnt : unsigned(4 downto 0); + signal make_trbnet_reset : std_logic; + signal make_trbnet_reset_q : std_logic; + signal send_reset_words : std_logic; + signal send_reset_words_q : std_logic; + signal send_reset_in : std_logic; + signal send_reset_in_qtx : std_logic; + signal reset_i : std_logic; + signal reset_i_rx : std_logic; + signal pwr_up : std_logic; + + signal clk_sys : std_logic; + signal clk_tx : std_logic; + signal clk_rx : std_logic; + signal clk_rxref : std_logic; + signal clk_txref : std_logic; + + -- Peter Schakel 3-dec-2014 + + signal sci_timer : unsigned(12 downto 0) := (others => '0'); + signal reset_n : std_logic; + signal trb_rx_serdes_rst : std_logic; + signal trb_rx_cdr_lol : std_logic; + signal trb_rx_los_low : std_logic; + signal trb_rx_pcs_rst : std_logic; + signal trb_tx_pcs_rst : std_logic; + signal rst_qd : std_logic; + signal rst_qd1 : std_logic; + signal rst_qd3 : std_logic; + signal link_OK_S : std_logic; + signal trb_rx_fsm_state : std_logic_vector(3 downto 0); + signal trb_tx_fsm_state : std_logic_vector(3 downto 0); + signal sync_rx_fsm_state : std_logic_vector(3 downto 0); + signal sync_tx_fsm_state : std_logic_vector(3 downto 0); + signal clk_200_osc : std_logic; + signal sync_rx_full_clk : std_logic; + signal sync_rx_half_clk : std_logic; + signal sync_tx_full_clk : std_logic; + signal sync_tx_half_clk : std_logic; + + signal sync_tx_data : std_logic_vector(7 downto 0); + signal sync_tx_k : std_logic; + signal sync_dlm_in_S : std_logic; + signal sync_rx_data : std_logic_vector(7 downto 0); + signal sync_rx_k : std_logic; + signal sync_rx_error : std_logic; + signal sync_rx_serdes_rst : std_logic; + signal sync_tx_pcs_rst : std_logic; + signal sync_rx_pcs_rst : std_logic; + signal sync_rx_los_low : std_logic; + signal sync_lsm_status : std_logic; + signal sync_rx_cdr_lol : std_logic; + signal dlm_fifo_rd_en : std_logic; + signal dlm_fifo_empty : std_logic; + signal dlm_fifo_reading : std_logic; + signal dlm_received_S : std_logic; + + signal syncfifo_din : std_logic_vector(17 downto 0); + signal syncfifo_dout : std_logic_vector(17 downto 0); + + type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); + signal sci_state : sci_ctrl; + + signal sci_ch_i : std_logic_vector(3 downto 0); + signal sci_qd_i : std_logic; + signal sci_reg_i : std_logic; + signal sci_addr_i : std_logic_vector(8 downto 0); + signal sci_data_in_i : std_logic_vector(7 downto 0); + signal sci_data_out_i : std_logic_vector(7 downto 0); + signal sci_read_i : std_logic; + signal sci_write_i : std_logic; + signal sci_write_shift_i : std_logic_vector(2 downto 0); + signal sci_read_shift_i : std_logic_vector(2 downto 0); + + signal tx_pll_lol_qd_i : std_logic; + + signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; + signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF"; + signal sync_wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF"; + signal sync_tx_allow : std_logic; + signal sync_rx_allow : std_logic; + signal sync_tx_allow_q : std_logic; + signal sync_rx_allow_q : std_logic; + signal link_phase_S : std_logic; --PL! + signal request_retr_i : std_logic; + signal start_retr_i : std_logic; + signal request_retr_position_i : std_logic_vector(7 downto 0); + signal start_retr_position_i : std_logic_vector(7 downto 0); + signal send_link_reset_i : std_logic; + signal make_link_reset_i : std_logic; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + attribute syn_keep of led_counter : signal is true; + attribute syn_keep of send_reset_in : signal is true; + attribute syn_keep of reset_i : signal is true; + attribute syn_preserve of reset_i : signal is true; + attribute syn_preserve of sci_ch_i : signal is true;-- + attribute syn_keep of sci_ch_i : signal is true;-- + attribute syn_preserve of sci_addr_i : signal is true;-- + attribute syn_keep of sci_addr_i : signal is true;-- + attribute syn_preserve of sci_data_in_i : signal is true;-- + attribute syn_keep of sci_data_in_i : signal is true;-- + attribute syn_preserve of sci_data_out_i : signal is true;-- + attribute syn_keep of sci_data_out_i : signal is true;-- + attribute syn_preserve of sci_read_i : signal is true;-- + attribute syn_keep of sci_read_i : signal is true;-- + attribute syn_preserve of sci_write_i : signal is true;-- + attribute syn_keep of sci_write_i : signal is true;-- + attribute syn_preserve of sci_write_shift_i : signal is true;-- + attribute syn_keep of sci_write_shift_i : signal is true;-- + attribute syn_preserve of sci_read_shift_i : signal is true;-- + attribute syn_keep of sci_read_shift_i : signal is true;-- + attribute syn_preserve of wa_position : signal is true;-- + attribute syn_keep of wa_position : signal is true;-- + attribute syn_preserve of wa_position_rx : signal is true;-- + attribute syn_keep of wa_position_rx : signal is true;-- + +begin + +clk_200_osc <= OSCCLK; + +SYNC_RX_HALF_CLK_OUT <= sync_rx_half_clk; +SYNC_RX_FULL_CLK_OUT <= sync_rx_full_clk; +SYNC_TX_HALF_CLK_OUT <= sync_tx_half_clk; +SYNC_TX_FULL_CLK_OUT <= sync_tx_full_clk; +--RX_CDR_LOL_OUT <= rx_cdr_lol; + +clk_sys <= SYSCLK; +clk_tx <= SYSCLK; +clk_rx <= ff_rxhalfclk; +clk_rxref <= OSCCLK; +clk_txref <= OSCCLK; + +--sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL! + +-------------------------------------------------------------------------- +-- Internal Lane Resets +-------------------------------------------------------------------------- + PROC_RESET : process(clk_sys) + begin + if rising_edge(clk_sys) then + reset_i <= RESET; + send_reset_in <= ctrl_op(15); + pwr_up <= '1'; --not CTRL_OP(i*16+14); + end if; + end process; + +-------------------------------------------------------------------------- +-- Synchronizer stages +-------------------------------------------------------------------------- + +-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP) +THE_SFP_STATUS_SYNC: signal_sync + generic map( + DEPTH => 3, + WIDTH => 2 + ) + port map( + RESET => '0', + D_IN(0) => sync_prsnt_n_in, + D_IN(1) => sync_los_in, + CLK0 => clk_sys, + CLK1 => clk_sys, + D_OUT(0) => sfp_prsnt_n, + D_OUT(1) => sfp_los + ); + + +THE_RX_K_SYNC: signal_sync + generic map( + DEPTH => 1, + WIDTH => 4 + ) + port map( + RESET => reset_i, + D_IN(1 downto 0) => comb_rx_k, + D_IN(2) => send_reset_words, + D_IN(3) => make_trbnet_reset, + CLK0 => clk_rx, -- CHANGED + CLK1 => clk_sys, + D_OUT(1 downto 0) => rx_k_q, + D_OUT(2) => send_reset_words_q, + D_OUT(3) => make_trbnet_reset_q + ); + +THE_RX_DATA_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 16 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_data, + CLK0 => clk_rx, + CLK1 => clk_rx, + D_OUT => rx_data + ); + +THE_RX_K_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_k, + CLK0 => clk_rx, + CLK1 => clk_rx, + D_OUT => rx_k + ); + +THE_RX_RESET: signal_sync + generic map( + DEPTH => 1, + WIDTH => 1 + ) + port map( + RESET => '0', + D_IN(0) => reset_i, + CLK0 => clk_rx, + CLK1 => clk_rx, + D_OUT(0) => reset_i_rx + ); + +-- Delay for ALLOW signals +THE_RX_ALLOW_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset_i, + D_IN(0) => rx_allow, + D_IN(1) => tx_allow, + CLK0 => clk_sys, + CLK1 => clk_sys, + D_OUT(0) => rx_allow_q, + D_OUT(1) => tx_allow_q + ); + +THE_TX_SYNC: signal_sync + generic map( + DEPTH => 1, + WIDTH => 2 + ) + port map( + RESET => '0', + D_IN(0) => send_reset_in, + D_IN(1) => tx_allow, + CLK0 => clk_tx, + CLK1 => clk_tx, + D_OUT(0) => send_reset_in_qtx, + D_OUT(1) => tx_allow_qtx + ); + +--THE_DLM_IN_DELAY: signal_sync +-- generic map( +-- DEPTH => 1, +-- WIDTH => 1 +-- ) +-- port map( +-- RESET => '0', +-- D_IN(0) => SYNC_DLM_IN, +-- CLK0 => sync_rx_full_clk, +-- CLK1 => sync_rx_full_clk, +-- D_OUT(0) => sync_dlm_in_S +-- ); +-------------------------------------------------------------------------- +-- Main control state machine, startup control for SFP +-------------------------------------------------------------------------- + +THE_SFP_LSM: trb_net16_lsm_sfp + generic map ( + HIGHSPEED_STARTUP => c_YES + ) + port map( + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear, + SFP_MISSING_IN => sfp_prsnt_n, + SFP_LOS_IN => sfp_los, + SD_LINK_OK_IN => link_ok(0), + SD_LOS_IN => link_error(8), + SD_TXCLK_BAD_IN => link_error(5), + SD_RXCLK_BAD_IN => link_error(4), + SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN => rx_k_q, + SD_CV_IN => link_error(7 downto 6), + FULL_RESET_OUT => quad_rst, + LANE_RESET_OUT => lane_rst, + TX_ALLOW_OUT => tx_allow, + RX_ALLOW_OUT => rx_allow, + SWAP_BYTES_OUT => swap_bytes, + STAT_OP => buf_stat_op, + CTRL_OP => ctrl_op, + STAT_DEBUG => buf_stat_debug + ); + +SYNC_TXDIS_OUT <= quad_rst or reset_i; + +-------------------------------------------------------------------------- +-------------------------------------------------------------------------- + +ffc_quad_rst <= quad_rst; +ffc_lane_tx_rst <= lane_rst; + + +ffc_lane_rx_rst <= lane_rst; + + + +-- Instantiation of serdes module + + THE_SERDES: sfp_2_200_int + port map( + HDINP_CH1 => CU_RXD_P_IN, + HDINN_CH1 => CU_RXD_N_IN, + HDOUTP_CH1 => CU_TXD_P_OUT, + HDOUTN_CH1 => CU_TXD_N_OUT, + SCI_SEL_CH1 => sci_ch_i(1), + RXICLK_CH1 => clk_rx, + TXICLK_CH1 => clk_tx, + RX_FULL_CLK_CH1 => ff_rxfullclk, + RX_HALF_CLK_CH1 => ff_rxhalfclk, + TX_FULL_CLK_CH1 => open, + TX_HALF_CLK_CH1 => ff_txhalfclk, + FPGA_RXREFCLK_CH1 => clk_rxref, + TXDATA_CH1 => tx_data, + TX_K_CH1 => tx_k, + TX_FORCE_DISP_CH1 => tx_correct, + TX_DISP_SEL_CH1 => "00", + RXDATA_CH1 => comb_rx_data, + RX_K_CH1 => comb_rx_k, + RX_DISP_ERR_CH1 => open, + RX_CV_ERR_CH1 => link_error(7 downto 6), + RX_SERDES_RST_CH1_C => trb_rx_serdes_rst, + SB_FELB_CH1_C => '0', --loopback enable + SB_FELB_RST_CH1_C => '0', --loopback reset + TX_PCS_RST_CH1_C => trb_tx_pcs_rst, --'1', --tx power up + TX_PWRUP_CH1_C => '1', --tx power up + RX_PCS_RST_CH1_C => trb_rx_pcs_rst, --'1', --rx power up + RX_PWRUP_CH1_C => '1', --rx power up + RX_LOS_LOW_CH1_S => trb_rx_los_low, --link_error(8), + LSM_STATUS_CH1_S => link_ok(0), + RX_CDR_LOL_CH1_S => trb_rx_cdr_lol, --link_error(4), + TX_DIV2_MODE_CH1_C => '0', --full rate + RX_DIV2_MODE_CH1_C => '0', --full rate + + HDINP_CH3 => SYNC_RXD_P_IN, + HDINN_CH3 => SYNC_RXD_N_IN, + HDOUTP_CH3 => SYNC_TXD_P_OUT, + HDOUTN_CH3 => SYNC_TXD_N_OUT, + SCI_SEL_CH3 => sci_ch_i(3), + TXICLK_CH3 => sync_rx_full_clk, + RX_FULL_CLK_CH3 => sync_rx_full_clk, + RX_HALF_CLK_CH3 => sync_rx_half_clk, + TX_FULL_CLK_CH3 => sync_tx_full_clk, + TX_HALF_CLK_CH3 => sync_tx_half_clk, + FPGA_RXREFCLK_CH3 => clk_200_osc, + TXDATA_CH3 => sync_tx_data, + TX_K_CH3 => sync_tx_k, + TX_FORCE_DISP_CH3 => '0', + TX_DISP_SEL_CH3 => '0', + RXDATA_CH3 => sync_rx_data, + RX_K_CH3 => sync_rx_k, + RX_DISP_ERR_CH3 => open, + RX_CV_ERR_CH3 => sync_rx_error, + RX_SERDES_RST_CH3_C => sync_rx_serdes_rst, + SB_FELB_CH3_C => '0', --loopback enable + SB_FELB_RST_CH3_C => '0', --loopback reset + TX_PCS_RST_CH3_C => sync_tx_pcs_rst, + TX_PWRUP_CH3_C => '1', + RX_PCS_RST_CH3_C => sync_rx_pcs_rst, + RX_PWRUP_CH3_C => '1', + RX_LOS_LOW_CH3_S => sync_rx_los_low, + LSM_STATUS_CH3_S => sync_lsm_status, + RX_CDR_LOL_CH3_S => sync_rx_cdr_lol, + TX_DIV2_MODE_CH3_C => '0', + RX_DIV2_MODE_CH3_C => '0', + + SCI_WRDATA => sci_data_in_i, + SCI_ADDR => sci_addr_i(5 downto 0), + SCI_RDDATA => sci_data_out_i, + SCI_SEL_QUAD => sci_addr_i(8), + SCI_RD => sci_read_i, + SCI_WRN => sci_write_i, + FPGA_TXREFCLK => clk_txref, +-- FPGA_TXREFCLK => rx_full_clk, + TX_SERDES_RST_C => CLEAR, + TX_PLL_LOL_QD_S => link_error(5), + TX_SYNC_QD_C => '0', + RST_QD_C => rst_qd, + REFCLK2FPGA => open, + SERDES_RST_QD_C => ffc_quad_rst + ); + +------------------------------------------------------------------------- +-- RX Fifo & Data output +------------------------------------------------------------------------- +THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport +generic map( + USE_STATUS_FLAGS => c_NO + ) +port map( read_clock_in => clk_sys, + write_clock_in => clk_rx, -- CHANGED + read_enable_in => fifo_rx_rd_en, + write_enable_in => fifo_rx_wr_en, + fifo_gsr_in => fifo_rx_reset, + write_data_in => fifo_rx_din, + read_data_out => fifo_rx_dout, + full_out => fifo_rx_full, + empty_out => fifo_rx_empty + ); + +fifo_rx_reset <= reset_i or not rx_allow_q; +fifo_rx_rd_en <= not fifo_rx_empty; + +-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path +THE_BYTE_SWAP_PROC: process + begin + wait until rising_edge(clk_rx); --CHANGED + last_rx <= rx_k(1) & rx_data(15 downto 8); + if( swap_bytes = '0' ) then + fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0); + fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0); + else + fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0); + fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0); + end if; + end process THE_BYTE_SWAP_PROC; + +buf_med_data_out <= fifo_rx_dout(15 downto 0); +buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q; +buf_med_packet_num_out <= rx_counter; +med_read_out <= tx_allow_q and not fifo_tx_almost_full; + + +THE_CNT_RESET_PROC : process + begin + wait until rising_edge(clk_rx); --CHANGED + if reset_i_rx = '1' then + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + reset_word_cnt <= (others => '0'); + else + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + if fifo_rx_din = "11" & x"FEFE" then + if reset_word_cnt(4) = '0' then + reset_word_cnt <= reset_word_cnt + to_unsigned(1,1); + else + send_reset_words <= '1'; + end if; + else + reset_word_cnt <= (others => '0'); + make_trbnet_reset <= reset_word_cnt(4); + end if; + end if; + end process; + + +THE_SYNC_PROC: process + begin + wait until rising_edge(clk_sys); + med_dataready_out <= buf_med_dataready_out; + med_data_out <= buf_med_data_out; + med_packet_num_out <= buf_med_packet_num_out; + if reset_i = '1' then + med_dataready_out <= '0'; + end if; + end process; + + +--rx packet counter +--------------------- +THE_RX_PACKETS_PROC: process( clk_sys ) + begin + if( rising_edge(clk_sys) ) then + last_fifo_rx_empty <= fifo_rx_empty; + if reset_i = '1' or rx_allow_q = '0' then + rx_counter <= c_H0; + else + if( buf_med_dataready_out = '1' ) then + if( rx_counter = c_max_word_number ) then + rx_counter <= (others => '0'); + else + rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1)); + end if; + end if; + end if; + end if; + end process; + +--TX Fifo & Data output to Serdes +--------------------- +THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( read_clock_in => clk_tx, + write_clock_in => clk_sys, + read_enable_in => fifo_tx_rd_en, + write_enable_in => fifo_tx_wr_en, + fifo_gsr_in => fifo_tx_reset, + write_data_in => fifo_tx_din, + read_data_out => fifo_tx_dout, + full_out => fifo_tx_full, + empty_out => fifo_tx_empty, + almost_full_out => fifo_tx_almost_full + ); + +fifo_tx_reset <= reset_i or not tx_allow_q; +fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in; +fifo_tx_wr_en <= med_dataready_in and tx_allow_q; +fifo_tx_rd_en <= tx_allow_qtx; + + +THE_SERDES_INPUT_PROC: process( clk_tx ) + begin + if( rising_edge(clk_tx) ) then + last_fifo_tx_empty <= fifo_tx_empty; + first_idle <= not last_fifo_tx_empty and fifo_tx_empty; + if send_reset_in = '1' then + tx_data <= x"FEFE"; + tx_k <= "11"; + elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then + tx_data <= x"50bc"; + tx_k <= "01"; + tx_correct <= first_idle & '0'; + else + tx_data <= fifo_tx_dout(15 downto 0); + tx_k <= "00"; + tx_correct <= "00"; + end if; + end if; + end process THE_SERDES_INPUT_PROC; + + +-- map 8-bit dlm on 18-bit fifo +syncfifo_din(7 downto 0) <= SYNC_DLM_WORD_IN; +syncfifo_din(17 downto 8) <= (others => '0'); +--SYNC_DLM_word_S <= syncfifo_dout(7 downto 0); + +SYNC_DLM_tx: trb_net_fifo_16bit_bram_dualport + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( + read_clock_in => sync_tx_full_clk, + write_clock_in => sync_rx_full_clk, + read_enable_in => dlm_fifo_rd_en, + write_enable_in => SYNC_DLM_IN, --sync_dlm_in_S, + fifo_gsr_in => reset, + write_data_in => syncfifo_din, + read_data_out => syncfifo_dout, + full_out => open, + empty_out => dlm_fifo_empty + ); + +sync_rx_proc : process(sync_rx_full_clk) +begin + if rising_edge(sync_rx_full_clk) then + SYNC_DLM_OUT <= '0'; + if dlm_received_S='1' then + dlm_received_S <= '0'; + SYNC_DLM_OUT <= '1'; + SYNC_DLM_WORD_OUT <= sync_rx_data; + elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then + dlm_received_S <= '1'; + end if; + end if; +end process; + +sync_tx_fsm : process(sync_tx_full_clk) +begin + if rising_edge(sync_tx_full_clk) then + case sync_tx_proc_state is + when cSEND_IDLE => + if (dlm_fifo_empty='1') then + sync_tx_proc_state <= cSEND_IDLE; + dlm_fifo_rd_en <= '0'; + sync_tx_data <= x"BC"; -- idle + sync_tx_k <= '1'; + else + sync_tx_proc_state <= cFIFO_READ; + dlm_fifo_rd_en <= '1'; + sync_tx_data <= x"BC"; -- dlm + sync_tx_k <= '1'; + end if; + when cFIFO_READ => + sync_tx_proc_state <= cSEND_DLM; + dlm_fifo_rd_en <= '0'; + sync_tx_data <= x"DC"; -- dlm + sync_tx_k <= '1'; + when cSEND_DLM => + sync_tx_proc_state <= cSEND_IDLE; + dlm_fifo_rd_en <= '0'; + sync_tx_data <= syncfifo_dout(7 downto 0); + sync_tx_k <= '0'; + when others => + sync_tx_proc_state <= cSEND_IDLE; + dlm_fifo_rd_en <= '0'; + sync_tx_data <= x"BC"; -- idle + sync_tx_k <= '1'; + end case; + end if; +end process; + + +--sync_tx_proc : process(sync_tx_full_clk) +--begin + --if rising_edge(sync_tx_full_clk) then + --if dlm_fifo_rd_en='1' then + --dlm_fifo_rd_en <= '0'; + --sync_tx_data <= syncfifo_dout(7 downto 0); + --sync_tx_k <= '0'; + --elsif (dlm_fifo_empty='0') and (dlm_fifo_reading='1') then + --dlm_fifo_rd_en <= '1'; + --sync_tx_data <= x"DC"; + --sync_tx_k <= '1'; + --elsif dlm_fifo_empty='0' then + --dlm_fifo_reading <= '1'; + --dlm_fifo_rd_en <= '0'; + --sync_tx_data <= x"BC"; -- idle + --sync_tx_k <= '1'; + --else + --dlm_fifo_reading <= '0'; + --dlm_fifo_rd_en <= '0'; + --sync_tx_data <= x"BC"; -- idle + --sync_tx_k <= '1'; + --end if; + --end if; +--end process; + +link_error(8) <= trb_rx_los_low; -- loss of signal +link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock +link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock + +reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1'; + +------------------------------------------------- +-- Reset FSM & Link states +------------------------------------------------- +THE_RX_FSM1: rx_reset_fsm + port map( + RST_N => reset_n, + RX_REFCLK => OSCCLK, + TX_PLL_LOL_QD_S => tx_pll_lol_qd_i, + RX_SERDES_RST_CH_C => trb_rx_serdes_rst, + RX_CDR_LOL_CH_S => trb_rx_cdr_lol, + RX_LOS_LOW_CH_S => trb_rx_los_low, + RX_PCS_RST_CH_C => trb_rx_pcs_rst, + WA_POSITION => "0000", + STATE_OUT => trb_rx_fsm_state + ); + +link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0'; + +THE_TX_FSM1: tx_reset_fsm + port map( + RST_N => reset_n, + TX_REFCLK => OSCCLK, + TX_PLL_LOL_QD_S => tx_pll_lol_qd_i, + RST_QD_C => rst_qd1, + TX_PCS_RST_CH_C => trb_tx_pcs_rst, + STATE_OUT => trb_tx_fsm_state --open + ); + +THE_RX_FSM3: rx_reset_fsm + port map( + RST_N => reset_n, + RX_REFCLK => sync_rx_full_clk, + TX_PLL_LOL_QD_S => tx_pll_lol_qd_i, + RX_SERDES_RST_CH_C => sync_rx_serdes_rst, + RX_CDR_LOL_CH_S => sync_rx_cdr_lol, + RX_LOS_LOW_CH_S => sync_rx_los_low, + RX_PCS_RST_CH_C => sync_rx_pcs_rst, + WA_POSITION => sync_wa_position_rx(11 downto 8), + STATE_OUT => sync_rx_fsm_state + ); + +SYNC_WA_POSITION : process(sync_rx_full_clk) --??CLK) +begin + if rising_edge(sync_rx_full_clk) then + sync_wa_position_rx <= wa_position; + end if; +end process; + +THE_TX_FSM3 : tx_reset_fsm + port map( + RST_N => reset_n, + TX_REFCLK => OSCCLK, + TX_PLL_LOL_QD_S => tx_pll_lol_qd_i, + RST_QD_C => rst_qd3, + TX_PCS_RST_CH_C => sync_tx_pcs_rst, + STATE_OUT => sync_tx_fsm_state + ); + +--rst_qd <= '1' when (rst_qd1='1') or (rst_qd3='1') else '0'; +rst_qd <= RESET; + +TX_READY_CH3 <= '1' when (sync_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0'; + +----------------------------------------------------------------------------------------------------- +-- SCI --gives access to serdes config port from slow control and reads word alignment every ~ 40 us +----------------------------------------------------------------------------------------------------- +PROC_SCI_CTRL: process(clk_sys) + variable cnt : integer range 0 to 4 := 0; +begin + if( rising_edge(clk_sys) ) then + SCI_ACK <= '0'; + case sci_state is + when IDLE => + sci_ch_i <= x"0"; + sci_qd_i <= '0'; + sci_reg_i <= '0'; + sci_read_i <= '0'; + sci_write_i <= '0'; + sci_timer <= sci_timer + 1; + if SCI_READ = '1' or SCI_WRITE = '1' then + sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); + sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); + sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); + sci_addr_i <= SCI_ADDR; + sci_data_in_i <= SCI_DATA_IN; + sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); + sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); + sci_state <= SCTRL; + elsif sci_timer(sci_timer'left) = '1' then + sci_timer <= (others => '0'); + sci_state <= GET_WA; + end if; + when SCTRL => + if sci_reg_i = '1' then + --// SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))); + SCI_DATA_OUT <= (others => '0'); + SCI_ACK <= '1'; + sci_write_i <= '0'; + sci_read_i <= '0'; + sci_state <= IDLE; + else + sci_state <= SCTRL_WAIT; + end if; + when SCTRL_WAIT => + sci_state <= SCTRL_WAIT2; + when SCTRL_WAIT2 => + sci_state <= SCTRL_FINISH; + when SCTRL_FINISH => + SCI_DATA_OUT <= sci_data_out_i; + SCI_ACK <= '1'; + sci_write_i <= '0'; + sci_read_i <= '0'; + sci_state <= IDLE; + + when GET_WA => + if cnt = 4 then + cnt := 0; + sci_state <= IDLE; + else + sci_state <= GET_WA_WAIT; + sci_addr_i <= '0' & x"22"; + sci_ch_i <= x"0"; + sci_ch_i(cnt) <= '1'; + sci_read_i <= '1'; + end if; + when GET_WA_WAIT => + sci_state <= GET_WA_WAIT2; + when GET_WA_WAIT2 => + sci_state <= GET_WA_FINISH; + when GET_WA_FINISH => + wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0); + sci_state <= GET_WA; + cnt := cnt + 1; + end case; + + if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then + SCI_NACK <= '1'; + else + SCI_NACK <= '0'; + end if; + end if; +end process PROC_SCI_CTRL; + +---------------------- +--Generate LED signals +---------------------- +LED_PROC : process( clk_sys ) + begin + if rising_edge(clk_sys) then + led_counter <= led_counter + to_unsigned(1,1); + if buf_med_dataready_out = '1' then + rx_led <= '1'; + elsif led_counter = 0 then + rx_led <= '0'; + end if; + if tx_k(0) = '0' then + tx_led <= '1'; + elsif led_counter = 0 then + tx_led <= '0'; + end if; + end if; + end process LED_PROC; + + +stat_op(15) <= send_reset_words_q; +stat_op(14) <= buf_stat_op(14); +stat_op(13) <= make_trbnet_reset_q; +stat_op(12) <= '0'; +stat_op(11) <= tx_led; --tx led +stat_op(10) <= rx_led; --rx led +stat_op(9 downto 0) <= buf_stat_op(9 downto 0); + +-- Debug output +stat_debug(15 downto 0) <= rx_data; +stat_debug(17 downto 16) <= rx_k; +stat_debug(19 downto 18) <= (others => '0'); +stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0); +stat_debug(24) <= fifo_rx_rd_en; +stat_debug(25) <= fifo_rx_wr_en; +stat_debug(26) <= fifo_rx_reset; +stat_debug(27) <= fifo_rx_empty; +stat_debug(28) <= fifo_rx_full; +stat_debug(29) <= last_rx(8); +stat_debug(30) <= rx_allow_q; +stat_debug(41 downto 31) <= (others => '0'); +stat_debug(42) <= clk_sys; +stat_debug(43) <= clk_sys; +stat_debug(59 downto 44) <= (others => '0'); +stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0); + + +end Cu_trb_net16_soda_sync_ecp3_sfp_arch; \ No newline at end of file diff --git a/code/ip/serdes_4_sync_downstream.ipx b/code/ip/serdes_4_sync_downstream.ipx index 2b7f836..4665264 100644 --- a/code/ip/serdes_4_sync_downstream.ipx +++ b/code/ip/serdes_4_sync_downstream.ipx @@ -1,8 +1,11 @@ - + - - - + + + + + + diff --git a/code/ip/serdes_4_sync_downstream.lpc b/code/ip/serdes_4_sync_downstream.lpc index e480fca..d4653b9 100644 --- a/code/ip/serdes_4_sync_downstream.lpc +++ b/code/ip/serdes_4_sync_downstream.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PCS -CoreRevision=8.1 +CoreRevision=8.2 ModuleName=serdes_4_sync_downstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=09/01/2014 -Time=11:06:05 +Date=02/19/2015 +Time=11:41:22 [Parameters] Verilog=0 diff --git a/code/ip/sfp_1_200_int.ipx b/code/ip/sfp_1_200_int.ipx index ea797de..951f7ad 100644 --- a/code/ip/sfp_1_200_int.ipx +++ b/code/ip/sfp_1_200_int.ipx @@ -1,10 +1,11 @@ - + - - - - - + + + + + + diff --git a/code/ip/sfp_1_200_int.lpc b/code/ip/sfp_1_200_int.lpc index 7963158..0b4f6ab 100644 --- a/code/ip/sfp_1_200_int.lpc +++ b/code/ip/sfp_1_200_int.lpc @@ -16,8 +16,8 @@ CoreRevision=8.2 ModuleName=sfp_1_200_int SourceFormat=VHDL ParameterFileVersion=1.0 -Date=12/04/2014 -Time=09:44:40 +Date=02/11/2015 +Time=09:38:25 [Parameters] Verilog=0 @@ -30,7 +30,7 @@ IO=0 _mode0=DISABLED _mode1=RXTX _mode2=DISABLED -_mode3=RXTX +_mode3=DISABLED _protocol0=G8B10B _protocol1=G8B10B _protocol2=G8B10B @@ -46,7 +46,7 @@ _refclk_rate=200 _tx_protocol0=DISABLED _tx_protocol1=G8B10B _tx_protocol2=DISABLED -_tx_protocol3=G8B10B +_tx_protocol3=DISABLED _tx_data_rate0=FULL _tx_data_rate1=FULL _tx_data_rate2=FULL @@ -78,7 +78,7 @@ _rx_datarange3=2 _rx_protocol0=DISABLED _rx_protocol1=G8B10B _rx_protocol2=DISABLED -_rx_protocol3=G8B10B +_rx_protocol3=DISABLED _rx_data_rate0=FULL _rx_data_rate1=FULL _rx_data_rate2=FULL diff --git a/code/ip/sfp_1_200_int.txt b/code/ip/sfp_1_200_int.txt index 82c5a8a..8db08f2 100644 --- a/code/ip/sfp_1_200_int.txt +++ b/code/ip/sfp_1_200_int.txt @@ -5,88 +5,53 @@ DEVICE_NAME "LFE3-150EA" CH1_PROTOCOL "G8B10B" -CH3_PROTOCOL "G8B10B" CH0_MODE "DISABLED" CH1_MODE "RXTX" CH2_MODE "DISABLED" -CH3_MODE "RXTX" +CH3_MODE "DISABLED" CH1_CDR_SRC "REFCLK_CORE" -CH3_CDR_SRC "REFCLK_CORE" PLL_SRC "REFCLK_CORE" TX_DATARATE_RANGE "MEDHIGH" CH1_RX_DATARATE_RANGE "MEDHIGH" -CH3_RX_DATARATE_RANGE "MEDHIGH" REFCK_MULT "10X" #REFCLK_RATE 200 CH1_RX_DATA_RATE "FULL" -CH3_RX_DATA_RATE "FULL" CH1_TX_DATA_RATE "FULL" -CH3_TX_DATA_RATE "FULL" CH1_TX_DATA_WIDTH "16" -CH3_TX_DATA_WIDTH "8" CH1_RX_DATA_WIDTH "16" -CH3_RX_DATA_WIDTH "8" CH1_TX_FIFO "ENABLED" -CH3_TX_FIFO "DISABLED" CH1_RX_FIFO "ENABLED" -CH3_RX_FIFO "DISABLED" CH1_TDRV "0" -CH3_TDRV "0" #CH1_TX_FICLK_RATE 100 -#CH3_TX_FICLK_RATE 200 #CH1_RXREFCLK_RATE "200" -#CH3_RXREFCLK_RATE "200" #CH1_RX_FICLK_RATE 100 -#CH3_RX_FICLK_RATE 200 CH1_TX_PRE "DISABLED" -CH3_TX_PRE "DISABLED" CH1_RTERM_TX "50" -CH3_RTERM_TX "50" CH1_RX_EQ "DISABLED" -CH3_RX_EQ "DISABLED" CH1_RTERM_RX "50" -CH3_RTERM_RX "50" CH1_RX_DCC "DC" -CH3_RX_DCC "DC" CH1_LOS_THRESHOLD_LO "2" -CH3_LOS_THRESHOLD_LO "2" PLL_TERM "50" PLL_DCC "AC" PLL_LOL_SET "0" CH1_TX_SB "DISABLED" -CH3_TX_SB "DISABLED" CH1_RX_SB "DISABLED" -CH3_RX_SB "DISABLED" CH1_TX_8B10B "ENABLED" -CH3_TX_8B10B "ENABLED" CH1_RX_8B10B "ENABLED" -CH3_RX_8B10B "ENABLED" CH1_COMMA_A "1100000101" -CH3_COMMA_A "1100000101" CH1_COMMA_B "0011111010" -CH3_COMMA_B "0011111010" CH1_COMMA_M "1111111100" -CH3_COMMA_M "1111111100" CH1_RXWA "ENABLED" -CH3_RXWA "ENABLED" CH1_ILSM "ENABLED" -CH3_ILSM "ENABLED" CH1_CTC "DISABLED" -CH3_CTC "DISABLED" CH1_CC_MATCH4 "0100011100" -CH3_CC_MATCH4 "0000000000" CH1_CC_MATCH_MODE "1" -CH3_CC_MATCH_MODE "1" CH1_CC_MIN_IPG "3" -CH3_CC_MIN_IPG "3" CCHMARK "9" CCLMARK "7" CH1_SSLB "DISABLED" -CH3_SSLB "DISABLED" CH1_SPLBPORTS "DISABLED" -CH3_SPLBPORTS "DISABLED" CH1_PCSLBPORTS "DISABLED" -CH3_PCSLBPORTS "DISABLED" INT_ALL "DISABLED" QD_REFCK2CORE "ENABLED" diff --git a/code/ip/sfp_1_200_int.vhd b/code/ip/sfp_1_200_int.vhd index 79dfc86..1dda35d 100644 --- a/code/ip/sfp_1_200_int.vhd +++ b/code/ip/sfp_1_200_int.vhd @@ -1952,32 +1952,6 @@ entity sfp_1_200_int is rx_div2_mode_ch1_c : in std_logic; -- CH2 -- -- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (7 downto 0); - tx_k_ch3 : in std_logic; - tx_force_disp_ch3 : in std_logic; - tx_disp_sel_ch3 : in std_logic; - rxdata_ch3 : out std_logic_vector (7 downto 0); - rx_k_ch3 : out std_logic; - rx_disp_err_ch3 : out std_logic; - rx_cv_err_ch3 : out std_logic; - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ---- Miscillaneous ports sci_wrdata : in std_logic_vector (7 downto 0); sci_addr : in std_logic_vector (5 downto 0); @@ -1988,7 +1962,6 @@ entity sfp_1_200_int is fpga_txrefclk : in std_logic; tx_serdes_rst_c : in std_logic; tx_pll_lol_qd_s : out std_logic; - tx_sync_qd_c : in std_logic; refclk2fpga : out std_logic; rst_n : in std_logic; serdes_rst_qd_c : in std_logic); @@ -2538,8 +2511,6 @@ end component; attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; attribute CH1_CDR_SRC: string; attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute CH3_CDR_SRC: string; - attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200"; attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; @@ -2583,7 +2554,6 @@ signal fpsc_vhi : std_logic := '1'; signal cin : std_logic_vector (11 downto 0) := "000000000000"; signal cout : std_logic_vector (19 downto 0); signal tx_full_clk_ch1_sig : std_logic; -signal tx_full_clk_ch3_sig : std_logic; signal refclk2fpga_sig : std_logic; signal tx_pll_lol_qd_sig : std_logic; @@ -2597,13 +2567,10 @@ signal rx_cdr_lol_ch2_sig : std_logic; signal rx_cdr_lol_ch3_sig : std_logic; signal rx_serdes_rst_ch1_c : std_logic; -signal rx_serdes_rst_ch3_c : std_logic; signal rx_pcs_rst_ch1_c : std_logic; -signal rx_pcs_rst_ch3_c : std_logic; -- reset sequence for rx signal refclkdiv2_rx_ch1 : std_logic; -signal refclkdiv2_rx_ch3 : std_logic; signal refclkdiv2_tx_ch : std_logic; signal tx_pcs_rst_ch_c : std_logic; @@ -2617,12 +2584,9 @@ vhi_inst : VHI port map(Z => fpsc_vhi); refclk2fpga <= refclk2fpga_sig; rx_los_low_ch1_s <= rx_los_low_ch1_sig; - rx_los_low_ch3_s <= rx_los_low_ch3_sig; rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig; - rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig; tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; tx_full_clk_ch1 <= tx_full_clk_ch1_sig; - tx_full_clk_ch3 <= tx_full_clk_ch3_sig; -- pcs_quad instance PCSD_INST : PCSD @@ -2630,7 +2594,6 @@ PCSD_INST : PCSD generic map (CONFIG_FILE => USER_CONFIG_FILE, QUAD_MODE => "SINGLE", CH1_CDR_SRC => "REFCLK_CORE", - CH3_CDR_SRC => "REFCLK_CORE", PLL_SRC => "REFCLK_CORE" ) --synopsys translate_on @@ -2957,10 +2920,10 @@ port map ( FFC_RATE_MODE_RX_2 => fpsc_vlo, ----- CH3 ----- - HDOUTP3 => hdoutp_ch3, - HDOUTN3 => hdoutn_ch3, - HDINP3 => hdinp_ch3, - HDINN3 => hdinn_ch3, + HDOUTP3 => open, + HDOUTN3 => open, + HDINP3 => fpsc_vlo, + HDINN3 => fpsc_vlo, PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, PCIE_TXCOMPLIANCE_3 => fpsc_vlo, PCIE_RXPOLARITY_3 => fpsc_vlo, @@ -2968,27 +2931,27 @@ port map ( PCIE_POWERDOWN_3_1 => fpsc_vlo, PCIE_RXVALID_3 => open, PCIE_PHYSTATUS_3 => open, - SCISELCH3 => sci_sel_ch3, - SCIENCH3 => fpsc_vhi, + SCISELCH3 => fpsc_vlo, + SCIENCH3 => fpsc_vlo, FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => txiclk_ch3, + FF_TXI_CLK_3 => fpsc_vlo, FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => rx_full_clk_ch3, - FF_RX_H_CLK_3 => rx_half_clk_ch3, - FF_TX_F_CLK_3 => tx_full_clk_ch3_sig, - FF_TX_H_CLK_3 => tx_half_clk_ch3, - FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3, - FF_TX_D_3_0 => txdata_ch3(0), - FF_TX_D_3_1 => txdata_ch3(1), - FF_TX_D_3_2 => txdata_ch3(2), - FF_TX_D_3_3 => txdata_ch3(3), - FF_TX_D_3_4 => txdata_ch3(4), - FF_TX_D_3_5 => txdata_ch3(5), - FF_TX_D_3_6 => txdata_ch3(6), - FF_TX_D_3_7 => txdata_ch3(7), - FF_TX_D_3_8 => tx_k_ch3, - FF_TX_D_3_9 => tx_force_disp_ch3, - FF_TX_D_3_10 => tx_disp_sel_ch3, + FF_RX_F_CLK_3 => open, + FF_RX_H_CLK_3 => open, + FF_TX_F_CLK_3 => open, + FF_TX_H_CLK_3 => open, + FFC_CK_CORE_RX_3 => fpsc_vlo, + FF_TX_D_3_0 => fpsc_vlo, + FF_TX_D_3_1 => fpsc_vlo, + FF_TX_D_3_2 => fpsc_vlo, + FF_TX_D_3_3 => fpsc_vlo, + FF_TX_D_3_4 => fpsc_vlo, + FF_TX_D_3_5 => fpsc_vlo, + FF_TX_D_3_6 => fpsc_vlo, + FF_TX_D_3_7 => fpsc_vlo, + FF_TX_D_3_8 => fpsc_vlo, + FF_TX_D_3_9 => fpsc_vlo, + FF_TX_D_3_10 => fpsc_vlo, FF_TX_D_3_11 => fpsc_vlo, FF_TX_D_3_12 => fpsc_vlo, FF_TX_D_3_13 => fpsc_vlo, @@ -3002,17 +2965,17 @@ port map ( FF_TX_D_3_21 => fpsc_vlo, FF_TX_D_3_22 => fpsc_vlo, FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => rxdata_ch3(0), - FF_RX_D_3_1 => rxdata_ch3(1), - FF_RX_D_3_2 => rxdata_ch3(2), - FF_RX_D_3_3 => rxdata_ch3(3), - FF_RX_D_3_4 => rxdata_ch3(4), - FF_RX_D_3_5 => rxdata_ch3(5), - FF_RX_D_3_6 => rxdata_ch3(6), - FF_RX_D_3_7 => rxdata_ch3(7), - FF_RX_D_3_8 => rx_k_ch3, - FF_RX_D_3_9 => rx_disp_err_ch3, - FF_RX_D_3_10 => rx_cv_err_ch3, + FF_RX_D_3_0 => open, + FF_RX_D_3_1 => open, + FF_RX_D_3_2 => open, + FF_RX_D_3_3 => open, + FF_RX_D_3_4 => open, + FF_RX_D_3_5 => open, + FF_RX_D_3_6 => open, + FF_RX_D_3_7 => open, + FF_RX_D_3_8 => open, + FF_RX_D_3_9 => open, + FF_RX_D_3_10 => open, FF_RX_D_3_11 => open, FF_RX_D_3_12 => open, FF_RX_D_3_13 => open, @@ -3027,30 +2990,30 @@ port map ( FF_RX_D_3_22 => open, FF_RX_D_3_23 => open, - FFC_RRST_3 => rx_serdes_rst_ch3_c, + FFC_RRST_3 => fpsc_vlo, FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c, - FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c, + FFC_SB_PFIFO_LP_3 => fpsc_vlo, + FFC_PFIFO_CLR_3 => fpsc_vlo, FFC_SB_INV_RX_3 => fpsc_vlo, FFC_PCIE_CT_3 => fpsc_vlo, FFC_PCI_DET_EN_3 => fpsc_vlo, FFC_FB_LOOPBACK_3 => fpsc_vlo, FFC_ENABLE_CGALIGN_3 => fpsc_vlo, FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => tx_pcs_rst_ch_c, - FFC_TXPWDNB_3 => tx_pwrup_ch3_c, - FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c, - FFC_RXPWDNB_3 => rx_pwrup_ch3_c, - FFS_RLOS_LO_3 => rx_los_low_ch3_sig, + FFC_LANE_TX_RST_3 => fpsc_vlo, + FFC_TXPWDNB_3 => fpsc_vlo, + FFC_LANE_RX_RST_3 => fpsc_vlo, + FFC_RXPWDNB_3 => fpsc_vlo, + FFS_RLOS_LO_3 => open, FFS_RLOS_HI_3 => open, FFS_PCIE_CON_3 => open, FFS_PCIE_DONE_3 => open, - FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s, + FFS_LS_SYNC_STATUS_3 => open, FFS_CC_OVERRUN_3 => open, FFS_CC_UNDERRUN_3 => open, FFS_SKP_ADDED_3 => open, FFS_SKP_DELETED_3 => open, - FFS_RLOL_3 => rx_cdr_lol_ch3_sig, + FFS_RLOL_3 => open, FFS_RXFBFIFO_ERROR_3 => open, FFS_TXFBFIFO_ERROR_3 => open, LDR_CORE2TX_3 => fpsc_vlo, @@ -3058,9 +3021,9 @@ port map ( LDR_RX2CORE_3 => open, FFS_CDR_TRAIN_DONE_3 => open, FFC_DIV11_MODE_TX_3 => fpsc_vlo, - FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c, + FFC_RATE_MODE_TX_3 => fpsc_vlo, FFC_DIV11_MODE_RX_3 => fpsc_vlo, - FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c, + FFC_RATE_MODE_RX_3 => fpsc_vlo, ----- Auxilliary ---- SCIWDATA7 => sci_wrdata(7), @@ -3096,7 +3059,7 @@ port map ( FFC_QUAD_RST => rst_qd_c, FFC_TRST => tx_serdes_rst_c, FFS_PLOL => tx_pll_lol_qd_sig, - FFC_SYNC_TOGGLE => tx_sync_qd_c, + FFC_SYNC_TOGGLE => fpsc_vlo, REFCK2CORE => refclk2fpga_sig, CIN0 => fpsc_vlo, CIN1 => fpsc_vlo, @@ -3158,27 +3121,6 @@ port map ( rx_serdes_rst_ch_c => rx_serdes_rst_ch1_c); - P4 : PROCESS(fpga_rxrefclk_ch3, rst_n) - BEGIN - IF (rst_n = '0') THEN - refclkdiv2_rx_ch3 <= '0'; - ELSIF (fpga_rxrefclk_ch3'event and fpga_rxrefclk_ch3 = '1') THEN - refclkdiv2_rx_ch3 <= not refclkdiv2_rx_ch3; - END IF; - END PROCESS; - -rx_reset_sm_ch3 : sfp_1_200_intrx_reset_sm ---synopsys translate_off - generic map (count_index => 4) ---synopsys translate_on -port map ( - refclkdiv2 => refclkdiv2_rx_ch3, - rst_n => rst_n, - rx_cdr_lol_ch_s => rx_cdr_lol_ch3_sig, - rx_los_low_ch_s => rx_los_low_ch3_sig, - tx_pll_lol_qd_s => tx_pll_lol_qd_sig, - rx_pcs_rst_ch_c => rx_pcs_rst_ch3_c, - rx_serdes_rst_ch_c => rx_serdes_rst_ch3_c); P5 : PROCESS(fpga_txrefclk, rst_n) diff --git a/code/med_ecp3_sfp_4_SODA.vhd b/code/med_ecp3_sfp_4_SODA.vhd index ea0669e..cd56fd7 100644 --- a/code/med_ecp3_sfp_4_SODA.vhd +++ b/code/med_ecp3_sfp_4_SODA.vhd @@ -29,10 +29,10 @@ entity med_ecp3_sfp_4_soda is TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz --Sync operation - RX_DLM_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); - RX_DLM_WORD_OUT : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); - TX_DLM_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); - TX_DLM_WORD_IN : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); + RX_DLM_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); + RX_DLM_WORD_OUT : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); + TX_DLM_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); + TX_DLM_WORD_IN : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! @@ -53,12 +53,7 @@ entity med_ecp3_sfp_4_soda is SCI_READ : in std_logic := '0'; SCI_WRITE : in std_logic := '0'; SCI_ACK : out std_logic := '0'; - SCI_NACK : out std_logic := '0'; - -- Status and control port --- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); --- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + SCI_NACK : out std_logic := '0' ); end entity; @@ -76,12 +71,14 @@ architecture med_ecp3_sfp_4_soda_arch of med_ecp3_sfp_4_soda is signal clk_200_osc : std_logic; signal clk_200_txdata : std_logic; ---signal clk_200_rxdn : std_logic_vector(3 downto 0); ---signal clk_200_i : std_logic_vector(3 downto 0); signal rx_full_clk : std_logic_vector(3 downto 0); signal rx_half_clk : std_logic_vector(3 downto 0); signal tx_full_clk : std_logic_vector(3 downto 0); signal tx_half_clk : std_logic_vector(3 downto 0); + +type t_tx_state is (cRESET,cSEND_IDLE,cSEND_DLM); +type t_tx_proc_state is array(c_HUB_CHILDREN-1 downto 0) of t_tx_state; +signal tx_proc_state : t_tx_proc_state; signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); signal tx_k : std_logic_vector(3 downto 0); @@ -100,6 +97,9 @@ signal rst_down_quad : std_logic; signal serdes_rst_qd : t_HUB_BIT; signal serdes_rst_down_quad : std_logic; -- combined serdes reset for whole quad signal sd_los_i : t_HUB_BIT; --PL! + +signal dlm_received_S : t_HUB_BIT; + signal rx_los_low : t_HUB_BIT; signal lsm_status : t_HUB_BIT; @@ -135,8 +135,6 @@ signal got_link_ready_i : t_HUB_BIT; --std_logic_vector(3 downto 0); signal internal_make_link_reset_out : t_HUB_BIT; --std_logic_vector(3 downto 0); signal start_timer : t_HUB_TIMER19 := (others => (others => '0')); --unsigned(18 downto 0) := (others => '0'); -signal watchdog_timer : t_HUB_TIMER21 := (others => (others => '0')); --unsigned(20 downto 0) := (others => '0'); -signal watchdog_trigger : t_HUB_BIT := (others => '0'); --std_logic_vector(3 downto 0) := (others => '0'); signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); @@ -151,6 +149,34 @@ type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GE signal sci_state : sci_ctrl; signal sci_timer : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0) := (others => '0'); +-- fix signal names for constraining +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_useioff : boolean; + +attribute syn_useioff of sd_los_i : signal is false; -- do not use an IOFF for this signal + +attribute syn_preserve of sci_ch_i : signal is true; +attribute syn_keep of sci_ch_i : signal is true; +attribute syn_preserve of sci_qd_i : signal is true; +attribute syn_keep of sci_qd_i : signal is true; +attribute syn_preserve of sci_reg_i : signal is true; +attribute syn_keep of sci_reg_i : signal is true; +attribute syn_preserve of sci_addr_i : signal is true; +attribute syn_keep of sci_addr_i : signal is true; +attribute syn_preserve of sci_data_in_i : signal is true; +attribute syn_keep of sci_data_in_i : signal is true; +attribute syn_preserve of sci_data_out_i : signal is true; +attribute syn_keep of sci_data_out_i : signal is true; +attribute syn_preserve of sci_read_i : signal is true; +attribute syn_keep of sci_read_i : signal is true; +attribute syn_preserve of sci_write_i : signal is true; +attribute syn_keep of sci_write_i : signal is true; +attribute syn_preserve of sci_write_shift_i : signal is true; +attribute syn_keep of sci_write_shift_i : signal is true; +attribute syn_preserve of sci_read_shift_i : signal is true; +attribute syn_keep of sci_read_shift_i : signal is true; + begin @@ -162,8 +188,8 @@ clk_200_txdata <= TX_DATACLK; -- This external clock is the rx_full of the upl gen_clocks : for i in 0 to 3 generate - rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); - rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); + rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i)); + rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i)); RX_HALF_CLK_OUT(i) <= rx_half_clk(i); RX_FULL_CLK_OUT(i) <= rx_full_clk(i); @@ -190,7 +216,7 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch0 => SD_RXD_N_IN(0), hdoutp_ch0 => SD_TXD_P_OUT(0), hdoutn_ch0 => SD_TXD_N_OUT(0), - rxiclk_ch0 => clk_200_txdata, --clk_200_i(0), + rxiclk_ch0 => clk_200_txdata, sci_sel_ch0 => sci_ch_i(0), txiclk_ch0 => clk_200_txdata, rx_full_clk_ch0 => rx_full_clk(0), @@ -223,7 +249,7 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch1 => SD_RXD_N_IN(1), hdoutp_ch1 => SD_TXD_P_OUT(1), hdoutn_ch1 => SD_TXD_N_OUT(1), - rxiclk_ch1 => clk_200_txdata, --clk_200_i(1), + rxiclk_ch1 => clk_200_txdata, sci_sel_ch1 => sci_ch_i(1), txiclk_ch1 => clk_200_txdata, rx_full_clk_ch1 => rx_full_clk(1), @@ -256,7 +282,7 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch2 => SD_RXD_N_IN(2), hdoutp_ch2 => SD_TXD_P_OUT(2), hdoutn_ch2 => SD_TXD_N_OUT(2), - rxiclk_ch2 => clk_200_txdata, --clk_200_i(2), + rxiclk_ch2 => clk_200_txdata, sci_sel_ch2 => sci_ch_i(2), txiclk_ch2 => clk_200_txdata, rx_full_clk_ch2 => rx_full_clk(2), @@ -289,7 +315,7 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch3 => SD_RXD_N_IN(3), hdoutp_ch3 => SD_TXD_P_OUT(3), hdoutn_ch3 => SD_TXD_N_OUT(3), - rxiclk_ch3 => clk_200_txdata, --clk_200_i(3), + rxiclk_ch3 => clk_200_txdata, sci_sel_ch3 => sci_ch_i(3), txiclk_ch3 => clk_200_txdata, rx_full_clk_ch3 => rx_full_clk(3), @@ -325,11 +351,11 @@ THE_SERDES : entity work.serdes_4_sync_downstream sci_rd => sci_read_i, sci_wrn => sci_write_i, - fpga_txrefclk => clk_200_txdata, --clk_200_osc, --clk_200_i(0), + fpga_txrefclk => clk_200_txdata, tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906 tx_pll_lol_qd_s => tx_pll_lol_quad, tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols - rst_qd_c => rst_down_quad, -- jemig wat is Oscar toch gasfjkl[glk + rst_qd_c => rst_down_quad, serdes_rst_qd_c => serdes_rst_down_quad ); @@ -354,7 +380,7 @@ generated_logic : for i in 0 to 3 generate THE_RX_FSM : rx_reset_fsm port map( RST_N => rst_n(i), - RX_REFCLK => rx_full_clk(i), --clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn + RX_REFCLK => rx_full_clk(i), TX_PLL_LOL_QD_S => tx_pll_lol(i), RX_SERDES_RST_CH_C => rx_serdes_rst(i), RX_CDR_LOL_CH_S => rx_cdr_lol(i), @@ -364,10 +390,10 @@ generated_logic : for i in 0 to 3 generate STATE_OUT => rx_fsm_state(i) ); - THE_TX_FSM : tx_reset_fsm + THE_TX_RESET_FSM : tx_reset_fsm port map( RST_N => rst_n(i), - TX_REFCLK => clk_200_txdata, --clk_200_osc, + TX_REFCLK => clk_200_txdata, TX_PLL_LOL_QD_S => tx_pll_lol(i), RST_QD_C => rst_qd(i), TX_PCS_RST_CH_C => tx_pcs_rst(i), @@ -400,102 +426,138 @@ generated_logic : for i in 0 to 3 generate begin if rising_edge(clk_200_txdata) then if got_link_ready_i(i) = '1' then - watchdog_timer(i) <= (others => '0'); - if start_timer(i)(start_timer'left) = '0' then - start_timer(i) <= start_timer(i) + 1; --- start_timer(i)(start_timer'left downto 0) <= start_timer(i)(start_timer'left downto 0) + 1; - end if; + if start_timer(i)(start_timer'left) = '0' then + start_timer(i) <= start_timer(i) + 1; + end if; else start_timer(i) <= (others => '0'); - if ((watchdog_timer(i)(watchdog_timer(i)'left) = '1') and (watchdog_timer(i)(watchdog_timer(i)'left - 1) = '1')) then - watchdog_trigger(i) <= '1'; - else - watchdog_trigger(i) <= '0'; - end if; - if watchdog_trigger(i) = '0' then - watchdog_timer(i) <= watchdog_timer(i) + 1; - else - watchdog_timer(i) <= (others => '0'); - end if; end if; end if; end process; ------------------------------------------------- -- TX Data ------------------------------------------------- - THE_TX : soda_tx_control - port map( - CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i), - CLK_100 => SYSCLK, - RESET_IN => rst(i), --CLEAR, PL! - - TX_DATA_IN => (others => '0'), -- MED_DATA_IN(i), - TX_PACKET_NUMBER_IN => (others => '0'), -- MED_PACKET_NUM_IN(i), - TX_WRITE_IN => '0', -- MED_DATAREADY_IN(i), - TX_READ_OUT => open, -- MED_READ_OUT(i), - - TX_DATA_OUT => tx_data(i), - TX_K_OUT => tx_k(i), - - REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO - REQUEST_POSITION_IN => request_retr_position_i(i), --TODO - - START_RETRANSMIT_IN => start_retr_i(i), --TODO - START_POSITION_IN => request_retr_position_i(i), --TODO - - TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i), - SEND_DLM => TX_DLM_IN(i), - SEND_DLM_WORD => TX_DLM_WORD_IN(i), - - SEND_LINK_RESET_IN => '0', --CTRL_OP(i)(15), - TX_ALLOW_IN => tx_allow(i), - RX_ALLOW_IN => rx_allow(i), - LINK_PHASE_OUT => link_phase_S(i), --PL! + the_tx_fsm : process(clk_200_txdata) + begin + if rising_edge(clk_200_txdata) then + if (RESET='1') then + tx_proc_state(i) <= cRESET; + tx_data(i) <= x"00"; -- idle + tx_k(i) <= '0'; + link_phase_S(i) <= c_PHASE_L; + else + link_phase_S(i) <= not(link_phase_S(i)); + case tx_proc_state(i) is + when cSEND_IDLE => + if (TX_DLM_IN(i)='0') then + tx_proc_state(i) <= cSEND_IDLE; + tx_data(i) <= x"BC"; -- idle + tx_k(i) <= '1'; + else + tx_proc_state(i) <= cSEND_DLM; + tx_data(i) <= x"DC"; -- dlm + tx_k(i) <= '1'; + end if; + when cSEND_DLM => + tx_proc_state(i) <= cSEND_IDLE; + tx_data(i) <= TX_DLM_WORD_IN(i); + tx_k(i) <= '0'; + when others => + tx_proc_state(i) <= cSEND_IDLE; + tx_data(i) <= x"BC"; -- idle + tx_k(i) <= '1'; + end case; + end if; + end if; + end process; +-- THE_TX : soda_tx_control +-- port map( +-- CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i), +-- CLK_100 => SYSCLK, +-- RESET_IN => rst(i), --CLEAR, PL! +-- +-- TX_DATA_IN => (others => '0'), -- MED_DATA_IN(i), +-- TX_PACKET_NUMBER_IN => (others => '0'), -- MED_PACKET_NUM_IN(i), +-- TX_WRITE_IN => '0', -- MED_DATAREADY_IN(i), +-- TX_READ_OUT => open, -- MED_READ_OUT(i), +-- +-- TX_DATA_OUT => tx_data(i), +-- TX_K_OUT => tx_k(i), +-- +-- REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO +-- REQUEST_POSITION_IN => request_retr_position_i(i), --TODO +-- +-- START_RETRANSMIT_IN => start_retr_i(i), --TODO +-- START_POSITION_IN => request_retr_position_i(i), --TODO +-- +-- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i), +-- SEND_DLM => TX_DLM_IN(i), +-- SEND_DLM_WORD => TX_DLM_WORD_IN(i), +-- +-- SEND_LINK_RESET_IN => '0', --CTRL_OP(i)(15), +-- TX_ALLOW_IN => tx_allow(i), +-- RX_ALLOW_IN => rx_allow(i), +-- LINK_PHASE_OUT => link_phase_S(i), --PL! +-- +-- DEBUG_OUT => debug_tx_control_i(i), +-- STAT_REG_OUT => stat_tx_control_i(i) +-- ); - DEBUG_OUT => debug_tx_control_i(i), - STAT_REG_OUT => stat_tx_control_i(i) - ); + LINK_PHASE_OUT(i) <= link_phase_S(i); --PL! + - LINK_PHASE_OUT(i) <= link_phase_S(i); --PL! ------------------------------------------------- -- RX Data - ------------------------------------------------- - THE_RX_CONTROL : rx_control - port map( - CLK_200 => clk_200_txdata, --clk_200_i(i), --PL! - CLK_100 => SYSCLK, - RESET_IN => rst(i), --CLEAR, PL! - - RX_DATA_OUT => open, -- MED_DATA_OUT(i), - RX_PACKET_NUMBER_OUT => open, -- MED_PACKET_NUM_OUT(i), - RX_WRITE_OUT => open, -- MED_DATAREADY_OUT(i), - RX_READ_IN => '0', -- MED_READ_IN(i), - - RX_DATA_IN => rx_data(i), - RX_K_IN => rx_k(i), - - REQUEST_RETRANSMIT_OUT => request_retr_i(i), - REQUEST_POSITION_OUT => request_retr_position_i(i), - - START_RETRANSMIT_OUT => start_retr_i(i), - START_POSITION_OUT => start_retr_position_i(i), - - --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM - RX_DLM => RX_DLM_OUT(i), - RX_DLM_WORD => RX_DLM_WORD_OUT(i), - - SEND_LINK_RESET_OUT => send_link_reset_i(i), - MAKE_RESET_OUT => make_link_reset_i(i), - RX_ALLOW_IN => rx_allow(i), - GOT_LINK_READY => got_link_ready_i(i), - - DEBUG_OUT => debug_rx_control_i(i), - STAT_REG_OUT => stat_rx_control_i(i) - ); + ------------------------------------------------- + the_rx_proc : process(clk_200_txdata) + begin + if rising_edge(clk_200_txdata) then + RX_DLM_OUT(i) <= '0'; + if dlm_received_S(i)='1' then + dlm_received_S(i) <= '0'; + RX_DLM_OUT(i) <= '1'; + RX_DLM_WORD_OUT(i) <= rx_data(i); + elsif (rx_data(i)=x"DC") and (rx_k(i)='1') then + dlm_received_S(i) <= '1'; + end if; + end if; + end process; +-- THE_RX_CONTROL : rx_control +-- port map( +-- CLK_200 => clk_200_txdata, --clk_200_i(i), --PL! +-- CLK_100 => SYSCLK, +-- RESET_IN => rst(i), --CLEAR, PL! +-- +-- RX_DATA_OUT => open, -- MED_DATA_OUT(i), +-- RX_PACKET_NUMBER_OUT => open, -- MED_PACKET_NUM_OUT(i), +-- RX_WRITE_OUT => open, -- MED_DATAREADY_OUT(i), +-- RX_READ_IN => '0', -- MED_READ_IN(i), +-- +-- RX_DATA_IN => rx_data(i), +-- RX_K_IN => rx_k(i), +-- +-- REQUEST_RETRANSMIT_OUT => request_retr_i(i), +-- REQUEST_POSITION_OUT => request_retr_position_i(i), +-- +-- START_RETRANSMIT_OUT => start_retr_i(i), +-- START_POSITION_OUT => start_retr_position_i(i), +-- +-- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM +-- RX_DLM => RX_DLM_OUT(i), +-- RX_DLM_WORD => RX_DLM_WORD_OUT(i), +-- +-- SEND_LINK_RESET_OUT => send_link_reset_i(i), +-- MAKE_RESET_OUT => make_link_reset_i(i), +-- RX_ALLOW_IN => rx_allow(i), +-- GOT_LINK_READY => got_link_ready_i(i), +-- +-- DEBUG_OUT => debug_rx_control_i(i), +-- STAT_REG_OUT => stat_rx_control_i(i) +-- ); internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; - sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL! - + sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); --PL! 200115 + end generate; ------------------------------------------------- @@ -600,53 +662,5 @@ end if; end process; --- ------------------------------------------------- --- -- Debug Registers --- ------------------------------------------------- --- debug_reg(3 downto 0) <= rx_fsm_state; --- debug_reg(4) <= rx_k; --- debug_reg(5) <= rx_error; --- debug_reg(6) <= rx_los_low; --- debug_reg(7) <= rx_cdr_lol; --- --- debug_reg(8) <= tx_k; --- debug_reg(9) <= tx_pll_lol; --- debug_reg(10) <= lsm_status; --- debug_reg(11) <= make_link_reset_i; --- debug_reg(15 downto 12) <= tx_fsm_state; --- -- debug_reg(31 downto 24) <= tx_data; --- --- debug_reg(16) <= '0'; --- debug_reg(17) <= tx_allow; --- debug_reg(18) <= RESET; --- debug_reg(19) <= CLEAR; --- debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8); --- --- debug_reg(35 downto 32) <= wa_position(3 downto 0); --- debug_reg(36) <= debug_tx_control_i(6); --- debug_reg(39 downto 37) <= "000"; --- debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0); - - - STAT_DEBUG <= (others => '0'); --debug_reg; - - generated_status : for i in 0 to 3 generate - -- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; - -- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL! - --- STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK); --- STAT_OP(i)(14) <= '0'; --- STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset --- STAT_OP(i)(12) <= '0'; --- STAT_OP(i)(11) <= '0'; --- STAT_OP(i)(10) <= rx_allow(i); --- STAT_OP(i)(9) <= tx_allow(i); --- STAT_OP(i)(8) <= got_link_ready_i(i); --- STAT_OP(i)(7) <= send_link_reset_i(i); --- STAT_OP(i)(6) <= make_link_reset_i(i); --- STAT_OP(i)(5) <= request_retr_i(i); --- STAT_OP(i)(4) <= start_retr_i(i); --- STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; - end generate; end med_ecp3_sfp_4_soda_arch; \ No newline at end of file diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd index 9e508ba..623bcf2 100644 --- a/code/med_ecp3_sfp_sync_down.vhd +++ b/code/med_ecp3_sfp_sync_down.vhd @@ -260,7 +260,7 @@ THE_SERDES : entity work.serdes_sync_source_downstream SCI_WRN => sci_write_i, fpga_txrefclk => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT - tx_serdes_rst_c => tx_serdes_rst, + tx_serdes_rst_c => '0', --tx_serdes_rst, tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd, serdes_rst_qd_c => serdes_rst_qd @@ -540,4 +540,4 @@ STAT_OP(5) <= request_retr_i; STAT_OP(4) <= start_retr_i; STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7"; -end med_ecp3_sfp_sync_down_arch; \ No newline at end of file +end med_ecp3_sfp_sync_down_arch; diff --git a/code/soda_4source.vhd b/code/soda_4source.vhd index 9badb56..2b1e536 100644 --- a/code/soda_4source.vhd +++ b/code/soda_4source.vhd @@ -47,6 +47,7 @@ architecture Behavioral of soda_4source is signal trb_cmd_pending_S : std_logic := '0'; signal trb_send_cmd_S : std_logic := '0'; signal soda_cmd_window_S : std_logic := '0'; + signal soda_cmd_pending_S : std_logic := '0'; signal start_of_superburst_S : std_logic := '0'; signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator -- signal soda_40mhz_cycle_S : std_logic := '0'; @@ -75,6 +76,7 @@ architecture Behavioral of soda_4source is signal TXstart_of_superburst_S : t_HUB_BIT_ARRAY := (others => '0'); signal TXsuper_burst_nr_S : t_HUB_LWORD_ARRAY; -- from super-burst-nr-generator signal TXsoda_cmd_valid_S : t_HUB_BIT_ARRAY; + signal TXsoda_cmd_window_S : t_HUB_BIT_ARRAY; signal TXsoda_cmd_word_S : t_HUB_LWORD_ARRAY; -- slave bus signals @@ -107,10 +109,10 @@ begin SODA_CMD_WINDOW_OUT => soda_cmd_window_S ); - channel :for i in c_HUB_CHILDREN-1 downto 0 generate TXsoda_cmd_valid_S(i) <= trb_cmd_strobe_S; --trb_cmd_valid_S; + TXsoda_cmd_window_S(i) <= soda_cmd_window_S; TXstart_of_superburst_S(i) <= start_of_superburst_S; TXsoda_cmd_word_S(i) <= '0' & trb_cmd_word_S; TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S; @@ -126,6 +128,7 @@ begin SODA_CYCLE_IN => SODA_CYCLE_IN, SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i), + SODA_CMD_WINDOW_IN => TXsoda_cmd_window_S(i), START_OF_SUPERBURST => TXstart_of_superburst_S(i), SUPER_BURST_NR_IN => TXsuper_burst_nr_S(i)(30 downto 0), SODA_CMD_WORD_IN => TXsoda_cmd_word_S(i)(30 downto 0), @@ -253,18 +256,18 @@ begin ----------------------------------------------------------- -- Transmission history for reply-checking -- ----------------------------------------------------------- - packet_history_proc : process(SYSCLK) - begin - if rising_edge(SYSCLK) then - if( RESET = '1' ) then - last_packet_sent_S <= c_NO_PACKET; - elsif (start_of_superburst_S='1') then - last_packet_sent_S <= c_BST_PACKET; - elsif (trb_cmd_strobe_S='1') then - last_packet_sent_S <= c_CMD_PACKET; - end if; - end if; - end process; +-- packet_history_proc : process(SYSCLK) +-- begin +-- if rising_edge(SYSCLK) then +-- if( RESET = '1' ) then +-- last_packet_sent_S <= c_NO_PACKET; +-- elsif (start_of_superburst_S='1') then +-- last_packet_sent_S <= c_BST_PACKET; +-- elsif (trb_cmd_strobe_S='1') then +-- last_packet_sent_S <= c_CMD_PACKET; +-- end if; +-- end if; +-- end process; --------------------------------------------------------- -- RegIO Statemachine diff --git a/code/soda_components.vhd b/code/soda_components.vhd index 600ca54..1a61970 100644 --- a/code/soda_components.vhd +++ b/code/soda_components.vhd @@ -80,6 +80,7 @@ package soda_components is --Internal Connection LINK_PHASE_IN : in std_logic := '0'; SODA_CYCLE_IN : in std_logic := '0'; + SODA_CMD_WINDOW_IN : in std_logic := '0'; SODA_CMD_STROBE_IN : in std_logic := '0'; -- START_OF_SUPERBURST : in std_logic := '0'; SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); @@ -672,6 +673,63 @@ package soda_components is ); end component; + component Cu_trb_net16_soda_syncUP_ecp3_sfp + port( + OSCCLK : in std_logic; -- 200 MHz reference clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + --Internal Connection TX + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic := '0'; + --Internal Connection RX + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0'); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); + MED_DATAREADY_OUT : out std_logic := '0'; + MED_READ_IN : in std_logic; + + --Copper SFP Connection + CU_RXD_P_IN : in std_logic; + CU_RXD_N_IN : in std_logic; + CU_TXD_P_OUT : out std_logic; + CU_TXD_N_OUT : out std_logic; + CU_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + CU_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + CU_TXDIS_OUT : out std_logic := '0'; -- SFP disable + --Fiber/sync SFP Connection + SYNC_RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + SYNC_TX_DLM_IN : in std_logic; + SYNC_TX_DLM_WORD_IN : in std_logic_vector(7 downto 0); + SYNC_RX_DLM_OUT : out std_logic; + SYNC_RX_DLM_WORD_OUT : out std_logic_vector(7 downto 0); + SYNC_RXD_P_IN : in std_logic; + SYNC_RXD_N_IN : in std_logic; + SYNC_TXD_P_OUT : out std_logic; + SYNC_TXD_N_OUT : out std_logic; + SYNC_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SYNC_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SYNC_TXDIS_OUT : out std_logic := '0'; -- SFP disable + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; + SCI_NACK : out std_logic := '0'; + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0'); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); + end component; + component Cu_trb_net16_soda_sync_ecp3_sfp port( OSCCLK : in std_logic; -- 200 MHz reference clock @@ -702,10 +760,10 @@ package soda_components is SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz - SYNC_DLM_IN : in std_logic; - SYNC_DLM_WORD_IN : in std_logic_vector(7 downto 0); - SYNC_DLM_OUT : out std_logic; - SYNC_DLM_WORD_OUT : out std_logic_vector(7 downto 0); + SYNC_RX_DLM_IN : in std_logic; + SYNC_RX_DLM_WORD_IN : in std_logic_vector(7 downto 0); + SYNC_TX_DLM_OUT : out std_logic; + SYNC_TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0); SYNC_RXD_P_IN : in std_logic; SYNC_RXD_N_IN : in std_logic; SYNC_TXD_P_OUT : out std_logic; @@ -727,7 +785,7 @@ package soda_components is STAT_DEBUG : out std_logic_vector (63 downto 0); CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ); - end component; + end component; component soda_tx_control port( @@ -808,43 +866,43 @@ component DCS generic(DCSMODE : string :="POS"); generic( SERDES_NUM : integer range 0 to 3 := 0; IS_SYNC_SLAVE : integer := c_NO); --select slave mode port( - OSC_CLK : in std_logic; -- 200 MHz reference clock - TX_DATACLK : in std_logic; -- 200 MHz data clock - SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset + OSC_CLK : in std_logic; -- 200 MHz reference clock + TX_DATACLK : in std_logic; -- 200 MHz data clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset --------------------------------------------------------------------------------------------------------------------------------------------------------- - LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. + -- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. --------------------------------------------------------------------------------------------------------------------------------------------------------- - RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz - RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz - TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz - TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz + RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz + TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz --Sync operation - RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); - RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); - TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); - TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); + RX_DLM_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); + RX_DLM_WORD_OUT : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); + TX_DLM_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); + TX_DLM_WORD_IN : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! - --SFP Connection - SD_RXD_P_IN : in t_HUB_BIT; --std_logic; - SD_RXD_N_IN : in t_HUB_BIT; --std_logic; - SD_TXD_P_OUT : out t_HUB_BIT; --std_logic; - SD_TXD_N_OUT : out t_HUB_BIT; --std_logic; - SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used - SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used - SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + --SFP Connection + SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used + SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used + SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable --Control Interface - SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); - SCI_READ : in std_logic := '0'; - SCI_WRITE : in std_logic := '0'; + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; SCI_ACK : out std_logic := '0'; SCI_NACK : out std_logic := '0' ); diff --git a/code/soda_hub.vhd b/code/soda_hub.vhd index 4253f5b..8afb431 100644 --- a/code/soda_hub.vhd +++ b/code/soda_hub.vhd @@ -103,14 +103,7 @@ architecture Behavioral of soda_hub is signal store_rd : std_logic; signal buf_bus_data_out : std_logic_vector(31 downto 0) := (others => '0'); signal ledregister_i : std_logic_vector(31 downto 0) := (others => '0'); - signal txup_dlm_out_S : std_logic; - --- debug --- signal debug_status_S : std_logic_vector(31 downto 0) := (others => '0'); --- signal debug_rx_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); --- signal debug_tx_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); --- signal debug_SOS_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); --- signal debug_cmd_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); +-- signal txup_dlm_out_S : std_logic; begin @@ -143,7 +136,7 @@ begin SODA_CMD_STROBE_IN => soda_cmd_valid_S, SODA_CMD_WORD_IN => soda_cmd_word_S, TX_DLM_PREVIEW_OUT => TXUP_DLM_PREVIEW_OUT, - TX_DLM_OUT => txup_dlm_out_S, --TX_DLM_OUT, + TX_DLM_OUT => TXUP_DLM_OUT, TX_DLM_WORD_OUT => TXUP_DLM_WORD_OUT ); @@ -160,10 +153,10 @@ begin --TXsoda_cmd_word_S(i) <= (others => '0'); --TXsuper_burst_nr_S(i) <= (others => '0'); --else - TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S; - TXstart_of_superburst_S(i) <= start_of_superburst_S; - TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S; - TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S; +-- TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S; +-- TXstart_of_superburst_S(i) <= start_of_superburst_S; +-- TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S; +-- TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S; --end if; --end if; --end process; @@ -177,11 +170,12 @@ begin SODACLK => SODACLK, RESET => RESET, --Internal Connection - LINK_PHASE_IN => UPLINK_PHASE_IN, --link_phase_S, PL! 17092014 vergeten ??? of niet nodig ? - SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i), - START_OF_SUPERBURST => TXstart_of_superburst_S(i), - SUPER_BURST_NR_IN => TXsuper_burst_nr_S(i)(30 downto 0), - SODA_CMD_WORD_IN => TXsoda_cmd_word_S(i)(30 downto 0), + LINK_PHASE_IN => UPLINK_PHASE_IN, --link_phase_S, PL! 17092014 vergeten ??? of niet nodig ? + SODA_CYCLE_IN => '1', -- 40MHz cycle is only required to sync superbursts at the source PL! 24022015 + SODA_CMD_STROBE_IN => soda_cmd_valid_S, --TXsoda_cmd_valid_S(i), + START_OF_SUPERBURST => start_of_superburst_S, --TXstart_of_superburst_S(i), + SUPER_BURST_NR_IN => super_burst_nr_S, --TXsuper_burst_nr_S(i)(30 downto 0), + SODA_CMD_WORD_IN => soda_cmd_word_S, --TXsoda_cmd_word_S(i)(30 downto 0), EXPECTED_REPLY_OUT => expected_reply_S(i), TIME_CAL_OUT => send_start_calibration_S(i), TX_DLM_PREVIEW_OUT => TXDN_DLM_PREVIEW_OUT(i), @@ -448,48 +442,8 @@ end process TRANSFORM; end if; end if; end process THE_READ_REG_PROC; --- buf_bus_data_out <= debug_status_S; --- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then --- buf_bus_data_out <= debug_rx_cnt_S; --- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0101") ) then --- buf_bus_data_out <= debug_tx_cnt_S; --- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0110") ) then --- buf_bus_data_out <= debug_sos_cnt_S; --- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0111") ) then --- buf_bus_data_out <= debug_cmd_cnt_S; --- end if; --- end if; --- end process THE_READ_REG_PROC; - --- debug signals - --DEBUG_HUB : process(SODACLK) - --begin - --if( rising_edge(SODACLK) ) then - --debug_status_S(0) <= RESET; - --debug_status_S(1) <= CLEAR; - --debug_status_S(2) <= CLK_EN; - --if ( RESET = '1' ) then - --debug_rx_cnt_S <= (others => '0'); - --debug_tx_cnt_S <= (others => '0'); - --else - --if (txup_dlm_out_S = '1') then - --debug_tx_cnt_S <= debug_tx_cnt_S + 1; - --end if; - --if (RXUP_DLM_IN = '1') then - --debug_rx_cnt_S <= debug_rx_cnt_S + 1; - --end if; - --if (start_of_superburst_S = '1') then - --debug_sos_cnt_S <= debug_sos_cnt_S + 1; - --end if; - --if (soda_cmd_valid_S = '1') then - --debug_cmd_cnt_S <= debug_cmd_cnt_S + 1; - --end if; - --end if; - --end if; - --end process; - --debug_status_S(31 downto 3) <= LINK_DEBUG_IN(31 downto 3); - TXUP_DLM_OUT <= txup_dlm_out_S; +-- TXUP_DLM_OUT <= txup_dlm_out_S; -- output signals LEDS_OUT <= LEDregister_i(3 downto 0); diff --git a/code/soda_only_ecp3_sfp_4_sync_down.vhd b/code/soda_only_ecp3_sfp_4_sync_down.vhd new file mode 100644 index 0000000..9d51221 --- /dev/null +++ b/code/soda_only_ecp3_sfp_4_sync_down.vhd @@ -0,0 +1,666 @@ +--4 channel Media interface for Lattice ECP3 using PCS at 2GHz + +LIBRARY IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.numeric_std.all; +use IEEE.std_logic_unsigned.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; +use work.soda_components.all; + +entity soda_only_ecp3_sfp_4_sync_down is + generic( SERDES_NUM : integer range 0 to 3 := 0; + IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave + port( + OSC_CLK : in std_logic; -- 200 MHz reference clock + TX_DATACLK : in std_logic; -- 200 MHz data clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + --------------------------------------------------------------------------------------------------------------------------------------------------------- +-- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. + --------------------------------------------------------------------------------------------------------------------------------------------------------- + RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz + RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz + TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + + --Sync operation + RX_DLM_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); + RX_DLM_WORD_OUT : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); + TX_DLM_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); + TX_DLM_WORD_IN : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); + TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! + LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! + + --SFP Connection + SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0); + SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used + SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used + SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; + SCI_NACK : out std_logic := '0' + ); +end entity; + + +architecture soda_only_ecp3_sfp_4_sync_down_arch of soda_only_ecp3_sfp_4_sync_down is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of soda_only_ecp3_sfp_4_sync_down_arch : architecture is "media_downlink_group"; + attribute syn_sharing : string; + attribute syn_sharing of soda_only_ecp3_sfp_4_sync_down_arch : architecture is "off"; + + + +signal clk_200_osc : std_logic; +signal clk_200_txdata : std_logic; +signal rx_full_clk : std_logic_vector(3 downto 0); +signal rx_half_clk : std_logic_vector(3 downto 0); +signal tx_full_clk : std_logic_vector(3 downto 0); +signal tx_half_clk : std_logic_vector(3 downto 0); + +type t_tx_state is (cRESET,cSEND_IDLE,cSEND_DLM); +type t_tx_proc_state is array(c_HUB_CHILDREN-1 downto 0) of t_tx_state; +signal tx_proc_state : t_tx_proc_state; + +signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); +signal tx_k : std_logic_vector(3 downto 0); +signal rx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); +signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0); + +signal rst_n : t_HUB_BIT; +signal rst : t_HUB_BIT; -- PL! +signal rx_serdes_rst : t_HUB_BIT; +signal tx_serdes_rst : std_logic; +signal tx_pcs_rst : t_HUB_BIT; +signal rx_pcs_rst : t_HUB_BIT; +signal rst_qd : t_HUB_BIT; +signal rst_down_quad : std_logic; +signal serdes_rst_qd : t_HUB_BIT; +signal serdes_rst_down_quad : std_logic; -- combined serdes reset for whole quad +signal sd_los_i : t_HUB_BIT; --PL! + +signal dlm_received_S : t_HUB_BIT; + + +signal rx_los_low : t_HUB_BIT; +signal lsm_status : t_HUB_BIT; +signal rx_cdr_lol : t_HUB_BIT; +signal tx_pll_lol : t_HUB_BIT; +signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad + +signal sci_ch_i : std_logic_vector(3 downto 0); +signal sci_qd_i : std_logic; +signal sci_reg_i : std_logic; +signal sci_addr_i : std_logic_vector(8 downto 0); +signal sci_data_in_i : std_logic_vector(7 downto 0); +signal sci_data_out_i : std_logic_vector(7 downto 0); +signal sci_read_i : std_logic; +signal sci_write_i : std_logic; +signal sci_write_shift_i : std_logic_vector(2 downto 0); +signal sci_read_shift_i : std_logic_vector(2 downto 0); + +signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF"; +signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF"; +signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal rx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal tx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal rx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal link_phase_S : t_HUB_BIT; --std_logic_vector(3 downto 0); --PL! +signal request_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal start_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal request_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0); +signal start_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0); +signal send_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal make_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal got_link_ready_i : t_HUB_BIT; --std_logic_vector(3 downto 0); +signal internal_make_link_reset_out : t_HUB_BIT; --std_logic_vector(3 downto 0); + +signal start_timer : t_HUB_TIMER19 := (others => (others => '0')); --unsigned(18 downto 0) := (others => '0'); + +signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); +signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0); + +signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); +signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); +signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); +signal debug_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0); +signal debug_reg : std_logic_vector(63 downto 0); + +type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); +signal sci_state : sci_ctrl; +signal sci_timer : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0) := (others => '0'); + +-- fix signal names for constraining +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_useioff : boolean; + +attribute syn_useioff of sd_los_i : signal is false; -- do not use an IOFF for this signal + +attribute syn_preserve of sci_ch_i : signal is true; +attribute syn_keep of sci_ch_i : signal is true; +attribute syn_preserve of sci_qd_i : signal is true; +attribute syn_keep of sci_qd_i : signal is true; +attribute syn_preserve of sci_reg_i : signal is true; +attribute syn_keep of sci_reg_i : signal is true; +attribute syn_preserve of sci_addr_i : signal is true; +attribute syn_keep of sci_addr_i : signal is true; +attribute syn_preserve of sci_data_in_i : signal is true; +attribute syn_keep of sci_data_in_i : signal is true; +attribute syn_preserve of sci_data_out_i : signal is true; +attribute syn_keep of sci_data_out_i : signal is true; +attribute syn_preserve of sci_read_i : signal is true; +attribute syn_keep of sci_read_i : signal is true; +attribute syn_preserve of sci_write_i : signal is true; +attribute syn_keep of sci_write_i : signal is true; +attribute syn_preserve of sci_write_shift_i : signal is true; +attribute syn_keep of sci_write_shift_i : signal is true; +attribute syn_preserve of sci_read_shift_i : signal is true; +attribute syn_keep of sci_read_shift_i : signal is true; + +begin + + +--SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready + +clk_200_osc <= OSC_CLK; -- This external clock is oscillator/pll generated !!! +clk_200_txdata <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!! + + +gen_clocks : for i in 0 to 3 generate + + rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i)); + rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i)); + + RX_HALF_CLK_OUT(i) <= rx_half_clk(i); + RX_FULL_CLK_OUT(i) <= rx_full_clk(i); + TX_HALF_CLK_OUT(i) <= tx_half_clk(i); + TX_FULL_CLK_OUT(i) <= tx_full_clk(i); + +-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master +-- clk_200_i(i) <= rx_full_clk(i); +-- end generate; + +-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate +-- clk_200_i(i) <= clk_200_txdata; +-- clk_200_rxdn(i) <= rx_full_clk(i); -- These clocks are the rx_full of the DOWNLINKs !!! +-- end generate; +end generate; + +------------------------------------------------- +-- Serdes +------------------------------------------------- +THE_SERDES : entity work.serdes_4_sync_downstream + port map( + -- CHANNEL0 -- + hdinp_ch0 => SD_RXD_P_IN(0), + hdinn_ch0 => SD_RXD_N_IN(0), + hdoutp_ch0 => SD_TXD_P_OUT(0), + hdoutn_ch0 => SD_TXD_N_OUT(0), + rxiclk_ch0 => clk_200_txdata, + sci_sel_ch0 => sci_ch_i(0), + txiclk_ch0 => clk_200_txdata, + rx_full_clk_ch0 => rx_full_clk(0), + rx_half_clk_ch0 => rx_half_clk(0), + tx_full_clk_ch0 => tx_full_clk(0), + tx_half_clk_ch0 => tx_half_clk(0), + fpga_rxrefclk_ch0 => clk_200_osc, + txdata_ch0 => tx_data(0), + tx_k_ch0 => tx_k(0), + tx_force_disp_ch0 => '0', + tx_disp_sel_ch0 => '0', + rxdata_ch0 => rx_data(0), + rx_k_ch0 => rx_k(0), + rx_disp_err_ch0 => open, + rx_cv_err_ch0 => rx_error(0), + rx_serdes_rst_ch0_c => rx_serdes_rst(0), + sb_felb_ch0_c => '0', + sb_felb_rst_ch0_c => '0', + tx_pcs_rst_ch0_c => tx_pcs_rst(0), + tx_pwrup_ch0_c => '1', + rx_pcs_rst_ch0_c => rx_pcs_rst(0), + rx_pwrup_ch0_c => '1', + rx_los_low_ch0_s => rx_los_low(0), + lsm_status_ch0_s => lsm_status(0), + rx_cdr_lol_ch0_s => rx_cdr_lol(0), + tx_div2_mode_ch0_c => '0', + rx_div2_mode_ch0_c => '0', + -- CHANNEL1 -- + hdinp_ch1 => SD_RXD_P_IN(1), + hdinn_ch1 => SD_RXD_N_IN(1), + hdoutp_ch1 => SD_TXD_P_OUT(1), + hdoutn_ch1 => SD_TXD_N_OUT(1), + rxiclk_ch1 => clk_200_txdata, + sci_sel_ch1 => sci_ch_i(1), + txiclk_ch1 => clk_200_txdata, + rx_full_clk_ch1 => rx_full_clk(1), + rx_half_clk_ch1 => rx_half_clk(1), + tx_full_clk_ch1 => tx_full_clk(1), + tx_half_clk_ch1 => tx_half_clk(1), + fpga_rxrefclk_ch1 => clk_200_osc, + txdata_ch1 => tx_data(1), + tx_k_ch1 => tx_k(1), + tx_force_disp_ch1 => '0', + tx_disp_sel_ch1 => '0', + rxdata_ch1 => rx_data(1), + rx_k_ch1 => rx_k(1), + rx_disp_err_ch1 => open, + rx_cv_err_ch1 => rx_error(1), + rx_serdes_rst_ch1_c => rx_serdes_rst(1), + sb_felb_ch1_c => '0', + sb_felb_rst_ch1_c => '0', + tx_pcs_rst_ch1_c => tx_pcs_rst(1), + tx_pwrup_ch1_c => '1', + rx_pcs_rst_ch1_c => rx_pcs_rst(1), + rx_pwrup_ch1_c => '1', + rx_los_low_ch1_s => rx_los_low(1), + lsm_status_ch1_s => lsm_status(1), + rx_cdr_lol_ch1_s => rx_cdr_lol(1), + tx_div2_mode_ch1_c => '0', + rx_div2_mode_ch1_c => '0', + -- CHANNEL2 -- + hdinp_ch2 => SD_RXD_P_IN(2), + hdinn_ch2 => SD_RXD_N_IN(2), + hdoutp_ch2 => SD_TXD_P_OUT(2), + hdoutn_ch2 => SD_TXD_N_OUT(2), + rxiclk_ch2 => clk_200_txdata, + sci_sel_ch2 => sci_ch_i(2), + txiclk_ch2 => clk_200_txdata, + rx_full_clk_ch2 => rx_full_clk(2), + rx_half_clk_ch2 => rx_half_clk(2), + tx_full_clk_ch2 => tx_full_clk(2), + tx_half_clk_ch2 => tx_half_clk(2), + fpga_rxrefclk_ch2 => clk_200_osc, + txdata_ch2 => tx_data(2), + tx_k_ch2 => tx_k(2), + tx_force_disp_ch2 => '0', + tx_disp_sel_ch2 => '0', + rxdata_ch2 => rx_data(2), + rx_k_ch2 => rx_k(2), + rx_disp_err_ch2 => open, + rx_cv_err_ch2 => rx_error(2), + rx_serdes_rst_ch2_c => rx_serdes_rst(2), + sb_felb_ch2_c => '0', + sb_felb_rst_ch2_c => '0', + tx_pcs_rst_ch2_c => tx_pcs_rst(2), + tx_pwrup_ch2_c => '1', + rx_pcs_rst_ch2_c => rx_pcs_rst(2), + rx_pwrup_ch2_c => '1', + rx_los_low_ch2_s => rx_los_low(2), + lsm_status_ch2_s => lsm_status(2), + rx_cdr_lol_ch2_s => rx_cdr_lol(2), + tx_div2_mode_ch2_c => '0', + rx_div2_mode_ch2_c => '0', + -- CHANNEL3 -- + hdinp_ch3 => SD_RXD_P_IN(3), + hdinn_ch3 => SD_RXD_N_IN(3), + hdoutp_ch3 => SD_TXD_P_OUT(3), + hdoutn_ch3 => SD_TXD_N_OUT(3), + rxiclk_ch3 => clk_200_txdata, + sci_sel_ch3 => sci_ch_i(3), + txiclk_ch3 => clk_200_txdata, + rx_full_clk_ch3 => rx_full_clk(3), + rx_half_clk_ch3 => rx_half_clk(3), + tx_full_clk_ch3 => tx_full_clk(3), + tx_half_clk_ch3 => tx_half_clk(3), + fpga_rxrefclk_ch3 => clk_200_osc, + txdata_ch3 => tx_data(3), + tx_k_ch3 => tx_k(3), + tx_force_disp_ch3 => '0', + tx_disp_sel_ch3 => '0', + rxdata_ch3 => rx_data(3), + rx_k_ch3 => rx_k(3), + rx_disp_err_ch3 => open, + rx_cv_err_ch3 => rx_error(3), + rx_serdes_rst_ch3_c => rx_serdes_rst(3), + sb_felb_ch3_c => '0', + sb_felb_rst_ch3_c => '0', + tx_pcs_rst_ch3_c => tx_pcs_rst(3), + tx_pwrup_ch3_c => '1', + rx_pcs_rst_ch3_c => rx_pcs_rst(3), + rx_pwrup_ch3_c => '1', + rx_los_low_ch3_s => rx_los_low(3), + lsm_status_ch3_s => lsm_status(3), + rx_cdr_lol_ch3_s => rx_cdr_lol(3), + tx_div2_mode_ch3_c => '0', + rx_div2_mode_ch3_c => '0', + -- COMMON -- + sci_wrdata => sci_data_in_i, + sci_rddata => sci_data_out_i, + sci_addr => sci_addr_i(5 downto 0), + sci_sel_quad => sci_qd_i, + sci_rd => sci_read_i, + sci_wrn => sci_write_i, + + fpga_txrefclk => clk_200_txdata, + tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906 + tx_pll_lol_qd_s => tx_pll_lol_quad, + tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols + rst_qd_c => rst_down_quad, + serdes_rst_qd_c => serdes_rst_down_quad + ); + +------------------------- +-- combined quad reset -- +------------------------- +--rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0'; +rst_down_quad <= RESET; -- PL: 18/06/14 +--serdes_rst_down_quad <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0'; +serdes_rst_down_quad <= '0'; -- PL: 23/06/14 + +generated_logic : for i in 0 to 3 generate + +-- SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready + SD_TXDIS_OUT(i) <= '0'; --not rx_allow_q(i); --slave only switches on when RX is ready + + tx_pll_lol(i) <= tx_pll_lol_quad; + + ------------------------------------------------- + -- Reset FSM & Link states + ------------------------------------------------- + THE_RX_FSM : rx_reset_fsm + port map( + RST_N => rst_n(i), + RX_REFCLK => rx_full_clk(i), + TX_PLL_LOL_QD_S => tx_pll_lol(i), + RX_SERDES_RST_CH_C => rx_serdes_rst(i), + RX_CDR_LOL_CH_S => rx_cdr_lol(i), + RX_LOS_LOW_CH_S => rx_los_low(i), + RX_PCS_RST_CH_C => rx_pcs_rst(i), + WA_POSITION => wa_position_rx(i), + STATE_OUT => rx_fsm_state(i) + ); + + THE_TX_RESET_FSM : tx_reset_fsm + port map( + RST_N => rst_n(i), + TX_REFCLK => clk_200_txdata, + TX_PLL_LOL_QD_S => tx_pll_lol(i), + RST_QD_C => rst_qd(i), + TX_PCS_RST_CH_C => tx_pcs_rst(i), + STATE_OUT => tx_fsm_state(i) + ); + + + -- Master does not do bit-locking + wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0"; + + + PROC_ALLOW : process(clk_200_txdata) --clk_200_i(i)) + begin + if rising_edge(clk_200_txdata) then -- clk_200_txdata ?? + if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then + rx_allow(i) <= '1'; + tx_allow(i) <= '1'; + else + rx_allow(i) <= '0'; + tx_allow(i) <= '1'; + end if; + end if; + end process; + + rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK); + tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK); + + + PROC_START_TIMER : process(clk_200_txdata) --clk_200_i(i)) + begin + if rising_edge(clk_200_txdata) then + if got_link_ready_i(i) = '1' then + if start_timer(i)(start_timer'left) = '0' then + start_timer(i) <= start_timer(i) + 1; + end if; + else + start_timer(i) <= (others => '0'); + end if; + end if; + end process; + ------------------------------------------------- + -- TX Data + ------------------------------------------------- + the_tx_fsm : process(clk_200_txdata) + begin + if rising_edge(clk_200_txdata) then + if (RESET='1') then + tx_proc_state(i) <= cRESET; + tx_data(i) <= x"00"; -- idle + tx_k(i) <= '0'; + link_phase_S(i) <= c_PHASE_L; + else + link_phase_S(i) <= not(link_phase_S(i)); + case tx_proc_state(i) is + when cSEND_IDLE => + if (TX_DLM_IN(i)='0') then + tx_proc_state(i) <= cSEND_IDLE; + tx_data(i) <= x"BC"; -- idle + tx_k(i) <= '1'; + else + tx_proc_state(i) <= cSEND_DLM; + tx_data(i) <= x"DC"; -- dlm + tx_k(i) <= '1'; + end if; + when cSEND_DLM => + tx_proc_state(i) <= cSEND_IDLE; + tx_data(i) <= TX_DLM_WORD_IN(i); + tx_k(i) <= '0'; + when others => + tx_proc_state(i) <= cSEND_IDLE; + tx_data(i) <= x"BC"; -- idle + tx_k(i) <= '1'; + end case; + end if; + end if; + end process; +-- THE_TX : soda_tx_control +-- port map( +-- CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i), +-- CLK_100 => SYSCLK, +-- RESET_IN => rst(i), --CLEAR, PL! +-- +-- TX_DATA_IN => (others => '0'), -- MED_DATA_IN(i), +-- TX_PACKET_NUMBER_IN => (others => '0'), -- MED_PACKET_NUM_IN(i), +-- TX_WRITE_IN => '0', -- MED_DATAREADY_IN(i), +-- TX_READ_OUT => open, -- MED_READ_OUT(i), +-- +-- TX_DATA_OUT => tx_data(i), +-- TX_K_OUT => tx_k(i), +-- +-- REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO +-- REQUEST_POSITION_IN => request_retr_position_i(i), --TODO +-- +-- START_RETRANSMIT_IN => start_retr_i(i), --TODO +-- START_POSITION_IN => request_retr_position_i(i), --TODO +-- +-- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i), +-- SEND_DLM => TX_DLM_IN(i), +-- SEND_DLM_WORD => TX_DLM_WORD_IN(i), +-- +-- SEND_LINK_RESET_IN => '0', --CTRL_OP(i)(15), +-- TX_ALLOW_IN => tx_allow(i), +-- RX_ALLOW_IN => rx_allow(i), +-- LINK_PHASE_OUT => link_phase_S(i), --PL! +-- +-- DEBUG_OUT => debug_tx_control_i(i), +-- STAT_REG_OUT => stat_tx_control_i(i) +-- ); + + LINK_PHASE_OUT(i) <= link_phase_S(i); --PL! + + + ------------------------------------------------- + -- RX Data + ------------------------------------------------- + the_rx_proc : process(clk_200_txdata) + begin + if rising_edge(clk_200_txdata) then + RX_DLM_OUT(i) <= '0'; + if dlm_received_S(i)='1' then + dlm_received_S(i) <= '0'; + RX_DLM_OUT(i) <= '1'; + RX_DLM_WORD_OUT(i) <= rx_data(i); + elsif (rx_data(i)=x"DC") and (rx_k(i)='1') then + dlm_received_S(i) <= '1'; + end if; + end if; + end process; +-- THE_RX_CONTROL : rx_control +-- port map( +-- CLK_200 => clk_200_txdata, --clk_200_i(i), --PL! +-- CLK_100 => SYSCLK, +-- RESET_IN => rst(i), --CLEAR, PL! +-- +-- RX_DATA_OUT => open, -- MED_DATA_OUT(i), +-- RX_PACKET_NUMBER_OUT => open, -- MED_PACKET_NUM_OUT(i), +-- RX_WRITE_OUT => open, -- MED_DATAREADY_OUT(i), +-- RX_READ_IN => '0', -- MED_READ_IN(i), +-- +-- RX_DATA_IN => rx_data(i), +-- RX_K_IN => rx_k(i), +-- +-- REQUEST_RETRANSMIT_OUT => request_retr_i(i), +-- REQUEST_POSITION_OUT => request_retr_position_i(i), +-- +-- START_RETRANSMIT_OUT => start_retr_i(i), +-- START_POSITION_OUT => start_retr_position_i(i), +-- +-- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM +-- RX_DLM => RX_DLM_OUT(i), +-- RX_DLM_WORD => RX_DLM_WORD_OUT(i), +-- +-- SEND_LINK_RESET_OUT => send_link_reset_i(i), +-- MAKE_RESET_OUT => make_link_reset_i(i), +-- RX_ALLOW_IN => rx_allow(i), +-- GOT_LINK_READY => got_link_ready_i(i), +-- +-- DEBUG_OUT => debug_rx_control_i(i), +-- STAT_REG_OUT => stat_rx_control_i(i) +-- ); + + internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; + sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); --PL! 200115 + +end generate; + +------------------------------------------------- +-- SCI +------------------------------------------------- +--gives access to serdes config port from slow control and reads word alignment every ~ 40 us +PROC_SCI_CTRL: process +variable cnt : integer range 0 to 4 := 0; +begin +wait until rising_edge(SYSCLK); + SCI_ACK <= '0'; + case sci_state is + when IDLE => + sci_ch_i <= x"0"; + sci_qd_i <= '0'; + sci_reg_i <= '0'; + sci_read_i <= '0'; + sci_write_i <= '0'; + sci_timer(0) <= sci_timer(0) + 1; + sci_timer(1) <= sci_timer(1) + 1; + sci_timer(2) <= sci_timer(2) + 1; + sci_timer(3) <= sci_timer(3) + 1; + if SCI_READ = '1' or SCI_WRITE = '1' then + sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); + sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8); + sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); + sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8); + sci_addr_i <= SCI_ADDR; + sci_data_in_i <= SCI_DATA_IN; + sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); + sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8)); + sci_state <= SCTRL; + else + if sci_timer(0)(sci_timer'left) = '1' then + sci_timer(0) <= (others => '0'); + sci_state <= GET_WA; + end if; + if sci_timer(1)(sci_timer'left) = '1' then + sci_timer(1) <= (others => '0'); + sci_state <= GET_WA; + end if; + if sci_timer(2)(sci_timer'left) = '1' then + sci_timer(2) <= (others => '0'); + sci_state <= GET_WA; + end if; + if sci_timer(3)(sci_timer'left) = '1' then + sci_timer(3) <= (others => '0'); + sci_state <= GET_WA; + end if; + end if; +when SCTRL => + if sci_reg_i = '1' then + SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))); + SCI_ACK <= '1'; + sci_write_i <= '0'; + sci_read_i <= '0'; + sci_state <= IDLE; + else + sci_state <= SCTRL_WAIT; + end if; +when SCTRL_WAIT => + sci_state <= SCTRL_WAIT2; +when SCTRL_WAIT2 => + sci_state <= SCTRL_FINISH; +when SCTRL_FINISH => + SCI_DATA_OUT <= sci_data_out_i; + SCI_ACK <= '1'; + sci_write_i <= '0'; + sci_read_i <= '0'; + sci_state <= IDLE; + +when GET_WA => + if cnt = 4 then + cnt := 0; + sci_state <= IDLE; + else + sci_state <= GET_WA_WAIT; + sci_addr_i <= '0' & x"22"; + sci_ch_i <= x"0"; + sci_ch_i(cnt) <= '1'; + sci_read_i <= '1'; + end if; +when GET_WA_WAIT => + sci_state <= GET_WA_WAIT2; +when GET_WA_WAIT2 => + sci_state <= GET_WA_FINISH; +when GET_WA_FINISH => +-- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0); + wa_position(cnt) <= sci_data_out_i(3 downto 0); + sci_state <= GET_WA; + cnt := cnt + 1; +end case; + +if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then + SCI_NACK <= '1'; +else + SCI_NACK <= '0'; +end if; + +end process; + + + +end soda_only_ecp3_sfp_4_sync_down_arch; diff --git a/code/soda_packet_builder.vhd b/code/soda_packet_builder.vhd index aacd6ac..641efe5 100644 --- a/code/soda_packet_builder.vhd +++ b/code/soda_packet_builder.vhd @@ -16,7 +16,8 @@ entity soda_packet_builder is --Internal Connection LINK_PHASE_IN : in std_logic := '0'; -- even/odd fase needed to match 16-bit link stuff in trb SODA_CYCLE_IN : in std_logic := '0'; -- 40MHz cycle for soda transmissions - SODA_CMD_STROBE_IN : in std_logic := '0'; + SODA_CMD_WINDOW_IN : in std_logic := '0'; + SODA_CMD_STROBE_IN : in std_logic := '0'; START_OF_SUPERBURST : in std_logic := '0'; SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit @@ -30,10 +31,15 @@ end soda_packet_builder; architecture Behavioral of soda_packet_builder is - signal soda_cmd_window_S : std_logic; - signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); -- from slowcontrol + signal soda_cmd_pending_S : std_logic := '0'; + signal soda_cmd_strobe_S : std_logic := '0'; + signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); -- from slowcontrol signal soda_pkt_word_S : std_logic_vector(7 downto 0) := (others => '0'); - signal soda_pkt_valid_S : std_logic; + signal soda_pkt_valid_S : std_logic; + signal reg1_soda_pkt_valid_S : std_logic; +-- signal reg2_soda_pkt_valid_S : std_logic; + signal wait4cycle_S : std_logic; + signal soc_S : std_logic; signal eoc_S : std_logic; @@ -42,11 +48,12 @@ architecture Behavioral of soda_packet_builder is signal crc_out_S : std_logic_vector(7 downto 0) := (others => '0'); signal crc_valid_S : std_logic; - type packet_state_type is ( c_IDLE, c_ERROR, - c_WAIT4BST1, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8, - c_WAIT4CMD1, c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8 - ); - signal packet_state_S : packet_state_type := c_IDLE; + type build_packet_state_type is ( c_IDLE, c_ERROR, + c_WAIT4CYCLE_B, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8, + c_WAIT4CYCLE_C, c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8 + ); -- c_WAIT4BST1, c_WAIT4CMD1, + signal build_packet_state_S : build_packet_state_type := c_IDLE; + signal build_packet_bits_S : std_logic_vector(7 downto 0) := (others => '0'); signal soda_dlm_preview_S : std_logic; @@ -66,149 +73,261 @@ begin soda_cmd_word_S <= SODA_CMD_WORD_IN; - TX_DLM_PREVIEW_OUT <= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1'))) or - ((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1'))) - else '0'; - TX_DLM_OUT <= soda_pkt_valid_S; +-- TX_DLM_PREVIEW_OUT <= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (soda_cmd_strobe_S='1'))) or +-- ((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1'))) +-- else '0'; + TX_DLM_PREVIEW_OUT <= '1' when ((soda_dlm_preview_S='1') or ((wait4cycle_S='1') and (SODA_CYCLE_IN='1'))) + else '0'; + TX_DLM_OUT <= reg1_soda_pkt_valid_S; TX_DLM_WORD_OUT <= soda_pkt_word_S; - - + + + strobe_delay_proc : process(SODACLK) + begin + if rising_edge(SODACLK) then + if (RESET='1') then + soda_cmd_pending_S <= '0'; + elsif (SODA_CMD_STROBE_IN='1') then + soda_cmd_pending_S <= '1'; + elsif (soda_cmd_strobe_S='1') then + soda_cmd_pending_S <= '0'; + end if; + end if; + end process; + + + strobe_delivery_proc : process(SODACLK) + begin + if rising_edge(SODACLK) then + if (RESET='1') then + soda_cmd_strobe_S <= '0'; + elsif ((SODA_CMD_STROBE_IN='1') and (soda_cmd_pending_S='1')) then + soda_cmd_strobe_S <= '1'; + else + soda_cmd_strobe_S <= '0'; + end if; + end if; + end process; + + packet_fsm_proc : process(SODACLK) begin if rising_edge(SODACLK) then if (RESET='1') then - packet_state_S <= c_IDLE; - soda_dlm_preview_S <= '0'; - soda_pkt_valid_S <= '0'; - soda_pkt_word_S <= (others => '0'); + build_packet_bits_S <= x"00"; + build_packet_state_S <= c_IDLE; + soda_dlm_preview_S <= '0'; + soda_pkt_valid_S <= '0'; + reg1_soda_pkt_valid_S <= '0'; +-- reg2_soda_pkt_valid_S <= '0'; + wait4cycle_S <= '0'; + soda_pkt_word_S <= (others => '0'); else - case packet_state_S is - when c_IDLE => + soda_pkt_valid_S <= reg1_soda_pkt_valid_S; +-- reg2_soda_pkt_valid_S <= reg1_soda_pkt_valid_S; + case build_packet_state_S is +-- when c_IDLE => +-- if (START_OF_SUPERBURST='1') then +-- soda_dlm_preview_S <= '1'; +-- if (LINK_PHASE_IN = c_PHASE_H) then +-- build_packet_state_S <= c_BST1; +-- soda_pkt_valid_S <= '1'; +-- soda_pkt_word_S <= '1' & SUPER_BURST_NR_IN(30 downto 24); +-- else +-- build_packet_state_S <= c_WAIT4BST1; +-- soda_pkt_valid_S <= '0'; +-- end if; +-- elsif (soda_cmd_strobe_S='1') then +-- soda_dlm_preview_S <= '1'; +-- if ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)) then +-- build_packet_state_S <= c_CMD1; +-- soda_pkt_valid_S <= '1'; +-- soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24); +-- else +-- build_packet_state_S <= c_WAIT4CMD1; +-- soda_pkt_valid_S <= '0'; +-- end if; +-- else +-- build_packet_state_S <= c_IDLE; +-- TIME_CAL_OUT <= '0'; +-- soda_pkt_valid_S <= '0'; +-- soda_pkt_word_S <= (others=>'0'); +-- end if; + when c_IDLE => if (START_OF_SUPERBURST='1') then - soda_dlm_preview_S <= '1'; - if (LINK_PHASE_IN = c_PHASE_H) then - packet_state_S <= c_BST1; - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= '1' & SUPER_BURST_NR_IN(30 downto 24); + if ((SODA_CYCLE_IN='1') and (LINK_PHASE_IN = c_PHASE_H)) then + build_packet_bits_S <= x"11"; + build_packet_state_S <= c_BST1; +-- soda_dlm_preview_S <= '1'; + reg1_soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= '1' & SUPER_BURST_NR_IN(30 downto 24); else - packet_state_S <= c_WAIT4BST1; - soda_pkt_valid_S <= '0'; - end if; - elsif (SODA_CMD_STROBE_IN='1') then - soda_dlm_preview_S <= '1'; - if ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)) then - packet_state_S <= c_CMD1; - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24); + build_packet_bits_S <= x"10"; + build_packet_state_S <= c_WAIT4CYCLE_B; + reg1_soda_pkt_valid_S <= '0'; + end if; + elsif (soda_cmd_strobe_S='1') then + if ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)) then + build_packet_bits_S <= x"21"; + build_packet_state_S <= c_CMD1; +-- soda_dlm_preview_S <= '1'; + reg1_soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24); else - packet_state_S <= c_WAIT4CMD1; - soda_pkt_valid_S <= '0'; - end if; + build_packet_bits_S <= x"20"; + build_packet_state_S <= c_WAIT4CYCLE_C; + reg1_soda_pkt_valid_S <= '0'; + end if; else - packet_state_S <= c_IDLE; - TIME_CAL_OUT <= '0'; - soda_pkt_valid_S <= '0'; - soda_pkt_word_S <= (others=>'0'); - end if; - when c_WAIT4BST1 => - packet_state_S <= c_BST1; - soda_dlm_preview_S <= '1'; - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= '1' & SUPER_BURST_NR_IN(30 downto 24); + build_packet_bits_S <= x"00"; + build_packet_state_S <= c_IDLE; + TIME_CAL_OUT <= '0'; + reg1_soda_pkt_valid_S <= '0'; + soda_pkt_word_S <= (others=>'0'); + end if; + when c_WAIT4CYCLE_B => + wait4cycle_S <= '1'; + if ((SODA_CYCLE_IN='1') and (LINK_PHASE_IN = c_PHASE_H)) then + build_packet_bits_S <= x"11"; + build_packet_state_S <= c_BST1; + wait4cycle_S <= '0'; + soda_dlm_preview_S <= '1'; + reg1_soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= '1' & SUPER_BURST_NR_IN(30 downto 24); + else + build_packet_bits_S <= x"10"; + build_packet_state_S <= c_WAIT4CYCLE_B; + soda_dlm_preview_S <= '0'; + reg1_soda_pkt_valid_S <= '0'; + end if; +-- when c_WAIT4BST1 => +-- build_packet_state_S <= c_BST1; +-- soda_dlm_preview_S <= '1'; +-- reg1_soda_pkt_valid_S <= '1'; +-- soda_pkt_word_S <= '1' & SUPER_BURST_NR_IN(30 downto 24); when c_BST1 => - packet_state_S <= c_BST2; - soda_pkt_valid_S <= '0'; + build_packet_bits_S <= x"12"; + build_packet_state_S <= c_BST2; + reg1_soda_pkt_valid_S <= '0'; when c_BST2 => - packet_state_S <= c_BST3; - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= SUPER_BURST_NR_IN(23 downto 16); + build_packet_bits_S <= x"13"; + build_packet_state_S <= c_BST3; + reg1_soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= SUPER_BURST_NR_IN(23 downto 16); when c_BST3 => - packet_state_S <= c_BST4; - soda_pkt_valid_S <= '0'; + build_packet_bits_S <= x"14"; + build_packet_state_S <= c_BST4; + reg1_soda_pkt_valid_S <= '0'; when c_BST4 => - packet_state_S <= c_BST5; - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= SUPER_BURST_NR_IN(15 downto 8); + build_packet_bits_S <= x"15"; + build_packet_state_S <= c_BST5; + reg1_soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= SUPER_BURST_NR_IN(15 downto 8); when c_BST5 => - packet_state_S <= c_BST6; - soda_pkt_valid_S <= '0'; + build_packet_bits_S <= x"16"; + build_packet_state_S <= c_BST6; + reg1_soda_pkt_valid_S <= '0'; when c_BST6 => - packet_state_S <= c_BST7; - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= SUPER_BURST_NR_IN(7 downto 0); - EXPECTED_REPLY_OUT <= SUPER_BURST_NR_IN(7 downto 0); + build_packet_bits_S <= x"17"; + build_packet_state_S <= c_BST7; + reg1_soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= SUPER_BURST_NR_IN(7 downto 0); + EXPECTED_REPLY_OUT <= SUPER_BURST_NR_IN(7 downto 0); when c_BST7 => - packet_state_S <= c_BST8; - soda_dlm_preview_S <= '0'; - soda_pkt_valid_S <= '0'; + build_packet_bits_S <= x"18"; + build_packet_state_S <= c_BST8; + soda_dlm_preview_S <= '0'; + reg1_soda_pkt_valid_S <= '0'; when c_BST8 => if (SODA_CMD_STROBE_IN='0') then - soda_dlm_preview_S <= '0'; - packet_state_S <= c_IDLE; + soda_dlm_preview_S <= '0'; + build_packet_bits_S <= x"00"; + build_packet_state_S <= c_IDLE; else - soda_dlm_preview_S <= '1'; - packet_state_S <= c_CMD1; + soda_dlm_preview_S <= '1'; + build_packet_bits_S <= x"21"; + build_packet_state_S <= c_CMD1; end if; - soda_pkt_valid_S <= '0'; - soda_pkt_word_S <= (others=>'0'); - when c_WAIT4CMD1 => - if ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)) then - packet_state_S <= c_CMD1; - soda_dlm_preview_S <= '1'; - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24); - else - packet_state_S <= c_WAIT4CMD1; - soda_dlm_preview_S <= '0'; - soda_pkt_valid_S <= '0'; --- soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24); - end if; + reg1_soda_pkt_valid_S <= '0'; + soda_pkt_word_S <= (others=>'0'); + when c_WAIT4CYCLE_C => + wait4cycle_S <= '1'; + if ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)) then + build_packet_bits_S <= x"21"; + build_packet_state_S <= c_CMD1; + wait4cycle_S <= '0'; + soda_dlm_preview_S <= '1'; + reg1_soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24); + else + build_packet_bits_S <= x"20"; + build_packet_state_S <= c_WAIT4CYCLE_C; + soda_dlm_preview_S <= '0'; + reg1_soda_pkt_valid_S <= '0'; + soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24); + end if; +-- when c_WAIT4CMD1 => +-- build_packet_state_S <= c_CMD1; +-- soda_dlm_preview_S <= '1'; +-- soda_pkt_valid_S <= '1'; +-- soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24); when c_CMD1 => - packet_state_S <= c_CMD2; - soda_dlm_preview_S <= '1'; - soda_pkt_valid_S <= '0'; - TIME_CAL_OUT <= soda_cmd_word_S(30); + build_packet_bits_S <= x"22"; + build_packet_state_S <= c_CMD2; + soda_dlm_preview_S <= '1'; + reg1_soda_pkt_valid_S <= '0'; + TIME_CAL_OUT <= soda_cmd_word_S(30); when c_CMD2 => - packet_state_S <= c_CMD3; - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= soda_cmd_word_S(23 downto 16); - TIME_CAL_OUT <= '0'; + build_packet_bits_S <= x"23"; + build_packet_state_S <= c_CMD3; + reg1_soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= soda_cmd_word_S(23 downto 16); + TIME_CAL_OUT <= '0'; when c_CMD3 => - packet_state_S <= c_CMD4; - soda_pkt_valid_S <= '0'; + build_packet_bits_S <= x"24"; + build_packet_state_S <= c_CMD4; + reg1_soda_pkt_valid_S <= '0'; when c_CMD4 => - packet_state_S <= c_CMD5; - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= soda_cmd_word_S(15 downto 8); + build_packet_bits_S <= x"25"; + build_packet_state_S <= c_CMD5; + reg1_soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= soda_cmd_word_S(15 downto 8); when c_CMD5 => - packet_state_S <= c_CMD6; - soda_pkt_valid_S <= '0'; + build_packet_bits_S <= x"26"; + build_packet_state_S <= c_CMD6; + reg1_soda_pkt_valid_S <= '0'; when c_CMD6 => - packet_state_S <= c_CMD7; - soda_pkt_valid_S <= '1'; - soda_pkt_word_S <= soda_cmd_word_S(7 downto 0); - EXPECTED_REPLY_OUT <= soda_cmd_word_S(7 downto 0); + build_packet_bits_S <= x"27"; + build_packet_state_S <= c_CMD7; + reg1_soda_pkt_valid_S <= '1'; + soda_pkt_word_S <= soda_cmd_word_S(7 downto 0); + EXPECTED_REPLY_OUT <= soda_cmd_word_S(7 downto 0); when c_CMD7 => if (crc_valid_S = '0') then - packet_state_S <= c_ERROR; + build_packet_bits_S <= x"0E"; + build_packet_state_S <= c_ERROR; else - packet_state_S <= c_CMD8; + build_packet_bits_S <= x"28"; + build_packet_state_S <= c_CMD8; end if; - soda_dlm_preview_S <= '0'; - soda_pkt_valid_S <= '0'; + soda_dlm_preview_S <= '0'; + reg1_soda_pkt_valid_S <= '0'; when c_CMD8 => - packet_state_S <= c_IDLE; - soda_dlm_preview_S <= '0'; - soda_pkt_valid_S <= '0'; - soda_pkt_word_S <= (others=>'0'); + build_packet_bits_S <= x"00"; + build_packet_state_S <= c_IDLE; + soda_dlm_preview_S <= '0'; + reg1_soda_pkt_valid_S <= '0'; + soda_pkt_word_S <= (others=>'0'); when c_ERROR => - packet_state_S <= c_IDLE; - soda_dlm_preview_S <= '0'; - soda_pkt_valid_S <= '0'; + build_packet_bits_S <= x"00"; + build_packet_state_S <= c_IDLE; + soda_dlm_preview_S <= '0'; + reg1_soda_pkt_valid_S <= '0'; when others => - packet_state_S <= c_IDLE; - soda_dlm_preview_S <= '0'; - soda_pkt_valid_S <= '0'; + build_packet_bits_S <= x"00"; + build_packet_state_S <= c_IDLE; + soda_dlm_preview_S <= '0'; + reg1_soda_pkt_valid_S <= '0'; end case; end if; end if; @@ -229,10 +348,10 @@ begin -- end process; - crc_gen_proc : process(SODACLK, packet_state_S) + crc_gen_proc : process(SODACLK, build_packet_state_S) begin if rising_edge(SODACLK) then - case packet_state_S is + case build_packet_state_S is when c_IDLE => crc_data_valid_S <= '0'; crc_datain_S <= (others=>'0'); @@ -287,16 +406,5 @@ begin end if; end process; - -cmd_window_gen : soda_cmd_window_generator - generic map(CLOCK_PERIOD => cSODA_CLOCK_PERIOD, -- clock-period in ns - COMMAND_WINDOS_SIZE => cSODA_COMMAND_WINDOS_SIZE -- command window size in ns - ) - port map(SODACLK => SODACLK, - RESET => RESET, - START_OF_SUPERBURST_IN => START_OF_SUPERBURST, - SODA_CMD_WINDOW_OUT => soda_cmd_window_S - ); - end architecture; \ No newline at end of file diff --git a/code/soda_reply_pkt_builder.vhd b/code/soda_reply_pkt_builder.vhd index de1840e..cbcacb7 100644 --- a/code/soda_reply_pkt_builder.vhd +++ b/code/soda_reply_pkt_builder.vhd @@ -1,6 +1,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; library work; use work.trb_net_std.all; @@ -28,83 +30,126 @@ end soda_reply_pkt_builder; architecture soda_reply_pkt_builder_arch of soda_reply_pkt_builder is - type packet_state_type is ( c_IDLE, c_ERROR, + type reply_packet_state_type is ( c_IDLE, c_ERROR, c_WAIT4BST1, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8, c_WAIT4CMD1, c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8 ); - signal packet_state_S : packet_state_type := c_IDLE; + signal reply_packet_state_S : reply_packet_state_type := c_IDLE; + signal reply_packet_bits_S : std_logic_vector(7 downto 0) := (others => '0'); signal soda_dlm_preview_S : std_logic; + signal sequence_error_S : std_logic; + signal next_superburst_nr_S : std_logic_vector(30 downto 0); + begin - TX_DLM_PREVIEW_OUT <= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1'))) or - ((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1'))) - else '0'; +-- TX_DLM_PREVIEW_OUT <= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1'))) or +-- ((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1'))) +-- else '0'; + TX_DLM_PREVIEW_OUT <= soda_dlm_preview_S; + +sequence_check_proc : process(SODACLK) + begin + if rising_edge(SODACLK) then + if (RESET='1') then + sequence_error_S <= '0'; + next_superburst_nr_S <= (others => '0'); + else + case reply_packet_state_S is + when c_IDLE => + if (START_OF_SUPERBURST='1') then + if (SUPER_BURST_NR_IN=next_superburst_nr_S) then + sequence_error_S <= '0'; + else + sequence_error_S <= '1'; + end if; + end if; +-- when c_BST1 => +-- sequence_error_S <= '0'; +-- next_superburst_nr_S <= SUPER_BURST_NR_IN + 1; + when c_BST2 => + sequence_error_S <= '0'; + next_superburst_nr_S <= SUPER_BURST_NR_IN + 1; + when others => + end case; + end if; + end if; + end process; reply_fsm_proc : process(SODACLK) begin if rising_edge(SODACLK) then - if (RESET='1') then - packet_state_S <= c_IDLE; + if (RESET='1') then + reply_packet_bits_S <= x"00"; + reply_packet_state_S <= c_IDLE; soda_dlm_preview_S <= '0'; TX_DLM_OUT <= '0'; TX_DLM_WORD_OUT <= (others=>'0'); else - case packet_state_S is + case reply_packet_state_S is when c_IDLE => - if (START_OF_SUPERBURST='1') then + if (START_OF_SUPERBURST='1') then soda_dlm_preview_S <= '1'; if (LINK_PHASE_IN = c_PHASE_H) then - packet_state_S <= c_BST1; - TX_DLM_OUT <= '1'; - TX_DLM_WORD_OUT <= SUPER_BURST_NR_IN(7 downto 0); + reply_packet_bits_S <= x"11"; + reply_packet_state_S <= c_BST1; + TX_DLM_OUT <= '1'; + TX_DLM_WORD_OUT <= SUPER_BURST_NR_IN(7 downto 0); else - packet_state_S <= c_WAIT4BST1; - TX_DLM_OUT <= '0'; + reply_packet_bits_S <= x"10"; + reply_packet_state_S <= c_WAIT4BST1; + TX_DLM_OUT <= '0'; end if; elsif (SODA_CMD_STROBE_IN='1') then - soda_dlm_preview_S <= '1'; + soda_dlm_preview_S <= '1'; if (LINK_PHASE_IN = c_PHASE_H) then - packet_state_S <= c_CMD1; - TX_DLM_OUT <= '1'; - TX_DLM_WORD_OUT <= '1' & SODA_CMD_WORD_IN(30 downto 24); + reply_packet_bits_S <= x"21"; + reply_packet_state_S <= c_CMD1; + TX_DLM_OUT <= '1'; + TX_DLM_WORD_OUT <= SODA_CMD_WORD_IN(7 downto 0); --'1' & SODA_CMD_WORD_IN(30 downto 24); else - packet_state_S <= c_WAIT4CMD1; - TX_DLM_OUT <= '0'; + reply_packet_bits_S <= x"20"; + reply_packet_state_S <= c_WAIT4CMD1; + TX_DLM_OUT <= '0'; end if; end if; when c_WAIT4BST1 => - packet_state_S <= c_BST1; - soda_dlm_preview_S <= '1'; - TX_DLM_OUT <= '1'; - TX_DLM_WORD_OUT <= SUPER_BURST_NR_IN(7 downto 0); + reply_packet_bits_S <= x"11"; + reply_packet_state_S <= c_BST1; + soda_dlm_preview_S <= '1'; + TX_DLM_OUT <= '1'; + TX_DLM_WORD_OUT <= SUPER_BURST_NR_IN(7 downto 0); when c_BST1 => - packet_state_S <= c_BST2; - TX_DLM_OUT <= '0'; - soda_dlm_preview_S <= '0'; + reply_packet_bits_S <= x"12"; + reply_packet_state_S <= c_BST2; + TX_DLM_OUT <= '0'; + soda_dlm_preview_S <= '0'; when c_BST2 => - packet_state_S <= c_IDLE; + reply_packet_bits_S <= x"00"; + reply_packet_state_S <= c_IDLE; when c_WAIT4CMD1 => - packet_state_S <= c_CMD1; - soda_dlm_preview_S <= '1'; - TX_DLM_OUT <= '1'; - TX_DLM_WORD_OUT <= '1' & SODA_CMD_WORD_IN(30 downto 24); + reply_packet_bits_S <= x"21"; + reply_packet_state_S <= c_CMD1; + soda_dlm_preview_S <= '1'; + TX_DLM_OUT <= '1'; + TX_DLM_WORD_OUT <= SODA_CMD_WORD_IN(7 downto 0); --'1' & SODA_CMD_WORD_IN(30 downto 24); when c_CMD1 => - packet_state_S <= c_CMD2; - TX_DLM_OUT <= '0'; - soda_dlm_preview_S <= '0'; + reply_packet_bits_S <= x"22"; + reply_packet_state_S <= c_CMD2; + TX_DLM_OUT <= '0'; + soda_dlm_preview_S <= '0'; when c_CMD2 => - packet_state_S <= c_IDLE; - when others => - packet_state_S <= c_IDLE; - TX_DLM_OUT <= '0'; - soda_dlm_preview_S <= '0'; + reply_packet_bits_S <= x"00"; + reply_packet_state_S <= c_IDLE; + when others => + reply_packet_bits_S <= x"00"; + reply_packet_state_S <= c_IDLE; + TX_DLM_OUT <= '0'; + soda_dlm_preview_S <= '0'; end case; end if; end if; - end process; - - + end process; end soda_reply_pkt_builder_arch; \ No newline at end of file diff --git a/code/trb3_periph_sodasource.vhd b/code/trb3_periph_sodasource.vhd index be52ac3..450bcca 100644 --- a/code/trb3_periph_sodasource.vhd +++ b/code/trb3_periph_sodasource.vhd @@ -123,12 +123,12 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is signal GSR_N : std_logic; attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; - signal clk_sys_internal : std_logic; - signal clk_raw_internal : std_logic; - signal rx_clock_half : std_logic; - signal rx_clock_full : std_logic; - signal clk_tdc : std_logic; - signal time_counter, time_counter2 : unsigned(31 downto 0); + signal clk_100_osc : std_logic; + signal clk_200_osc : std_logic; +-- signal rx_clock_half : std_logic; +-- signal rx_clock_full : std_logic; +-- signal clk_tdc : std_logic; + signal time_counter : unsigned(31 downto 0); --Media Interface signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0); signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0); @@ -233,10 +233,10 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is attribute syn_keep of soda_tx_clock_full : signal is true; attribute syn_preserve of soda_tx_clock_half : signal is true; attribute syn_keep of soda_tx_clock_half : signal is true; - attribute syn_preserve of clk_sys_internal : signal is true; - attribute syn_keep of clk_sys_internal : signal is true; - attribute syn_preserve of clk_raw_internal : signal is true; - attribute syn_keep of clk_raw_internal : signal is true; + attribute syn_preserve of clk_100_osc : signal is true; + attribute syn_keep of clk_100_osc : signal is true; + attribute syn_preserve of clk_200_osc : signal is true; + attribute syn_keep of clk_200_osc : signal is true; attribute syn_preserve of tx_dlm_i : signal is true; attribute syn_keep of tx_dlm_i : signal is true; attribute syn_preserve of rx_dlm_i : signal is true; @@ -257,8 +257,8 @@ begin port map( CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_sys_internal, -- PLL/DLL remastered clock + CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) @@ -275,27 +275,27 @@ gen_200_PLL : if USE_125_MHZ = c_NO generate THE_MAIN_PLL : pll_in200_out100 port map( CLK => CLK_GPLL_RIGHT, - CLKOP => clk_sys_internal, - CLKOK => clk_raw_internal, + CLKOP => clk_100_osc, + CLKOK => clk_200_osc, LOCK => pll_lock ); end generate; gen_125 : if USE_125_MHZ = c_YES generate - clk_sys_internal <= CLK_GPLL_LEFT; - clk_raw_internal <= CLK_GPLL_LEFT; + clk_100_osc <= CLK_GPLL_LEFT; + clk_200_osc <= CLK_GPLL_LEFT; end generate; --gen_sync_clocks : if SYNC_MODE = c_YES generate -- clk_sys_i <= soda_tx_clock_half; -- clk_200_i <= soda_tx_clock_full; --- clk_sys_internal <= soda_tx_clock_half; --- clk_raw_internal <= soda_tx_clock_full; +-- clk_100_osc <= soda_tx_clock_half; +-- clk_200_osc <= soda_tx_clock_full; --end generate; --gen_local_clocks : if SYNC_MODE = c_NO generate --- clk_sys_i <= clk_sys_internal; --- clk_200_ip <= clk_raw_internal; +-- clk_sys_i <= clk_100_osc; +-- clk_200_ip <= clk_200_osc; --end generate; @@ -312,8 +312,8 @@ end generate; USE_SLAVE => SYNC_MODE ) port map( - CLK => clk_raw_internal, - SYSCLK => clk_sys_internal, + CLK => clk_200_osc, + SYSCLK => clk_100_osc, RESET => reset_i, CLEAR => clear_i, CLK_EN => '1', @@ -379,7 +379,7 @@ THE_HUB : trb_net16_hub_base CLOCK_FREQUENCY => CLOCK_FREQUENCY ) port map ( - CLK => clk_sys_internal, --clk_sys_i, PL! 30062014 + CLK => clk_100_osc, --clk_sys_i, PL! 30062014 RESET => reset_i, CLK_EN => '1', @@ -431,7 +431,7 @@ THE_HUB : trb_net16_hub_base PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0) ) port map( - CLK => clk_sys_internal, + CLK => clk_100_osc, RESET => reset_i, DAT_ADDR_IN => regio_addr_out, @@ -512,7 +512,7 @@ THE_HUB : trb_net16_hub_base THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch port map( - CLK_IN => clk_sys_internal, + CLK_IN => clk_100_osc, RESET_IN => reset_i, BUS_ADDR_IN => spimem_addr, @@ -545,8 +545,8 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down IS_SYNC_SLAVE => c_NO ) port map( - OSCCLK => clk_raw_internal, - SYSCLK => clk_sys_internal, + OSCCLK => clk_200_osc, + SYSCLK => clk_100_osc, RESET => reset_i, CLEAR => clear_i, --Internal Connection for TrbNet data -> not used a.t.m. @@ -606,7 +606,7 @@ THE_SOB_SOURCE : soda_start_of_burst_faker BURST_PERIOD => cBURST_PERIOD -- burst-period in ns ) port map( - SYSCLK => soda_tx_clock_half, --clk_sys_internal, PL! 30062014 + SYSCLK => soda_tx_clock_half, --clk_100_osc, PL! 30062014 RESET => reset_i, SODA_BURST_PULSE_OUT => SOB_S ); @@ -615,8 +615,8 @@ THE_SOB_SOURCE : soda_start_of_burst_faker THE_SODA_SOURCE : soda_source port map( - SYSCLK => soda_tx_clock_half, --clk_sys_internal, --clk_sys_i, PL! 30062014 - SODACLK => soda_tx_clock_full, --clk_raw_internal, -- PL! 30062014 + SYSCLK => soda_tx_clock_half, --clk_100_osc, --clk_sys_i, PL! 30062014 + SODACLK => soda_tx_clock_full, --clk_200_osc, -- PL! 30062014 RESET => reset_i, --Internal Connection SODA_BURST_PULSE_IN => SOB_S, @@ -636,25 +636,6 @@ THE_SODA_SOURCE : soda_source LEDS_OUT => soda_leds ); - -raw : soda_clockscaler - port map( - CLK => clk_raw_internal, - RESET => reset_i, - CLOCK_ENABLE_OUT => open, - CLOCK_OUT => open - ); - -tx : soda_clockscaler - port map( - CLK => soda_tx_clock_full, - RESET => reset_i, - CLOCK_ENABLE_OUT => open, - CLOCK_OUT => open - - ); - - --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- @@ -662,14 +643,6 @@ tx : soda_clockscaler LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10); LED_GREEN <= med_stat_op(12); --tx_pll_lol LED_RED <= med_stat_op(11); --rx_cdr_lol --- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal); --- LED_YELLOW <= soda_leds(0); --'1'; --- LED_GREEN <= not med_stat_op(9); --- LED_RED <= not (med_stat_op(10) or med_stat_op(11)); --- LED_ORANGE <= soda_leds(0); --- LED_YELLOW <= soda_leds(1); --- LED_GREEN <= soda_leds(2); --- LED_RED <= soda_leds(3); --------------------------------------------------------------------------- -- Test Connector @@ -678,11 +651,11 @@ tx : soda_clockscaler --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- - process - begin - wait until rising_edge(soda_tx_clock_half); --clk_sys_internal); PL! 30062014 - time_counter <= time_counter + 1; - end process; +process + begin + wait until rising_edge(soda_tx_clock_half); --clk_100_osc); PL! 30062014 + time_counter <= time_counter + 1; +end process; diff --git a/code/trb_net16_soda_sync_ecp3_sfp.vhd b/code/trb_net16_soda_sync_ecp3_sfp.vhd index b933128..471762a 100644 --- a/code/trb_net16_soda_sync_ecp3_sfp.vhd +++ b/code/trb_net16_soda_sync_ecp3_sfp.vhd @@ -40,8 +40,8 @@ entity Cu_trb_net16_soda_sync_ecp3_sfp is SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz - SYNC_dlm_IN : in std_logic; - SYNC_dlm_WORD_IN : in std_logic_vector(7 downto 0); + SYNC_DLM_IN : in std_logic; + SYNC_DLM_WORD_IN : in std_logic_vector(7 downto 0); SYNC_DLM_OUT : out std_logic; SYNC_DLM_WORD_OUT : out std_logic_vector(7 downto 0); SYNC_RXD_P_IN : in std_logic; diff --git a/ctsc.ldf b/ctsc.ldf index 1b768a3..5c618dd 100644 --- a/ctsc.ldf +++ b/ctsc.ldf @@ -42,7 +42,7 @@ - + diff --git a/ctsh.ldf b/ctsh.ldf new file mode 100644 index 0000000..649498b --- /dev/null +++ b/ctsh.ldf @@ -0,0 +1,317 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ctsh.lpf b/ctsh.lpf new file mode 100644 index 0000000..a9e079d --- /dev/null +++ b/ctsh.lpf @@ -0,0 +1,161 @@ +rvl_alias "soda_rxup_full_clk" "trb_media_and_soda_sync_uplink/sync_rx_full_clk_out"; +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +BLOCK RD_DURING_WR_PATHS ; +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ; +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; +################################################################# +# To central FPGA +################################################################# +LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; +LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; +LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; +LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; +LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; +LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; +LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; +LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; +LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; +LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; +LOCATE COMP "FPGA5_COMM_10" SITE "V10"; +LOCATE COMP "FPGA5_COMM_11" SITE "W10"; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +LOCATE COMP "TEST_LINE[0]" SITE "A5" ; +LOCATE COMP "TEST_LINE[1]" SITE "A6" ; +LOCATE COMP "TEST_LINE[2]" SITE "G8" ; +LOCATE COMP "TEST_LINE[3]" SITE "F9" ; +LOCATE COMP "TEST_LINE[4]" SITE "D9" ; +LOCATE COMP "TEST_LINE[5]" SITE "D10" ; +LOCATE COMP "TEST_LINE[6]" SITE "F10" ; +LOCATE COMP "TEST_LINE[7]" SITE "E10" ; +LOCATE COMP "TEST_LINE[8]" SITE "A8" ; +LOCATE COMP "TEST_LINE[9]" SITE "B8" ; +LOCATE COMP "TEST_LINE[10]" SITE "G10" ; +LOCATE COMP "TEST_LINE[11]" SITE "G9" ; +LOCATE COMP "TEST_LINE[12]" SITE "C9" ; +LOCATE COMP "TEST_LINE[13]" SITE "C10" ; +LOCATE COMP "TEST_LINE[14]" SITE "H10" ; +LOCATE COMP "TEST_LINE[15]" SITE "H11" ; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ; +################################################################# +# Connection to AddOn +################################################################# +LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1 +LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3 +LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5 +LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7 +LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15 +LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17 +LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21 +LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23 +LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25 +LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27 +LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35 +LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 +LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2 +LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4 +LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6 +LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8 +LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 +LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18 +LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22 +LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24 +LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26 +LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28 +LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36 +LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38 +LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169 +LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171 +LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173 +LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175 +LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183 +LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185 +LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170 +LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172 +LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174 +LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176 +LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184 +LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186 +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +################################################################# +# Additional Lines to AddOn +################################################################# +#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 +#all lines are input only +#line 4/5 go to PLL input +#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 +#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 +#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "B12" ; +LOCATE COMP "FLASH_CS" SITE "E11" ; +LOCATE COMP "FLASH_DIN" SITE "E12" ; +LOCATE COMP "FLASH_DOUT" SITE "A12" ; +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +LOCATE COMP "PROGRAMN" SITE "B11" ; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13" ; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; +#coding of FPGA number +LOCATE COMP "CODE_LINE[1]" SITE "AA20" ; +LOCATE COMP "CODE_LINE[0]" SITE "Y21" ; +IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ; +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14" ; +#IOBUF PORT "SUPPL" IO_TYPE=LVDS25; +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12" ; +LOCATE COMP "LED_ORANGE" SITE "G13" ; +LOCATE COMP "LED_RED" SITE "A15" ; +LOCATE COMP "LED_YELLOW" SITE "A16" ; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; +################################################################# +#GSR_NET NET "GSR_N"; +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "TRB_MEDIA_AND_SODA_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "THE_SODA_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; + +MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; +MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ; +MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI*" 20.000000 ns ; +MULTICYCLE FROM CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI*" 20.000000 ns ; +#MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 50 ns; + +BLOCK JTAGPATHS ; +## IOBUF ALLPORTS ; +USE PRIMARY NET "clk_200_osc" ; +USE PRIMARY NET "clk_100_osc" ; +FREQUENCY NET "clk_200_osc" 200.000000 MHz ; +FREQUENCY NET "clk_100_osc" 100.000000 MHz ; + +FREQUENCY NET "soda_rxup_full_clk" 200.000000 MHz ; +FREQUENCY NET "soda_rxup_half_clk" 100.000000 MHz ; +FREQUENCY NET "soda_rxdn_full_clk" 200.000000 MHz ; +FREQUENCY NET "soda_rxdn_half_clk" 100.000000 MHz ; +#FREQUENCY NET "soda_tx_full_clk" 200.000000 MHz ; +#FREQUENCY NET "soda_tx_half_clk" 100.000000 MHz ; \ No newline at end of file diff --git a/soda4srcEP.ldf b/soda4srcEP.ldf new file mode 100644 index 0000000..63077e8 --- /dev/null +++ b/soda4srcEP.ldf @@ -0,0 +1,278 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/soda4srcEP.lpf b/soda4srcEP.lpf new file mode 100644 index 0000000..1246f20 --- /dev/null +++ b/soda4srcEP.lpf @@ -0,0 +1,167 @@ +rvl_alias "clk_200_osc" "clk_200_osc"; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; +BLOCK JTAGPATHS ; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY??? +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ; +DEFINE PORT GROUP "CLK_group" "*CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; +################################################################# +# To central FPGA +################################################################# +LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ; +LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ; +LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ; +LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ; +LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ; +LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ; +LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ; +LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ; +LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ; +LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ; +LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ; +LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +################################################################# +# Connection to AddOn +################################################################# +LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1 +LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3 +LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5 +LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7 +LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15 +LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17 +LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21 +LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23 +LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25 +LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27 +LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35 +LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 +LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2 +LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4 +LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6 +LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8 +LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 +LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18 +LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22 +LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24 +LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26 +LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28 +LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36 +LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38 +LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169 +LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171 +LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173 +LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175 +LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183 +LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185 +LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170 +LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172 +LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174 +LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176 +LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184 +LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186 +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "B12" ; +LOCATE COMP "FLASH_CS" SITE "E11" ; +LOCATE COMP "FLASH_DIN" SITE "E12" ; +LOCATE COMP "FLASH_DOUT" SITE "A12" ; +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +LOCATE COMP "PROGRAMN" SITE "B11" ; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13" ; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; +#coding of FPGA number +LOCATE COMP "CODE_LINE[1]" SITE "AA20" ; +LOCATE COMP "CODE_LINE[0]" SITE "Y21" ; +IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ; +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14" ; +#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12" ; +LOCATE COMP "LED_ORANGE" SITE "G13" ; +LOCATE COMP "LED_RED" SITE "A15" ; +LOCATE COMP "LED_YELLOW" SITE "A16" ; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; +################################################################# +# TEST LINES +################################################################# +LOCATE COMP "TEST_LINE[0]" SITE "A5" ; +LOCATE COMP "TEST_LINE[1]" SITE "A6" ; +LOCATE COMP "TEST_LINE[2]" SITE "G8" ; +LOCATE COMP "TEST_LINE[3]" SITE "F9" ; +LOCATE COMP "TEST_LINE[4]" SITE "D9" ; +LOCATE COMP "TEST_LINE[5]" SITE "D10" ; +LOCATE COMP "TEST_LINE[6]" SITE "F10" ; +LOCATE COMP "TEST_LINE[7]" SITE "E10" ; +LOCATE COMP "TEST_LINE[8]" SITE "A8" ; +LOCATE COMP "TEST_LINE[9]" SITE "B8" ; +LOCATE COMP "TEST_LINE[10]" SITE "G10" ; +LOCATE COMP "TEST_LINE[11]" SITE "G9" ; +LOCATE COMP "TEST_LINE[12]" SITE "C9" ; +LOCATE COMP "TEST_LINE[13]" SITE "C10" ; +LOCATE COMP "TEST_LINE[14]" SITE "H10" ; +LOCATE COMP "TEST_LINE[15]" SITE "H11" ; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ; +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "MED_ECP3_SODA_QUAD_SOURCE/THE_SERDES/PCSD_INST" SITE "PCSB" ; + +MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; +#MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/SCI_DATA_OUT*" 20.000000 ns ; +MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 25.000000 ns ; +MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 25.000000 ns ; +MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; + +## IOBUF ALLPORTS ; +USE PRIMARY NET "clk_200_osc" ; +USE PRIMARY NET "clk_100_osc" ; +FREQUENCY NET "clk_200_osc" 200.000000 MHz ; +FREQUENCY NET "clk_100_osc" 100.000000 MHz ; + +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_0" 200.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_1" 200.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_2" 200.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_3" 200.000000 MHz ; + +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_0" 100.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_1" 100.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_2" 100.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_3" 100.000000 MHz ; + +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_0" 200.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_1" 200.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_2" 200.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_3" 200.000000 MHz ; + +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_0" 100.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_1" 100.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_2" 100.000000 MHz ; +FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_3" 100.000000 MHz ; + +MULTICYCLE TO CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; +MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; diff --git a/soda_addressmap.txt b/soda_addressmap.txt index 870a4a3..8b86a1a 100644 --- a/soda_addressmap.txt +++ b/soda_addressmap.txt @@ -47,6 +47,15 @@ DEBUG_STATUS(2) <= CLK_EN; DEBUG_STATUS(1) <= CLEAR; DEBUG_STATUS(0) <= RESET; - +----------------------------------------------------------------------------------- +constant K_IDLE : std_logic_vector(7 downto 0) := x"BC"; +constant D_IDLE0 : std_logic_vector(7 downto 0) := x"C5"; +constant D_IDLE1 : std_logic_vector(7 downto 0) := x"50"; +constant K_SOP : std_logic_vector(7 downto 0) := x"FB"; +constant K_EOP : std_logic_vector(7 downto 0) := x"FD"; +constant K_BGN : std_logic_vector(7 downto 0) := x"1C"; +constant K_REQ : std_logic_vector(7 downto 0) := x"7C"; +constant K_RST : std_logic_vector(7 downto 0) := x"FE"; +constant K_DLM : std_logic_vector(7 downto 0) := x"DC"; diff --git a/soda_source_probe.rvl b/soda_source_probe.rvl index af0f175..177026e 100644 --- a/soda_source_probe.rvl +++ b/soda_source_probe.rvl @@ -1,19 +1,83 @@ - + - + - + + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -24,6 +88,8 @@ + + @@ -34,7 +100,6 @@ - @@ -45,6 +110,8 @@ + + @@ -55,57 +122,26 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + - - - - - - + + + - - -