From: Jan Michel Date: Fri, 5 Jun 2015 12:40:00 +0000 (+0200) Subject: added proper clock handler X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=13d8f48a656f68949ca37b00659b82e4d848efb2;p=trb3sc.git added proper clock handler --- diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd new file mode 100644 index 0000000..2e63d23 --- /dev/null +++ b/code/clock_reset_handler.vhd @@ -0,0 +1,212 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_components.all; + use work.trb_net_std.all; + use work.trb3_components.all; + use work.config.all; + +entity clock_reset_handler is + port ( + INT_CLK_IN : in std_logic; -- oscillator + EXT_CLK_IN : in std_logic; -- external clock input + NET_CLK_FULL_IN : in std_logic; -- recovered clock + NET_CLK_HALF_IN : in std_logic; + RESET_FROM_NET : in std_logic; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + + RESET_OUT : out std_logic; + CLEAR_OUT : out std_logic; + GSR_OUT : out std_logic; + + FULL_CLK_OUT : out std_logic; -- 200/240 MHz for FPGA fabric + SYS_CLK_OUT : out std_logic; -- 100/120 MHz for FPGA fabric + REF_CLK_OUT : out std_logic; -- 200/240 internal reference clock + + LED_RED_OUT : out std_logic_vector( 1 downto 0); + LED_GREEN_OUT : out std_logic_vector( 1 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture clock_reset_handler_arch of clock_reset_handler is + +attribute syn_keep : boolean; +attribute syn_preserve : boolean; + +signal clk_int_full, clk_int_half : std_logic; +signal clk_ext_full, clk_ext_half : std_logic; +signal clk_selected_full, clk_selected_half, clk_selected_ref : std_logic; + +signal pll_int_lock, pll_ext_lock : std_logic; +signal wait_for_lock : std_logic := '1'; +signal clock_select : std_logic := '0'; + +signal timer : unsigned(15 downto 0) := (others => '0'); +signal clear_n_i : std_logic := '0'; + +attribute syn_keep of clear_n_i : signal is true; +attribute syn_preserve of clear_n_i : signal is true; + +begin + +SYS_CLK_OUT <= clk_selected_half; +FULL_CLK_OUT <= clk_selected_full; +REF_CLK_OUT <= clk_selected_ref; + +LED_RED_OUT(0) <= '0' when USE_RXCLOCK = c_YES else '1'; +LED_GREEN_OUT(0) <= '0' when USE_RXCLOCK = c_NO else '1'; + +LED_GREEN_OUT(1) <= '0'; +LED_RED_OUT(1) <= clock_select; + +GSR_OUT <= not pll_int_lock or clear_n_i; + +--------------------------------------------------------------------------- +-- if RX clock is used, just forward what is provided, adjust internal as reference +--------------------------------------------------------------------------- +gen_recov_clock : if USE_RXCLOCK = c_YES generate + clk_selected_full <= NET_CLK_FULL_IN; + clk_selected_half <= NET_CLK_HALF_IN; + + timer <= (others => '1'); + + gen_200rec : if USE_120_MHZ = c_NO generate + THE_INT_PLL : entity work.pll_in240_out200 + port map( + CLK => INT_CLK_IN, + CLKOP => clk_int_full, + CLKOK => clk_int_half, + LOCK => pll_int_lock + ); + clk_selected_ref <= clk_int_full; + end generate; + + gen_240rec : if USE_120_MHZ = c_YES generate + clk_selected_ref <= INT_CLK_IN; + pll_int_lock <= '1'; + end generate; +end generate; + + +--------------------------------------------------------------------------- +-- No recovered clock +--------------------------------------------------------------------------- +gen_norecov_clock : if USE_RXCLOCK = c_NO generate + + clk_selected_ref <= clk_selected_full; + + --------------------------------------------------------------------------- + -- Make internal clock 200 MHz if required + --------------------------------------------------------------------------- + gen_200 : if USE_120_MHZ = c_NO generate + THE_INT_PLL : entity work.pll_in240_out200 + port map( + CLK => INT_CLK_IN, + CLKOP => clk_int_full, + CLKOK => clk_int_half, + LOCK => pll_int_lock + ); + + THE_EXT_PLL : pll_in200_out100 + port map( + CLK => EXT_CLK_IN, + RESET => '0', + CLKOP => clk_ext_half, + CLKOK => clk_ext_full, + LOCK => pll_ext_lock + ); + end generate; + + gen_240 : if USE_120_MHZ = c_YES generate + THE_INT_PLL : entity work.pll_in240_out240 + port map( + CLK => INT_CLK_IN, + CLKOP => clk_int_half, + CLKOK => clk_int_full, + LOCK => pll_int_lock + ); + + THE_EXT_PLL : entity work.pll_in240_out240 + port map( + CLK => EXT_CLK_IN, + CLKOP => clk_ext_half, + CLKOK => clk_ext_full, + LOCK => pll_ext_lock + ); + end generate; + + + --------------------------------------------------------------------------- + -- Select clocks + --------------------------------------------------------------------------- + THE_CLOCK_SWITCH_FULL: DCS + port map( + SEL => clock_select, + CLK0 => clk_int_full, + CLK1 => clk_ext_full, + DCSOUT => clk_selected_full + ); + THE_CLOCK_SWITCH_HALF: DCS + port map( + SEL => clock_select, + CLK0 => clk_int_half, + CLK1 => clk_ext_half, + DCSOUT => clk_selected_half + ); + + --------------------------------------------------------------------------- + -- Clock switch logic + --------------------------------------------------------------------------- + + process begin + wait until rising_edge(INT_CLK_IN); + if timer(15) = '1' and timer(0) = '0' then --after 135us + timer <= timer + 1; + clock_select <= pll_ext_lock; + elsif timer(15) = '1' and timer(0) = '1' then --after 135us plus 1 + timer <= timer; + else + timer <= timer + 1; + clock_select <= '0'; + end if; + end process; + + +end generate; + +clear_n_i <= timer(15) when rising_edge(INT_CLK_IN); + +--------------------------------------------------------------------------- +-- Reset generation +--------------------------------------------------------------------------- +THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => clear_n_i, -- reset input (low active, async) + CLK_IN => INT_CLK_IN, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_selected_half, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_int_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => RESET_FROM_NET, -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE! + RESET_OUT => RESET_OUT, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +DEBUG_OUT(0) <= pll_int_lock; +DEBUG_OUT(1) <= pll_ext_lock; +DEBUG_OUT(2) <= clock_select; +DEBUG_OUT(3) <= clear_n_i; +DEBUG_OUT(31 downto 4) <= (others => '0'); + + +end architecture; \ No newline at end of file diff --git a/cores/pll_in240_out240.ipx b/cores/pll_in240_out240.ipx new file mode 100644 index 0000000..7123d5a --- /dev/null +++ b/cores/pll_in240_out240.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/cores/pll_in240_out240.lpc b/cores/pll_in240_out240.lpc new file mode 100644 index 0000000..6315116 --- /dev/null +++ b/cores/pll_in240_out240.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8LFN1156C +SpeedGrade=8L +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.7 +ModuleName=pll_in240_out240 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/03/2015 +Time=17:25:05 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=240 +Div=2 +ClkOPBp=0 +Post=8 +U_OFrq=120 +OP_Tol=0.0 +OFrq=120.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=1 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=120 +OK_Tol=0.0 +KFrq=240.000000 +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=1.485393 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=1 +ClkOKBp=1 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_in240_out240 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -bypassk -fclkop 120 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 240 -fclkok_tol 0.0 -norst -noclkok2 -bw diff --git a/cores/pll_in240_out240.vhd b/cores/pll_in240_out240.vhd new file mode 100644 index 0000000..0bb44ff --- /dev/null +++ b/cores/pll_in240_out240.vhd @@ -0,0 +1,102 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in240_out240 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -bypassk -fclkop 120 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 240 -fclkok_tol 0.0 -norst -noclkok2 -bw + +-- Wed Jun 3 17:25:05 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_in240_out240 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + CLKOK: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in240_out240 : entity is true; +end pll_in240_out240; + +architecture Structure of pll_in240_out240 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "120.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "240.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "240.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "ENABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 1, CLKI_DIV=> 2, + FIN=> "240.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_in240_out240 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/pinout/trb3sc_basic.lpf b/pinout/trb3sc_basic.lpf index 26524ff..a077403 100644 --- a/pinout/trb3sc_basic.lpf +++ b/pinout/trb3sc_basic.lpf @@ -9,7 +9,7 @@ BLOCK RD_DURING_WR_PATHS ; SYSCONFIG MCCLK_FREQ = 20; -FREQUENCY PORT CLK_CORE_PCLK 200 MHz; #actually 240! +FREQUENCY PORT CLK_CORE_PCLK 240 MHz; FREQUENCY PORT CLK_CORE_PLL_LEFT 240 MHz; FREQUENCY PORT CLK_CORE_PLL_RIGHT 240 MHz; @@ -23,10 +23,27 @@ FREQUENCY PORT CLK_EXT_PLL_RIGHT 200 MHz; #If these signals do not exist, somebody messed around with the design... -MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; -MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns; +MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; +MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 20 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/gen_norecov_clock.clear_n_i" 20 ns; +MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; GSR_NET NET "GSR_N"; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/sci*" 20 ns; +MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/SCI_DATA_OUT*" 20 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.sci_write_i"; +BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.sci_write_i"; + +LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB" ; +REGION "MEDIA_UPLINK" "R102C95D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_UPLINK" ; + + + ################################################################# # Clock I/O ################################################################# diff --git a/scripts/compile.pl b/scripts/compile.pl index 75776b8..afed5ed 100755 --- a/scripts/compile.pl +++ b/scripts/compile.pl @@ -20,7 +20,7 @@ my $synplify_locale_workaround = "en_US\@UTF-8"; my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed - +my $twr_number_of_errors = $config{twr_number_of_errors} || 10; ################################################################################### @@ -277,7 +277,7 @@ if($par==1 || $all==1){ } else { - $c=qq|par -f "../par.p2t" $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + $c=qq|par -f "../par.p2t" $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|; execute($c); #my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd"; #system($c); @@ -296,10 +296,10 @@ if($timing==1 || $all==1){ execute($c); # TWR Timing Report - $c=qq|trce -c -v 65 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; + $c=qq|trce -c -v $twr_number_of_errors -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); - $c=qq|trce -hld -c -v 65 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; + $c=qq|trce -hld -c -v $twr_number_of_errors -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); my $c="cat $TOPNAME.par"; diff --git a/template/config.vhd b/template/config.vhd index cdd92bd..0d7909f 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -11,11 +11,11 @@ package config is ------------------------------------------------------------------------------ --Runs with 120 MHz instead of 100 MHz - constant USE_120_MHZ : integer := c_NO; --not implemented yet! - constant USE_EXTERNAL_CLOCK : integer := c_YES; + constant USE_120_MHZ : integer := c_NO; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. --Use sync mode, RX clock for all parts of the FPGA - constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + constant USE_RXCLOCK : integer := c_NO; --Address settings constant INIT_ADDRESS : std_logic_vector := x"F3CC"; diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl index 1b78812..2306fd6 100644 --- a/template/config_compile_frankfurt.pl +++ b/template/config_compile_frankfurt.pl @@ -8,5 +8,5 @@ synplify_command => "/d/jspc29/lattice/diamond/3.4_x64/bin/lin64/syn firefox_open => 0, - +twr_number_of_errors => 20, diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj index 22be06a..9d84d59 100644 --- a/template/trb3sc_basic.prj +++ b/template/trb3sc_basic.prj @@ -64,7 +64,9 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" #Basic Infrastructure add_file -vhdl -lib work "../../trb3/base/cores/pll_in200_out100.vhd" -add_file -vhdl -lib work "../../trb3/base/code/clock_switch.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" +add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd index 81addaf..f41ac6b 100644 --- a/template/trb3sc_basic.vhd +++ b/template/trb3sc_basic.vhd @@ -134,19 +134,18 @@ entity trb3sc_basic is end entity; architecture trb3sc_arch of trb3sc_basic is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal clk_half_rx, clk_full_rx : std_logic; - signal clk_sys, clk_osc : std_logic; - signal clk_200_i : std_logic; - - signal clk_half_osc, clk_half_rx : std_logic; - signal clk_full_osc, clk_full_rx : std_logic; - - signal pll_lock : std_logic; signal GSR_N : std_logic; signal reset_i : std_logic; signal clear_i : std_logic; signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal debug_clock_reset : std_logic_vector(31 downto 0); --Media Interface signal med_stat_op : std_logic_vector (1*16-1 downto 0); @@ -176,74 +175,47 @@ architecture trb3sc_arch of trb3sc_basic is signal sed_error_i : std_logic; signal clock_select : std_logic; - -begin ---------------------------------------------------------------------------- --- Reset Handling ---------------------------------------------------------------------------- - - -GSR_N <= pll_lock; -THE_RESET_HANDLER : trb_net_reset_handler - generic map( - RESET_DELAY => x"FEEE" - ) - port map( - CLEAR_IN => '0', -- reset input (high active, async) - CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_full_osc, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_sys, -- PLL/DLL remastered clock - PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) - RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) - CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! - RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) - DEBUG_OUT => open - ); - + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + attribute syn_keep of bussci_rx : signal is true; + attribute syn_preserve of bussci_rx : signal is true; + attribute syn_keep of busflash_rx : signal is true; + attribute syn_preserve of busflash_rx : signal is true; + attribute syn_keep of bussed_rx : signal is true; + attribute syn_preserve of bussed_rx : signal is true; + attribute syn_keep of bustc_rx : signal is true; + attribute syn_preserve of bustc_rx : signal is true; + +begin --------------------------------------------------------------------------- --- Clock Handling +-- Clock & Reset Handling --------------------------------------------------------------------------- - -THE_CLOCK_SELECT: entity work.clock_switch +THE_CLOCK_RESET : entity work.clock_reset_handler port map( - INT_CLK_IN => CLK_CORE_PCLK, - SYS_CLK_IN => clk_sys, + INT_CLK_IN => CLK_CORE_PCLK, + EXT_CLK_IN => CLK_EXT_PLL_LEFT, + NET_CLK_FULL_IN => clk_full_rx, + NET_CLK_HALF_IN => clk_half_rx, + RESET_FROM_NET => med_stat_op(13), - BUS_RX => bustc_rx, - BUS_TX => bustc_tx, - - PLL_LOCK => pll_lock, - RESET_IN => reset_i, - RESET_OUT => open, + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, - CLOCK_SELECT => clock_select, - DEBUG_OUT => open - ); - -THE_CLOCK_SWITCH: DCS - port map( - SEL => clock_select, - CLK0 => CLK_CORE_PCLK, - CLK1 => CLK_EXT_PCLK, - DCSOUT => clk_osc - ); + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, - -THE_MAIN_PLL : pll_in200_out100 - port map( - CLK => clk_osc, - RESET => '0', - CLKOP => clk_half_osc, - CLKOK => clk_full_osc, - LOCK => pll_lock - ); - + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, -clk_sys <= clk_half_osc; --clk_half_rx; + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset + ); --------------------------------------------------------------------------- @@ -452,13 +424,13 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_GREEN <= '0'; - LED_ORANGE <= '0'; - LED_RED <= not sed_error_i; - LED_YELLOW <= '0'; + LED_GREEN <= debug_clock_reset(0); + LED_ORANGE <= debug_clock_reset(1); + LED_RED <= debug_clock_reset(2); --not sed_error_i; + LED_YELLOW <= debug_clock_reset(3); - LED_RJ_GREEN <= '0' & not std_logic_vector(to_unsigned(USE_RXCLOCK,1)); --1 must be 0, - LED_RJ_RED <= not clock_select & std_logic_vector(to_unsigned(USE_RXCLOCK,1)); +-- LED_RJ_GREEN <= '0' & not std_logic_vector(to_unsigned(USE_RXCLOCK,1)); --1 must be 0, +-- LED_RJ_RED <= not clock_select & std_logic_vector(to_unsigned(USE_RXCLOCK,1)); LED_WHITE <= time_counter(26) & time_counter(28); LED_SFP_GREEN <= not med_stat_op(9) & '1'; --SFP Link Status LED_SFP_RED <= not (med_stat_op(10) or med_stat_op(11)) & '1'; --SFP RX/TX