From: hadaq <hadaq>
Date: Fri, 23 Mar 2012 17:42:37 +0000 (+0000)
Subject: hist dis
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=140830df6765db3beefba2586a787759ce2a52a4;p=daqdocu.git

hist dis
---

diff --git a/cts.tex b/cts.tex
index 817adc6..e49029f 100644
--- a/cts.tex
+++ b/cts.tex
@@ -76,7 +76,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
   \item [0xA0C8] Sample period for signals being histogrammed - $value*100ns$. See fig. \ref{ctsbeam}
   \item [0xA0D0 -- 0xA0C9] Registers for downscaling incoming signals, only $2^{value}$ is passing. 
   \item [0xA0D6 -- 0xA0D1] Registers for making a delay of the signal - $value * 1,25\,ns$
-  \item [0xA0D8 -- 0xA0D7] not used
+  \item [0xA0D8 -- 0xA0D7] Disable individual histograms. First 16 bits for Start used for triggering next 16 Start used for histogramming and last 8 bits (already D8 register) for VETO 
   \item [0xA0D9] -- Length of the beam itself. After this time the beam inhibit signal is set till next START BEAM signal - $value*100ns$ 
   \item [0xA0DA] -- use different parts of the START detector for histograms
     \begin{description}