From: Cahit Date: Tue, 8 Dec 2015 15:28:38 +0000 (+0100) Subject: added trailer word to the data stream to mark some errors in the DAQ X-Git-Tag: v2.3~60 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=14316c5bbb34916e26f2f43f6404cb990f766ac7;p=tdc.git added trailer word to the data stream to mark some errors in the DAQ --- diff --git a/releases/ReleaseNotes.org b/releases/ReleaseNotes.org index 7312250..e6697f0 100644 --- a/releases/ReleaseNotes.org +++ b/releases/ReleaseNotes.org @@ -8,7 +8,13 @@ |-------------+----------------+----------------------------------------------------------------------------------| | | | <80> | |-------------+----------------+----------------------------------------------------------------------------------| -| tdc\_v2.2* | 08.03.2015 | Faster clock (400 MHz) for the delay line is used. | +| tdc\_v2.4* | 08.03.2015 | Faster clock (400 MHz) for the delay line is used. | +|-------------+----------------+----------------------------------------------------------------------------------| +| tdc\_v2.3 | 08.12.2015 | Trailer word is introduced to mark some error bits. | +|-------------+----------------+----------------------------------------------------------------------------------| +| tdc\_v2.2 | 07.10.2015 | The delay line size is decreased to 288 from 304. | +| | | The trigger window end and coarse counter reset signals are distributed via SECONDARY clock nets | +| | | A bug in the semi-asynchronous stretcher (combinatoral reset signal caused blockage) is removed. | |-------------+----------------+----------------------------------------------------------------------------------| | tdc\_v2.1.5 | 22.06.2015 | Extra coarse counter reset register for higher frequency. | |-------------+----------------+----------------------------------------------------------------------------------| diff --git a/releases/tdc_v2.3/Readout_record.vhd b/releases/tdc_v2.3/Readout_record.vhd index 9c2da78..8588723 100644 --- a/releases/tdc_v2.3/Readout_record.vhd +++ b/releases/tdc_v2.3/Readout_record.vhd @@ -5,7 +5,7 @@ -- File : Readout_record.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2015-12-07 +-- Last update: 2015-12-08 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -117,12 +117,12 @@ architecture behavioral of Readout_record is signal missing_ref_time : std_logic; signal wrong_readout_fsm : std_logic; signal wrong_readout : std_logic; + signal invalid_trg_fsm : std_logic; + signal invalid_trg : std_logic; signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER := 0; signal fifo_nr_wr_fsm : integer range 0 to CHANNEL_NUMBER := 0; signal buf_delay_fsm : integer range 0 to 63 := 0; signal buf_delay : integer range 0 to 63 := 0; --- signal isLastTriggerNoTiming : std_logic := '0'; --- signal wr_trailer_fsm : std_logic; signal idle_fsm : std_logic; signal readout_fsm : std_logic; signal wait_fsm : std_logic; @@ -190,8 +190,8 @@ architecture behavioral of Readout_record is signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); -- debug signal header_error_bits : std_logic_vector(15 downto 0); - signal header_trg_type : std_logic_vector(3 downto 0); - signal header_trg_code : std_logic_vector(7 downto 0); + signal trailer_trg_type : std_logic_vector(3 downto 0); + signal trailer_trg_code : std_logic_vector(7 downto 0); signal trailer_error_bits : std_logic_vector(15 downto 0); signal rd_fsm_debug : std_logic_vector(3 downto 0); signal rd_fsm_debug_r : std_logic_vector(3 downto 0); @@ -278,8 +278,11 @@ begin -- behavioral begin if rising_edge(CLK_100) then if RESET_100 = '1' then - RD_CURRENT <= IDLE; - fifo_nr_rd <= 0; + RD_CURRENT <= IDLE; + missing_ref_time <= '0'; + wrong_readout <= '0'; + invalid_trg <= '0'; + fifo_nr_rd <= 0; else RD_CURRENT <= RD_NEXT; rd_en <= rd_en_fsm; @@ -291,6 +294,7 @@ begin -- behavioral missing_ref_time <= missing_ref_time_fsm; buf_delay <= buf_delay_fsm; wrong_readout <= wrong_readout_fsm; + invalid_trg <= invalid_trg_fsm; idle_time_up <= idle_fsm; readout_time_up <= readout_fsm; wait_time_up <= wait_fsm; @@ -316,8 +320,9 @@ begin -- behavioral wr_status_fsm <= '0'; data_finished_fsm <= '0'; trg_release_fsm <= '0'; - missing_ref_time_fsm <= '0'; + missing_ref_time_fsm <= missing_ref_time; wrong_readout_fsm <= wrong_readout; + invalid_trg_fsm <= invalid_trg; idle_fsm <= '0'; readout_fsm <= '0'; wait_fsm <= '0'; @@ -328,10 +333,12 @@ begin -- behavioral case (RD_CURRENT) is when IDLE => if READOUT_RX.valid_timing_trg = '1' then -- physical trigger - RD_NEXT <= WAIT_FOR_TRG_WIND_END; - --if isLastTriggerNoTiming = '1' then - -- wrong_readout_fsm <= '1'; - --end if; + if READOUT_RX.trg_type = x"1" then -- status trigger + RD_NEXT <= WAIT_FOR_TRG_WIND_END; + else -- the other triggers + RD_NEXT <= SEND_TRG_RELEASE_A; + data_finished_fsm <= '1'; + end if; readout_fsm <= '1'; elsif READOUT_RX.valid_notiming_trg = '1' then if READOUT_RX.trg_type = x"E" then -- status trigger @@ -346,8 +353,8 @@ begin -- behavioral data_finished_fsm <= '1'; end if; elsif READOUT_RX.invalid_trg = '1' then -- invalid trigger - RD_NEXT <= SEND_TRG_RELEASE_A; - data_finished_fsm <= '1'; + RD_NEXT <= SEND_TRG_RELEASE_A; + invalid_trg_fsm <= '1'; end if; idle_fsm <= '1'; rd_fsm_debug_fsm <= x"1"; @@ -359,7 +366,7 @@ begin -- behavioral wr_header_fsm <= '1'; end if; if MISSING_REF_TIME_IN = '1' then - missing_ref_time_fsm <= '1'; + missing_ref_time_fsm <= '1'; end if; end if; wait_fsm <= '1'; @@ -395,7 +402,6 @@ begin -- behavioral RD_NEXT <= WAIT_FOR_LVL1_TRG_B; elsif READOUT_RX.trg_timeout = '1' then RD_NEXT <= SEND_TRG_RELEASE_A; - data_finished_fsm <= '1'; end if; wait_fsm <= '1'; rd_fsm_debug_fsm <= x"6"; @@ -408,7 +414,6 @@ begin -- behavioral when WAIT_FOR_LVL1_TRG_C => if READOUT_RX.trg_spurious = '1' then wrong_readout_fsm <= '1'; --- wr_trailer_fsm <= '1'; end if; RD_NEXT <= SEND_TRG_RELEASE_A; wait_fsm <= '1'; @@ -420,7 +425,6 @@ begin -- behavioral RD_NEXT <= WAIT_FOR_LVL1_TRG_A; else RD_NEXT <= SEND_TRG_RELEASE_A; - data_finished_fsm <= '1'; end if; else wr_status_fsm <= '1'; @@ -430,6 +434,7 @@ begin -- behavioral when SEND_TRG_RELEASE_A => RD_NEXT <= SEND_TRG_RELEASE_B; + wr_trailer_fsm <= '1'; fifo_nr_rd_fsm <= 0; readout_fsm <= '1'; rd_fsm_debug_fsm <= x"A"; @@ -441,11 +446,13 @@ begin -- behavioral rd_fsm_debug_fsm <= x"B"; when SEND_TRG_RELEASE_C => - RD_NEXT <= IDLE; - trg_release_fsm <= '1'; - wrong_readout_fsm <= '0'; - readout_fsm <= '1'; - rd_fsm_debug_fsm <= x"C"; + RD_NEXT <= IDLE; + trg_release_fsm <= '1'; + missing_ref_time_fsm <= '0'; + wrong_readout_fsm <= '0'; + invalid_trg_fsm <= '0'; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"C"; when others => RD_NEXT <= IDLE; @@ -595,7 +602,8 @@ begin -- behavioral begin if rising_edge(CLK_100) then if wr_header = '1' then - data_out_r <= "001" & "0" & READOUT_RX.trg_type & READOUT_RX.trg_code & header_error_bits; + --data_out_r <= "001" & "0" & READOUT_RX.trg_type & READOUT_RX.trg_code & header_error_bits; + data_out_r <= "001" & "0" & x"000" & header_error_bits; stop_status <= '0'; elsif wr_ch_data_r = '1' then data_out_r <= ch_data_4r; @@ -621,10 +629,9 @@ begin -- behavioral when others => null; end case; i := i+1; - --elsif wr_trailer = '1' then - -- data_out_r <= "011" & "0000000000000" & trailer_error_bits; - -- data_wr_r <= '1'; - -- stop_status<= '0'; + elsif wr_trailer = '1' then + data_out_r <= "000" & "0" & trailer_trg_type & trailer_trg_code & trailer_error_bits; + stop_status <= '0'; else data_out_r <= (others => '1'); stop_status <= '0'; @@ -632,8 +639,8 @@ begin -- behavioral end if; end process Data_Out_MUX; - wr_info <= wr_header or wr_status when rising_edge(CLK_100); - wr_time <= wr_ch_data_r and ch_data_4r(31) when rising_edge(CLK_100); + wr_info <= wr_header or wr_status or wr_trailer when rising_edge(CLK_100); + wr_time <= wr_ch_data_r and ch_data_4r(31) when rising_edge(CLK_100); wr_epoch <= wr_ch_data_r and not data_out_r(31) and data_out_r(30) and data_out_r(29) and ch_data_4r(31); @@ -651,28 +658,31 @@ begin -- behavioral READOUT_DEBUG(10) <= trg_release; READOUT_DEBUG(16 downto 11) <= data_out_r(27 downto 22); READOUT_DEBUG(31 downto 17) <= (others => '0'); - + -- Error, warning bits set in the header header_error_bits(0) <= or_all(CH_ALMOST_FULL_IN); - header_error_bits(1) <= missing_ref_time; - header_error_bits(15 downto 2) <= (others => '0'); + header_error_bits(15 downto 1) <= (others => '0'); - HeaderTriggerInfo: process (CLK_100) is + -- Error, warning bits set in the trailer + trailer_error_bits(0) <= missing_ref_time; -- info from the triggerhandler + trailer_error_bits(1) <= wrong_readout; -- if there is a wrong readout because of a spurious timing trigger + trailer_error_bits(2) <= invalid_trg; -- if there is an invalid trigger + trailer_error_bits(3) <= READOUT_RX.trg_missing; -- if the trigger handler detects no reference time signal + trailer_error_bits(4) <= READOUT_RX.trg_multiple; -- if there is multiple triggers + trailer_error_bits(5) <= READOUT_RX.trg_spike; -- if there is spikes + trailer_error_bits(6) <= READOUT_RX.trg_timeout; -- if there is a timeout signal from the endpoint + trailer_error_bits(15 downto 7) <= (others => '0'); + + TrailerTriggerInfo: process (CLK_100) is begin if rising_edge(CLK_100) then -- rising clock edge - if READOUT_RX.data_valid = '1' then - header_trg_type <= READOUT_RX.trg_type when ; - header_trg_code <= READOUT_RX.trg_code when ; + if READOUT_RX.data_valid = '1' or READOUT_RX.trg_timeout = '1' then + trailer_trg_type <= READOUT_RX.trg_type; + trailer_trg_code <= READOUT_RX.trg_code; end if; end if; - end process HeaderTriggerInfo; - - - -- Error, warning bits set in the trailer - trailer_error_bits <= (others => '0'); - -- trailer_error_bits (0) <= wrong_readout; -- if there is a wrong readout because of a spurious timing trigger - + end process TrailerTriggerInfo; ------------------------------------------------------------------------------- -- Control bits diff --git a/releases/tdc_v2.3/tdc_version.vhd b/releases/tdc_v2.3/tdc_version.vhd index f7db006..9cbf33f 100644 --- a/releases/tdc_v2.3/tdc_version.vhd +++ b/releases/tdc_v2.3/tdc_version.vhd @@ -4,6 +4,6 @@ use ieee.numeric_std.all; package tdc_version is - constant TDC_VERSION : std_logic_vector(11 downto 0) := x"220"; + constant TDC_VERSION : std_logic_vector(11 downto 0) := x"230"; end;