From: Thomas Gessler Date: Fri, 24 Jul 2020 21:49:10 +0000 (+0200) Subject: Add XCKU quad-MGT core and clean up code X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=1451ab6d7a8a4def91e10ba32b7344e0cb00409c;p=trbnet.git Add XCKU quad-MGT core and clean up code --- diff --git a/media_interfaces/med_xcku_sfp_sync.vhd b/media_interfaces/med_xcku_sfp_sync.vhd index 36232f6..b23bbbe 100644 --- a/media_interfaces/med_xcku_sfp_sync.vhd +++ b/media_interfaces/med_xcku_sfp_sync.vhd @@ -149,7 +149,7 @@ SD_TXDIS_OUT <= not rx_ready_i when IS_SYNC_SLAVE = 1 else '0'; --slave only s ------------------------------------------------- gen_pcs0 : if SERDES_NUM = 0 generate -THE_GTH_8b10b : entity work.gth_8b10b +THE_GTH_8b10b : entity work.gth_xcku_x0y8_top port map( clk_100 => SYSCLK, clk_200 => CLK_INTERNAL_FULL, diff --git a/media_interfaces/med_xcku_sfp_sync_4.vhd b/media_interfaces/med_xcku_sfp_sync_4.vhd new file mode 100644 index 0000000..4098b89 --- /dev/null +++ b/media_interfaces/med_xcku_sfp_sync_4.vhd @@ -0,0 +1,259 @@ +--Media interface for Xilinx Kintex UltraScale + + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.config.all; +use work.trb_net_components.all; +use work.med_sync_define.all; + +entity med_xcku_sfp_sync_4 is + generic( + IS_SYNC_SLAVE : int_array_t(0 to 3) := (c_NO, c_NO, c_NO, c_NO); --select slave mode + IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES) + ); + port( + CLK_REF_FULL : in std_logic; -- 200 MHz reference clock + CLK_INTERNAL_FULL : in std_logic; -- internal 200 MHz, always on + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + TX_USRCLK : out std_logic; + FREECLK : in std_logic; + --Internal Connection TX + MEDIA_MED2INT : out med2int_array_t(0 to 3); + MEDIA_INT2MED : in int2med_array_t(0 to 3); + + --Sync operation + RX_DLM : out std_logic_vector(3 downto 0) := x"0"; + RX_DLM_WORD : out std_logic_vector(4*8-1 downto 0) := (others => '0'); + TX_DLM : in std_logic_vector(3 downto 0) := x"0"; + TX_DLM_WORD : in std_logic_vector(4*8-1 downto 0) := (others => '0'); + + --SFP Connection + SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable + SD_REFCLK : in std_logic; + SD_RX_N : in std_logic_vector(3 downto 0); + SD_RX_P : in std_logic_vector(3 downto 0); + SD_TX_N : out std_logic_vector(3 downto 0); + SD_TX_P : out std_logic_vector(3 downto 0); + --Control Interface + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + + -- Status and control port + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); +end entity; + + +architecture med_xcku_sfp_sync_4_arch of med_xcku_sfp_sync_4 is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of med_xcku_sfp_sync_4_arch : architecture is "media_interface_group"; + attribute syn_sharing : string; + attribute syn_sharing of med_xcku_sfp_sync_4_arch : architecture is "off"; + attribute syn_hier : string; + attribute syn_hier of med_xcku_sfp_sync_4_arch : architecture is "hard"; + +-- signal clk_200_i : std_logic; +signal clk_200_ref : std_logic; +signal clk_rx_full : std_logic; +signal clk_tx_full : std_logic; + +signal tx_data : std_logic_vector(4*8-1 downto 0); +signal tx_k : std_logic_vector(3 downto 0); +signal rx_data : std_logic_vector(4*8-1 downto 0); +signal rx_k : std_logic_vector(3 downto 0); +signal rx_error : std_logic_vector(3 downto 0); + +signal rst_n : std_logic; +signal rx_serdes_rst : std_logic_vector(3 downto 0); +signal tx_serdes_rst : std_logic_vector(3 downto 0); +signal tx_pcs_rst : std_logic_vector(3 downto 0); +signal rx_pcs_rst : std_logic_vector(3 downto 0); +signal rst_qd : std_logic_vector(3 downto 0); +signal serdes_rst_qd : std_logic_vector(3 downto 0); + +signal rx_los_low : std_logic_vector(3 downto 0); +signal lsm_status : std_logic_vector(3 downto 0); +signal rx_cdr_lol : std_logic_vector(3 downto 0); +signal tx_pll_lol : std_logic; + +signal sci_ch_i : std_logic_vector(4 downto 0); +signal sci_addr_i : std_logic_vector(5 downto 0); +signal sci_data_in_i : std_logic_vector(7 downto 0); +signal sci_data_out_i : std_logic_vector(7 downto 0); +signal sci_read_i : std_logic; +signal sci_write_i : std_logic; + +signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; +signal wa_position_sel : std_logic_vector(3 downto 0); + +signal stat_rx_control_i : std_logic_vector(4*32-1 downto 0); +signal stat_tx_control_i : std_logic_vector(4*32-1 downto 0); +signal debug_rx_control_i : std_logic_vector(4*32-1 downto 0); +signal debug_tx_control_i : std_logic_vector(4*32-1 downto 0); +signal stat_fsm_reset_i : std_logic_vector(4*32-1 downto 0); +signal debug_med_sync_control_i : std_logic_vector(31 downto 0); + +signal stat_med : std_logic_vector(127 downto 0); + +signal gtpowergood_i : std_logic_vector(3 downto 0); +signal tx_ready_i : std_logic; +signal rx_ready_i : std_logic; +signal tx_active_i : std_logic; +signal rx_active_i : std_logic; +signal rx_cdr_stable_i : std_logic; + +signal init_done_i : std_logic; + +begin + +clk_200_ref <= CLK_REF_FULL; + +SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready +-- SD_TXDIS_OUT <= (others => RESET); +------------------------------------------------- +-- Serdes +------------------------------------------------- +THE_GTH_8b10b : entity work.gth_xcku_quad_x0y2_top + port map( + clk_100 => SYSCLK, + clk_200 => CLK_INTERNAL_FULL, + reset_all => RESET, + mgtrefclk0_x0y3_int => SD_REFCLK, + FREECLK => FREECLK, + + ch0_gthrxn_in => SD_RX_N, + ch0_gthrxp_in => SD_RX_P, + ch0_gthtxn_out => SD_TX_N, + ch0_gthtxp_out => SD_TX_P, + + tx_clk => clk_tx_full, + tx_data => tx_data, + tx_k => tx_k, + + rx_clk => clk_rx_full, + rx_data => rx_data, --clk with 200MHz osci + rx_k => rx_k, + + rx_cdr_stable => rx_cdr_stable_i, + tx_pll_reset => '0',--reset_tx_pll_and_datapath_i, + rx_pll_reset => '0',--reset_rx_pll_and_datapath_i, + + tx_ready => tx_ready_i, + rx_ready => rx_ready_i, + + tx_active => tx_active_i, + rx_active => rx_active_i, + gtpowergood => gtpowergood_i, + + init_done => init_done_i, + TX_USRCLK => TX_USRCLK + ); + + tx_serdes_rst <= "0000"; --SD_LOS_IN; --no function + serdes_rst_qd <= "0000"; --included in rst_qd + wa_position_sel <= x"0"; +-- wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0 +-- else wa_position(15 downto 12) when SERDES_NUM = 3; + +gen_control : for i in 0 to 3 generate + gen_used_control : if IS_USED(i) = c_YES generate + THE_MED_CONTROL : entity work.med_sync_control + generic map( + IS_SYNC_SLAVE => IS_SYNC_SLAVE(i), + IS_TX_RESET => 1 + ) + port map( + CLK_SYS => SYSCLK, + CLK_RXI => clk_rx_full, --clk_rx_full, + CLK_RXHALF => '0', + CLK_TXI => clk_tx_full, --clk_200_ref, --clk_200_internal, --clk_tx_full, JM150706 + CLK_REF => CLK_INTERNAL_FULL, + RESET => RESET, + CLEAR => CLEAR, + + INIT_DONE => init_done_i, + + TX_ACTIVE => tx_active_i, + RX_ACTIVE => rx_active_i, + + RX_SERDES_RST => open, + TX_SERDES_RST => open, + + MEDIA_MED2INT => MEDIA_MED2INT(i), + MEDIA_INT2MED => MEDIA_INT2MED(i), + + TX_DATA => tx_data(i*8+7 downto i*8), + TX_K => tx_k(i), + RX_DATA => rx_data(i*8+7 downto i*8), + RX_K => rx_k(i), + + TX_DLM_WORD => TX_DLM_WORD(i*8+7 downto i*8), + TX_DLM => TX_DLM(i), + RX_DLM_WORD => RX_DLM_WORD(i*8+7 downto i*8), + RX_DLM => RX_DLM(i), + + SERDES_RX_READY_IN => rx_ready_i, + SERDES_TX_READY_IN => tx_ready_i, + + STAT_TX_CONTROL => stat_tx_control_i(i*32+31 downto i*32), + STAT_RX_CONTROL => stat_rx_control_i(i*32+31 downto i*32), + DEBUG_TX_CONTROL => debug_tx_control_i(i*32+31 downto i*32), + DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32), + STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32), + DEBUG_OUT => debug_med_sync_control_i + ); + end generate; + + gen_not_used : if IS_USED(i) = c_NO generate + MEDIA_MED2INT(i).dataready <= '0'; + MEDIA_MED2INT(i).tx_read <= '1'; + MEDIA_MED2INT(i).stat_op <= x"0007"; + end generate; + +-- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0); +-- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8); +-- STAT_DEBUG(7) <= '0'; +-- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0); +-- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16); +-- STAT_DEBUG(31 downto 0) <= debug_rx_control_i(31 downto 0); +-- -- -- STAT_DEBUG(3 downto 0) <= debug_med_sync_control_i(3 downto 0); +-- -- -- STAT_DEBUG(7 downto 4) <= rx_los_low(0) & lsm_status(0) & rx_cdr_lol(0) & tx_pll_lol; +-- STAT_DEBUG(9) <= CLK_REF_FULL; +-- STAT_DEBUG(10) <= clk_rx_full; +-- STAT_DEBUG(11) <= clk_tx_full; + + + stat_med(i*32+0) <= rst_qd(i); + stat_med(i*32+1) <= rx_pcs_rst(i); + stat_med(i*32+2) <= tx_pcs_rst(i); + stat_med(i*32+3) <= rx_serdes_rst(i); + stat_med(i*32+4) <= tx_pll_lol; + stat_med(i*32+5) <= rx_cdr_lol(i); + stat_med(i*32+6) <= rx_los_low(i); + stat_med(i*32+7) <= rx_ready_i; + stat_med(i*32+8) <= tx_ready_i; + stat_med(i*32+9) <= lsm_status(i); + stat_med(i*32+31 downto i*32+10) <= (others => '0'); +end generate; + +THE_BUS : process begin + wait until rising_edge(SYSCLK); + BUS_TX.unknown <= BUS_RX.read or BUS_RX.write; + BUS_TX.ack <= '0'; +end process; + +end architecture; + diff --git a/media_interfaces/xcku/clk_wiz_0/clk_wiz_0.xci b/media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xci similarity index 99% rename from media_interfaces/xcku/clk_wiz_0/clk_wiz_0.xci rename to media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xci index 3e73a58..bcca90e 100644 --- a/media_interfaces/xcku/clk_wiz_0/clk_wiz_0.xci +++ b/media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xci @@ -6,7 +6,7 @@ 1.0 - clk_wiz_0 + clk_wiz_sysclk false @@ -393,7 +393,7 @@ 0 1440.000 600.000 - clk_wiz_0 + clk_wiz_sysclk MMCM false empty @@ -494,7 +494,7 @@ false CLK_VALID auto - clk_wiz_0 + clk_wiz_sysclk daddr dclk den diff --git a/media_interfaces/xcku/clk_wiz_0/clk_wiz_0.xml b/media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xml similarity index 99% rename from media_interfaces/xcku/clk_wiz_0/clk_wiz_0.xml rename to media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xml index 790682b..888d934 100644 --- a/media_interfaces/xcku/clk_wiz_0/clk_wiz_0.xml +++ b/media_interfaces/xcku/clk_wiz_sysclk/clk_wiz_sysclk.xml @@ -2,7 +2,7 @@ xilinx.com customized_ip - clk_wiz_0 + clk_wiz_sysclk 1.0 @@ -1185,7 +1185,7 @@ outputProductCRC - 9:58c6f79d + 9:6c74f6e8 @@ -2173,7 +2173,7 @@ c_component_name - clk_wiz_0 + clk_wiz_sysclk C_PLATFORM @@ -3480,7 +3480,7 @@ Component_Name - clk_wiz_0 + clk_wiz_sysclk USER_CLK_FREQ0 diff --git a/media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xci b/media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xci similarity index 99% rename from media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xci rename to media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xci index f6efa8f..6c5a0f0 100644 --- a/media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xci +++ b/media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xci @@ -6,7 +6,7 @@ 1.0 - clk_txUsrClk + clk_wiz_tx_usrclk false @@ -400,7 +400,7 @@ 0 1440.000 600.000 - clk_txUsrClk + clk_wiz_tx_usrclk MMCM false empty @@ -501,7 +501,7 @@ false CLK_VALID auto - clk_txUsrClk + clk_wiz_tx_usrclk daddr dclk den diff --git a/media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xml b/media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xml similarity index 99% rename from media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xml rename to media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xml index cc4c11c..81cf3f7 100644 --- a/media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xml +++ b/media_interfaces/xcku/clk_wiz_tx_usrclk/clk_wiz_tx_usrclk.xml @@ -2,7 +2,7 @@ xilinx.com customized_ip - clk_txUsrClk + clk_wiz_tx_usrclk 1.0 @@ -1270,7 +1270,7 @@ outputProductCRC - 9:bd96fd14 + 9:f3d36923 @@ -2270,7 +2270,7 @@ c_component_name - clk_txUsrClk + clk_wiz_tx_usrclk C_PLATFORM @@ -3577,7 +3577,7 @@ Component_Name - clk_txUsrClk + clk_wiz_tx_usrclk USER_CLK_FREQ0 diff --git a/media_interfaces/xcku/common/gth_xcku_components.vhd b/media_interfaces/xcku/common/gth_xcku_components.vhd new file mode 100644 index 0000000..cd63634 --- /dev/null +++ b/media_interfaces/xcku/common/gth_xcku_components.vhd @@ -0,0 +1,48 @@ +library ieee; +use ieee.std_logic_1164.all; + +package gth_xcku_components is + component clk_wiz_sysclk is + port ( + clk_in1_p : in std_logic; + clk_in1_n : in std_logic; + reset : in std_logic; + clk_out1 : out std_logic; + clk_out2 : out std_logic; + locked : out std_logic + ); + end component; + + component clk_wiz_tx_usrclk is + port ( + clk_in1 : in std_logic; + reset : in std_logic; + clk_out1 : out std_logic; + clk_out2 : out std_logic; + locked : out std_logic + ); + end component; + + component IBUFDS_GTE3 is + generic ( + REFCLK_EN_TX_PATH : std_logic := '0'; + REFCLK_HROW_CK_SEL : std_logic_vector(1 downto 0) := "00"; + REFCLK_ICNTL_RX : std_logic_vector(1 downto 0) := "00" + ); + port ( + I : in std_logic; + IB : in std_logic; + CEB : in std_logic; + O : out std_logic; + ODIV2 : out std_logic_vector(0 downto 0) + ); + end component; + + component gtwizard_ultrascale_v1_7_8_bit_synchronizer + port ( + clk_in : in std_logic; + i_in : in std_logic; + o_out : out std_logic + ); + end component; +end package gth_xcku_components; diff --git a/media_interfaces/xcku/cri_gth_reset_sync.v b/media_interfaces/xcku/common/gth_xcku_init.v similarity index 93% rename from media_interfaces/xcku/cri_gth_reset_sync.v rename to media_interfaces/xcku/common/gth_xcku_init.v index e4ad660..ec2f2b6 100644 --- a/media_interfaces/xcku/cri_gth_reset_sync.v +++ b/media_interfaces/xcku/common/gth_xcku_init.v @@ -56,7 +56,7 @@ // with system bring-up such as clock or data connection readiness. This is an example and can be modified as necessary. // ===================================================================================================================== -module cri_gth_init # ( +module gth_xcku_init # ( parameter real P_FREERUN_FREQUENCY = 100, parameter real P_TX_TIMER_DURATION_US = 30000, @@ -68,7 +68,7 @@ module cri_gth_init # ( input wire reset_all_in, input wire tx_init_done_in, input wire rx_init_done_in, - input wire rx_cdr_stable_in, + input wire rx_data_good_in, output reg reset_all_out = 1'b0, output reg reset_rx_out = 1'b0, output reg init_done_out = 1'b0, @@ -85,7 +85,7 @@ module cri_gth_init # ( // The reset_all_in input should be driven by the master "reset all" example design input wire reset_all_sync; (* DONT_TOUCH = "TRUE" *) - cri_gth_q0_2_0_8_example_reset_synchronizer reset_synchronizer_reset_all_inst ( + gtwizard_ultrascale_v1_7_8_reset_synchronizer reset_synchronizer_reset_all_inst ( .clk_in (clk_freerun_in), .rst_in (reset_all_in), .rst_out (reset_all_sync) @@ -97,7 +97,7 @@ module cri_gth_init # ( // logical AND of gtwiz_reset_tx_done_out with gtwiz_buffbypass_tx_done_out if the TX buffer is bypassed. wire tx_init_done_sync; (* DONT_TOUCH = "TRUE" *) - cri_gth_q0_2_0_8_example_bit_synchronizer bit_synchronizer_tx_init_done_inst ( + gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_tx_init_done_inst ( .clk_in (clk_freerun_in), .i_in (tx_init_done_in), .o_out (tx_init_done_sync) @@ -109,19 +109,22 @@ module cri_gth_init # ( // logical AND of gtwiz_reset_rx_done_out with gtwiz_buffbypass_rx_done_out if the RX elastic buffer is bypassed. wire rx_init_done_sync; (* DONT_TOUCH = "TRUE" *) - cri_gth_q0_2_0_8_example_bit_synchronizer bit_synchronizer_rx_init_done_inst ( + gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_rx_init_done_inst ( .clk_in (clk_freerun_in), .i_in (rx_init_done_in), .o_out (rx_init_done_sync) ); - - wire rx_cdr_stable_in_sync; + // Synchronize the RX data good indicator into the free-running clock domain + // The rx_data_good_in input should be driven the user application's indication of continual good data reception. + // The example design drives rx_data_good_in high when no PRBS checker errors are seen in the 8 most recent + // consecutive clock cycles of data reception. + wire rx_data_good_sync; (* DONT_TOUCH = "TRUE" *) - cri_gth_q0_2_0_8_example_bit_synchronizer bit_synchronizer_rx_cdr_stable_inst ( + gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_rx_data_good_inst ( .clk_in (clk_freerun_in), - .i_in (rx_cdr_stable_in), - .o_out (rx_cdr_stable_in_sync) + .i_in (rx_data_good_in), + .o_out (rx_data_good_sync) ); diff --git a/media_interfaces/xcku/common/gth_xcku_init_orig.v b/media_interfaces/xcku/common/gth_xcku_init_orig.v new file mode 100644 index 0000000..98491da --- /dev/null +++ b/media_interfaces/xcku/common/gth_xcku_init_orig.v @@ -0,0 +1,288 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ===================================================================================================================== +// This example design initialization module provides a demonstration of how initialization logic can be constructed to +// interact with and enhance the reset controller helper block in order to assist with successful system bring-up. This +// example initialization logic monitors for timely reset completion, retrying resets as necessary to mitigate problems +// with system bring-up such as clock or data connection readiness. This is an example and can be modified as necessary. +// ===================================================================================================================== + +module gth_xcku_init # ( + + parameter real P_FREERUN_FREQUENCY = 100, + parameter real P_TX_TIMER_DURATION_US = 30000, + parameter real P_RX_TIMER_DURATION_US = 130000 + +)( + + input wire clk_freerun_in, + input wire reset_all_in, + input wire tx_init_done_in, + input wire rx_init_done_in, + input wire rx_data_good_in, + output reg reset_all_out = 1'b0, + output reg reset_rx_out = 1'b0, + output reg init_done_out = 1'b0, + output reg [3:0] retry_ctr_out = 4'd0 + +); + + + // ------------------------------------------------------------------------------------------------------------------- + // Synchronizers + // ------------------------------------------------------------------------------------------------------------------- + + // Synchronize the "reset all" input signal into the free-running clock domain + // The reset_all_in input should be driven by the master "reset all" example design input + wire reset_all_sync; + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_v1_7_8_reset_synchronizer reset_synchronizer_reset_all_inst ( + .clk_in (clk_freerun_in), + .rst_in (reset_all_in), + .rst_out (reset_all_sync) + ); + + // Synchronize the TX initialization done indicator into the free-running clock domain + // The tx_init_done_in input should be driven by the signal or logical combination of signals that represents a + // completed TX initialization process; for example, the reset helper block gtwiz_reset_tx_done_out signal, or the + // logical AND of gtwiz_reset_tx_done_out with gtwiz_buffbypass_tx_done_out if the TX buffer is bypassed. + wire tx_init_done_sync; + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_tx_init_done_inst ( + .clk_in (clk_freerun_in), + .i_in (tx_init_done_in), + .o_out (tx_init_done_sync) + ); + + // Synchronize the RX initialization done indicator into the free-running clock domain + // The rx_init_done_in input should be driven by the signal or logical combination of signals that represents a + // completed RX initialization process; for example, the reset helper block gtwiz_reset_rx_done_out signal, or the + // logical AND of gtwiz_reset_rx_done_out with gtwiz_buffbypass_rx_done_out if the RX elastic buffer is bypassed. + wire rx_init_done_sync; + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_rx_init_done_inst ( + .clk_in (clk_freerun_in), + .i_in (rx_init_done_in), + .o_out (rx_init_done_sync) + ); + + // Synchronize the RX data good indicator into the free-running clock domain + // The rx_data_good_in input should be driven the user application's indication of continual good data reception. + // The example design drives rx_data_good_in high when no PRBS checker errors are seen in the 8 most recent + // consecutive clock cycles of data reception. + wire rx_data_good_sync; + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_v1_7_8_bit_synchronizer bit_synchronizer_rx_data_good_inst ( + .clk_in (clk_freerun_in), + .i_in (rx_data_good_in), + .o_out (rx_data_good_sync) + ); + + + // ------------------------------------------------------------------------------------------------------------------- + // Timer + // ------------------------------------------------------------------------------------------------------------------- + + // Declare registers and local parameters used for the shared TX and RX initialization timer + // The free-running clock frequency is specified by the P_FREERUN_FREQUENCY parameter. The TX initialization timer + // duration is specified by the P_TX_TIMER_DURATION_US parameter (default 30,000us), and the resulting terminal count + // is assigned to p_tx_timer_term_cyc_int. The RX initialization timer duration is specified by the + // P_RX_TIMER_DURATION_US parameter (default 130,000us), and the resulting terminal count is assigned to + // p_rx_timer_term_cyc_int. + reg timer_clr = 1'b1; + reg [24:0] timer_ctr = 25'd0; + reg tx_timer_sat = 1'b0; + reg rx_timer_sat = 1'b0; + wire [24:0] p_tx_timer_term_cyc_int = P_TX_TIMER_DURATION_US * P_FREERUN_FREQUENCY; + wire [24:0] p_rx_timer_term_cyc_int = P_RX_TIMER_DURATION_US * P_FREERUN_FREQUENCY; + + // When the timer is enabled by the initialization state machine, increment the timer_ctr counter until its value + // reaches p_rx_timer_term_cyc_int RX terminal count and rx_timer_sat is asserted. Assert tx_timer_sat when the + // counter value reaches the p_tx_timer_term_cyc_int TX terminal count. Clear the timer and remove assertions when the + // timer is disabled by the initialization state machine. + always @(posedge clk_freerun_in) begin + if (timer_clr) begin + timer_ctr <= 25'd0; + tx_timer_sat <= 1'b0; + rx_timer_sat <= 1'b0; + end + else begin + if (timer_ctr == p_tx_timer_term_cyc_int) + tx_timer_sat <= 1'b1; + + if (timer_ctr == p_rx_timer_term_cyc_int) + rx_timer_sat <= 1'b1; + else + timer_ctr <= timer_ctr + 25'd1; + end + end + + + // ------------------------------------------------------------------------------------------------------------------- + // Retry counter + // ------------------------------------------------------------------------------------------------------------------- + + // Increment the retry_ctr_out register for each TX or RX reset asserted by the initialization state machine until the + // register saturates at 4'd15. This value, which is initialized on device programming and is never reset, could be + // useful for debugging purposes. The initialization state machine will continue to retry as needed beyond the retry + // register saturation point indicated, so 4'd15 should be interpreted as "15 or more attempts since programming." + reg retry_ctr_incr = 1'b0; + + always @(posedge clk_freerun_in) begin + if ((retry_ctr_incr == 1'b1) && (retry_ctr_out != 4'd15)) + retry_ctr_out <= retry_ctr_out + 4'd1; + end + + + // ------------------------------------------------------------------------------------------------------------------- + // Initialization state machine + // ------------------------------------------------------------------------------------------------------------------- + + // Declare local parameters and state register for the initialization state machine + localparam [1:0] ST_START = 2'd0; + localparam [1:0] ST_TX_WAIT = 2'd1; + localparam [1:0] ST_RX_WAIT = 2'd2; + localparam [1:0] ST_MONITOR = 2'd3; + reg [1:0] sm_init = ST_START; + reg sm_init_active = 1'b0; + + // Implement the initialization state machine control and its outputs as a single sequential process. The state + // machine is reset by the synchronized reset_all_in input, and does not begin operating until its first use. Note + // that this state machine is designed to interact with and enhance the reset controller helper block. + always @(posedge clk_freerun_in) begin + if (reset_all_sync) begin + timer_clr <= 1'b1; + reset_all_out <= 1'b0; + reset_rx_out <= 1'b0; + retry_ctr_incr <= 1'b0; + init_done_out <= 1'b0; + sm_init_active <= 1'b1; + sm_init <= ST_START; + end + else begin + case (sm_init) + + // When starting the initialization procedure, clear the timer and remove reset outputs, then proceed to wait + // for completion of TX initialization + ST_START: begin + if (sm_init_active) begin + timer_clr <= 1'b1; + reset_all_out <= 1'b0; + reset_rx_out <= 1'b0; + retry_ctr_incr <= 1'b0; + sm_init <= ST_TX_WAIT; + end + end + + // Enable the timer. If TX initialization completes before the counter's TX terminal count, clear the timer and + // proceed to wait for RX initialization. If the TX terminal count is reached, clear the timer, assert the + // reset_all_out output (which in this example causes a master reset_all assertion), and increment the retry + // counter. Completion conditions for TX initialization are described above. + ST_TX_WAIT: begin + if (tx_init_done_sync) begin + timer_clr <= 1'b1; + sm_init <= ST_RX_WAIT; + end + else begin + if (tx_timer_sat) begin + timer_clr <= 1'b1; + reset_all_out <= 1'b1; + retry_ctr_incr <= 1'b1; + sm_init <= ST_START; + end + else begin + timer_clr <= 1'b0; + end + end + end + + // Enable the timer. When the RX terminal count is reached, check whether RX initialization has completed and + // whether the data good indicator is high. If both conditions are met, transition to the MONITOR state. If + // either condition is not met, then clear the timer, assert the reset_rx_out output (which in this example + // either drives gtwiz_reset_rx_pll_and_datapath_in or gtwiz_reset_rx_datapath_in, depending on PLL sharing), + // and increnent the retry counter. + ST_RX_WAIT: begin + if (rx_timer_sat) begin + if (rx_init_done_sync && rx_data_good_sync) begin + init_done_out <= 1'b1; + sm_init <= ST_MONITOR; + end + else begin + timer_clr <= 1'b1; + reset_rx_out <= 1'b1; + retry_ctr_incr <= 1'b1; + sm_init <= ST_START; + end + end + else begin + timer_clr <= 1'b0; + end + end + + // In this MONITOR state, assert the init_done_out output for use as desired. If RX initialization or the data + // good indicator is lost while in this state, reset the RX components as described in the ST_RX_WAIT state. + ST_MONITOR: begin + if (~rx_init_done_sync || ~rx_data_good_sync) begin + init_done_out <= 1'b0; + timer_clr <= 1'b1; + reset_rx_out <= 1'b1; + retry_ctr_incr <= 1'b1; + sm_init <= ST_START; + end + end + + endcase + end + end + + +endmodule diff --git a/media_interfaces/xcku/cri_gth_q0_2_0_8_example_wrapper_functions.v b/media_interfaces/xcku/common/gth_xcku_wrapper_functions.v similarity index 96% rename from media_interfaces/xcku/cri_gth_q0_2_0_8_example_wrapper_functions.v rename to media_interfaces/xcku/common/gth_xcku_wrapper_functions.v index d8ab0be..b158f07 100644 --- a/media_interfaces/xcku/cri_gth_q0_2_0_8_example_wrapper_functions.v +++ b/media_interfaces/xcku/common/gth_xcku_wrapper_functions.v @@ -45,7 +45,6 @@ // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //------------------------------------------------------------------------------ - localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000; // ===================================================================================================================== diff --git a/media_interfaces/xcku/cri_gth_q0_2_0_8_example_bit_sync.v b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_bit_sync.v similarity index 84% rename from media_interfaces/xcku/cri_gth_q0_2_0_8_example_bit_sync.v rename to media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_bit_sync.v index b72c2da..b093c9c 100644 --- a/media_interfaces/xcku/cri_gth_q0_2_0_8_example_bit_sync.v +++ b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_bit_sync.v @@ -1,5 +1,5 @@ //------------------------------------------------------------------------------ -// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and @@ -46,16 +46,13 @@ // PART OF THIS FILE AT ALL TIMES. //------------------------------------------------------------------------------ +// *************************** +// * DO NOT MODIFY THIS FILE * +// *************************** `timescale 1ps/1ps -// ********************************************************************************************************************* -// IMPORTANT -// This block is delivered within the example design. If you wish to modify its behavior, be careful to understand the -// existing behavior and the effects of any modifications you may choose to make. -// ********************************************************************************************************************* - -module cri_gth_q0_2_0_8_example_bit_synchronizer # ( +module gtwizard_ultrascale_v1_7_8_bit_synchronizer # ( parameter INITIALIZE = 5'b00000, parameter FREQUENCY = 512 diff --git a/media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_rx.v b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v similarity index 88% rename from media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_rx.v rename to media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v index aa4c8aa..544ceaf 100644 --- a/media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_rx.v +++ b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v @@ -1,5 +1,5 @@ //------------------------------------------------------------------------------ -// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and @@ -46,18 +46,13 @@ // PART OF THIS FILE AT ALL TIMES. //------------------------------------------------------------------------------ +// *************************** +// * DO NOT MODIFY THIS FILE * +// *************************** `timescale 1ps/1ps -// ********************************************************************************************************************* -// IMPORTANT -// This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design. -// However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this -// core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any -// modifications you may choose to make. -// ********************************************************************************************************************* - -module cri_gth_0_2_0_8_example_gtwiz_userclk_rx #( +module gtwizard_ultrascale_v1_7_8_gtwiz_userclk_rx #( parameter integer P_CONTENTS = 0, parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1, diff --git a/media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_tx.v b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v similarity index 88% rename from media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_tx.v rename to media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v index b6e6c35..38b0b82 100644 --- a/media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_tx.v +++ b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v @@ -1,5 +1,5 @@ //------------------------------------------------------------------------------ -// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and @@ -46,18 +46,13 @@ // PART OF THIS FILE AT ALL TIMES. //------------------------------------------------------------------------------ +// *************************** +// * DO NOT MODIFY THIS FILE * +// *************************** `timescale 1ps/1ps -// ********************************************************************************************************************* -// IMPORTANT -// This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design. -// However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this -// core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any -// modifications you may choose to make. -// ********************************************************************************************************************* - -module cri_gth_0_2_0_8_example_gtwiz_userclk_tx #( +module gtwizard_ultrascale_v1_7_8_gtwiz_userclk_tx #( parameter integer P_CONTENTS = 0, parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1, diff --git a/media_interfaces/xcku/cri_gth_q0_2_0_8_example_reset_sync.v b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_reset_sync.v similarity index 86% rename from media_interfaces/xcku/cri_gth_q0_2_0_8_example_reset_sync.v rename to media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_reset_sync.v index 77bcaef..6ddf260 100644 --- a/media_interfaces/xcku/cri_gth_q0_2_0_8_example_reset_sync.v +++ b/media_interfaces/xcku/common/gtwizard_ultrascale_v1_7_reset_sync.v @@ -1,5 +1,5 @@ //------------------------------------------------------------------------------ -// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and @@ -46,16 +46,13 @@ // PART OF THIS FILE AT ALL TIMES. //------------------------------------------------------------------------------ +// *************************** +// * DO NOT MODIFY THIS FILE * +// *************************** `timescale 1ps/1ps -// ********************************************************************************************************************* -// IMPORTANT -// This block is delivered within the example design. If you wish to modify its behavior, be careful to understand the -// existing behavior and the effects of any modifications you may choose to make. -// ********************************************************************************************************************* - -module cri_gth_q0_2_0_8_example_reset_synchronizer # ( +module gtwizard_ultrascale_v1_7_8_reset_synchronizer # ( parameter FREQUENCY = 512 diff --git a/media_interfaces/xcku/cri_gth_define.vhd b/media_interfaces/xcku/cri_gth_define.vhd deleted file mode 100644 index 42a59d0..0000000 --- a/media_interfaces/xcku/cri_gth_define.vhd +++ /dev/null @@ -1,56 +0,0 @@ -library ieee; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - - -package cri_gth_define is - - -component clk_wiz_0 is - port ( - clk_in1_p : in std_logic; - clk_in1_n : in std_logic; - --clk_in1 : in std_logic; - reset : in std_logic; - clk_out1 : out std_logic; - clk_out2 : out std_logic; - locked : out std_logic - ); -end component; - -component clk_txUsrClk is - port ( - clk_in1 : in std_logic; - reset : in std_logic; - clk_out1 : out std_logic; - clk_out2 : out std_logic; - locked : out std_logic - ); -end component; - -component IBUFDS_GTE3 is - generic ( - REFCLK_EN_TX_PATH : std_logic := '0'; - REFCLK_HROW_CK_SEL : std_logic_vector(1 downto 0) := "00"; - REFCLK_ICNTL_RX : std_logic_vector(1 downto 0) := "00" - ); - port(-- IBUFDS_GTE3_MGTREFCLK0_X0Y3_INST ( - I : in std_logic; - IB : in std_logic; - CEB : in std_logic; - O : out std_logic; - ODIV2 : out std_logic_vector(0 downto 0) - ); -end component; - -component cri_gth_q0_2_0_8_example_bit_synchronizer - port ( - clk_in : in std_logic; - i_in : in std_logic; - o_out : out std_logic - ); - end component; - - -end package; \ No newline at end of file diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2.xci new file mode 100644 index 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"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000" + + + C_PCIE_ENABLE + 0 + + + C_PCIE_CORECLK_FREQ + 250 + + + C_COMMON_SCALING_FACTOR + 1 + + + C_CPLL_VCO_FREQUENCY + 2578.125 + + + C_FORCE_COMMONS + 0 + + + C_FREERUN_FREQUENCY + 100 + + + C_GT_TYPE + 0 + + + C_GT_REV + 17 + + + C_INCLUDE_CPLL_CAL + 2 + + + C_ENABLE_COMMON_USRCLK + 0 + + + C_USER_GTPOWERGOOD_DELAY_EN + 0 + + + C_SIM_CPLL_CAL_BYPASS + 1 + + + C_LOCATE_COMMON + 0 + + + C_LOCATE_RESET_CONTROLLER + 0 + + + C_LOCATE_USER_DATA_WIDTH_SIZING + 0 + + + C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER + 0 + + + C_LOCATE_IN_SYSTEM_IBERT_CORE + 2 + + + C_LOCATE_RX_USER_CLOCKING + 1 + + + C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER + 0 + + + C_LOCATE_TX_USER_CLOCKING + 1 + + + C_RESET_CONTROLLER_INSTANCE_CTRL + 0 + + + C_RX_BUFFBYPASS_MODE + 0 + + + C_RX_BUFFER_BYPASS_INSTANCE_CTRL + 0 + + + C_RX_BUFFER_MODE + 1 + + + C_RX_CB_DISP + "00000000" + + + C_RX_CB_K + "00000000" + + + C_RX_CB_MAX_LEVEL + 2 + + + C_RX_CB_LEN_SEQ + 1 + + + C_RX_CB_NUM_SEQ + 0 + + + C_RX_CB_VAL + "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + + + C_RX_CC_DISP + "00110000" + + + C_RX_CC_ENABLE + 1 + + + C_RESET_SEQUENCE_INTERVAL + 0 + + + C_RX_CC_K + "00100010" + + + C_RX_CC_LEN_SEQ + 2 + + + C_RX_CC_NUM_SEQ + 2 + + + C_RX_CC_PERIODICITY + 5000 + + + C_RX_CC_VAL + "00000000000000000000001011110000010100000000000000000000000000101111000001010000" + + + C_RX_COMMA_M_ENABLE + 1 + + + C_RX_COMMA_M_VAL + "0101111100" + + + C_RX_COMMA_P_ENABLE + 1 + + + C_RX_COMMA_P_VAL + "1010000011" + + + C_RX_DATA_DECODING + 1 + + + C_RX_ENABLE + 1 + + + C_RX_INT_DATA_WIDTH + 20 + + + C_RX_LINE_RATE + 2 + + + C_RX_MASTER_CHANNEL_IDX + 8 + + + C_RX_OUTCLK_BUFG_GT_DIV + 1 + + + C_RX_OUTCLK_FREQUENCY + 100.0000000 + + + C_RX_OUTCLK_SOURCE + 1 + + + C_RX_PLL_TYPE + 0 + + + C_RX_RECCLK_OUTPUT + 0x000000000000000000000000000000000000000000000000 + + + C_RX_REFCLK_FREQUENCY + 125 + + + C_RX_SLIDE_MODE + 0 + + + C_RX_USER_CLOCKING_CONTENTS + 0 + + + C_RX_USER_CLOCKING_INSTANCE_CTRL + 0 + + + C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK + 1 + + + C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 + 1 + + + C_RX_USER_CLOCKING_SOURCE + 0 + + + C_RX_USER_DATA_WIDTH + 16 + + + C_RX_USRCLK_FREQUENCY + 100.0000000 + + + C_RX_USRCLK2_FREQUENCY + 100.0000000 + + + C_SECONDARY_QPLL_ENABLE + 0 + + + C_SECONDARY_QPLL_REFCLK_FREQUENCY + 257.8125 + + + C_TOTAL_NUM_CHANNELS + 4 + + + C_TOTAL_NUM_COMMONS + 1 + + + C_TOTAL_NUM_COMMONS_EXAMPLE + 0 + + + C_TXPROGDIV_FREQ_ENABLE + 0 + + + C_TXPROGDIV_FREQ_SOURCE + 0 + + + C_TXPROGDIV_FREQ_VAL + 100 + + + C_TX_BUFFBYPASS_MODE + 0 + + + C_TX_BUFFER_BYPASS_INSTANCE_CTRL + 0 + + + C_TX_BUFFER_MODE + 1 + + + C_TX_DATA_ENCODING + 1 + + + C_TX_ENABLE + 1 + + + C_TX_INT_DATA_WIDTH + 20 + + + C_TX_LINE_RATE + 2 + + + C_TX_MASTER_CHANNEL_IDX + 8 + + + C_TX_OUTCLK_BUFG_GT_DIV + 1 + + + C_TX_OUTCLK_FREQUENCY + 100.0000000 + + + C_TX_OUTCLK_SOURCE + 1 + + + C_TX_PLL_TYPE + 0 + + + C_TX_REFCLK_FREQUENCY + 125 + + + C_TX_USER_CLOCKING_CONTENTS + 0 + + + C_TX_USER_CLOCKING_INSTANCE_CTRL + 0 + + + C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK + 1 + + + C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 + 1 + + + C_TX_USER_CLOCKING_SOURCE + 0 + + + C_TX_USER_DATA_WIDTH + 16 + + + C_TX_USRCLK_FREQUENCY + 100.0000000 + + + C_TX_USRCLK2_FREQUENCY + 100.0000000 + + + + + + choice_list_00d9575a + 16 + 32 + 64 + + + choice_list_0fbde0c1 + 20 + + + choice_list_13717074 + -20 + -40 + + + choice_list_1fad77c0 + RXOUTCLKPMA + RXOUTCLKPCS + RXPROGDIVCLK + + + choice_list_24871ac1 + AC + DC + + + choice_list_305f448a + TXOUTCLKPMA + TXOUTCLKPCS + TXPROGDIVCLK + + + choice_list_3179277f + QPLL0 + QPLL1 + CPLL + + + choice_list_556e59ba + 0 + 100 + 200 + 300 + 400 + 500 + 600 + 700 + 800 + 900 + 1000 + 1100 + 1200 + 1300 + 1400 + 1500 + 1600 + 1700 + 1800 + 1900 + 2000 + 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716.4179104 + 719.1011236 + 727.2727273 + 735.6321839 + 738.4615385 + 744.1860465 + 750 + 752.9411765 + 761.9047619 + 771.0843373 + 774.1935484 + 780.4878049 + 786.8852459 + 790.1234568 + 800 + 810.1265823 + 813.559322 + + + choice_list_e6469819 + 1 + 2 + 4 + + + choice_list_ed5e3eb0 + QPLL0 + + + choice_pairs_03018cc1 + 1 + 2 + 0 + + + choice_pairs_0c77e1fe + 0 + 1 + + + choice_pairs_1040277f + AVTT + FLOAT + GND + PROGRAMMABLE + + + choice_pairs_1436b008 + MULTI + SINGLE + + + choice_pairs_1ebf969f + None + GTH-10GBASE-KR + GTH-10GBASE-R + GTH-12G_SDI + GTH-1G_10G_25G_switchable + GTH-3G_SDI + GTH-Aurora_64B66B + GTH-Aurora_8B10B + GTH-Bandwidth_Engine + GTH-CAUI_10 + GTH-CEI_11G_SR + GTH-CPRI_10G + GTH-CPRI_10_1G + GTH-CPRI_3G + GTH-CPRI_6G + GTH-DisplayPort_1_62G + GTH-DisplayPort_2_7G + GTH-DisplayPort_5_4G + GTH-Gigabit_Ethernet + GTH-HDMI + GTH-HD_SDI + GTH-HMC_12_5G + GTH-Interlaken_10G + GTH-Interlaken_12_5G + GTH-Interlaken_6_25G + GTH-JESD204 + GTH-JESD204_3_125G + GTH-JESD204_6_375G + GTH-OTL4_10 + GTH-OTU2 + GTH-OTU2e + GTH-QSGMII + GTH-RXAUI + GTH-SATA + GTH-SRIO_Gen2 + GTH-XAUI + GTH-XLAUI + + + choice_pairs_40d02874 + 10GBASE_KR + CUSTOM + PCIE_GEN1_GEN2 + PCIE_GEN3 + QPI + + + choice_pairs_4e550952 + NONE + EXAMPLE_DESIGN + + + choice_pairs_7b0c3758 + RX + BOTH + TX + + + choice_pairs_85f99b7f + K28.1 + K28.5 + NONE + + + choice_pairs_8846c8f0 + RAW + 8B10B + 64B66B + 64B66B_CAUI + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_88c85933 + 8B10B + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + RAW + 64B66B + 64B66B_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_93c2d4ee + CORE + EXAMPLE_DESIGN + + + choice_pairs_9c19f015 + 1 + 2 + + + choice_pairs_a537ddda + 0 + 1 + + + choice_pairs_aa541099 + AUTO + DFE + LPM + + + choice_pairs_ae574462 + OFF + PCS + PMA + AUTO + + + choice_pairs_b0974ef0 + 1 + 2 + 0 + + + choice_pairs_d4feb97d + DISABLE + ENABLE + + + choice_pairs_f05b8192 + CHANNEL + NAME + + + The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. + + + GT_TYPE + Transceiver type + For devices which contain more than one serial transceiver type, select the type of transceiver to configure + GTH + + + INTERNAL_GT_PRIM_TYPE + gthe3 + + + + false + + + + + + GT_REV + Transceiver revision + Select the serial transceiver silicon revision + 0 + + + GT_DIRECTION + Transmit and/or Receive direction + Enable transmit and/or receive + BOTH + + + RX_ENABLE + Enabled + Enable the receiver for use + true + + + + false + + + + + + TX_ENABLE + Enabled + Enable the transmitter for use + true + + + + false + + + + + + CHANNEL_ENABLE + Enable channel + Indicate whether this transceiver channel is instantiated and enabled for use + X0Y11 X0Y10 X0Y9 X0Y8 + + + TX_MASTER_CHANNEL + Master TX channel + Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) + X0Y8 + + + RX_MASTER_CHANNEL + Master RX channel + Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) + X0Y8 + + + INTERNAL_TOTAL_NUM_CHANNELS + Total number of channels + 4 + + + + false + + + + + + INTERNAL_TOTAL_NUM_COMMONS + Total number of commons required + 1 + + + + false + + + + + + LOCATE_COMMON + Include transceiver COMMON in the + If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. + CORE + + + INTERNAL_NUM_COMMONS_CORE + Number of commons in core + 1 + + + + false + + + + + + INTERNAL_NUM_COMMONS_EXAMPLE + Number of commons in example + 0 + + + + false + + + + + + INTERNAL_TX_USRCLK_FREQUENCY + 100.0000000 + + + + false + + + + + + INTERNAL_RX_USRCLK_FREQUENCY + 100.0000000 + + + + false + + + + + + RX_PPM_OFFSET + PPM offset between receiver and transmitter + Specify the PPM offset between received data and transmitted data + 0 + + + OOB_ENABLE + Enable Out of Band signaling (OOB)/Electrical Idle + Enable or disable Out of Band signaling (OOB)/Electrical Idle + false + + + + false + + + + + + RX_SSC_PPM + Spread spectrum clocking + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Insertion loss at Nyquist (dB) + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 20 + + + PCIE_CORECLK_FREQ + 250 + + + PCIE_USERCLK_FREQ + 250 + + + TX_LINE_RATE + Line rate (Gb/s) + Enter the transmitter line rate in Gb/s + 2 + + + TX_PLL_TYPE + PLL type + Select the transmitter PLL type + QPLL0 + + + TX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type + 125 + + + TX_DATA_ENCODING + Encoding + Select the encoding format for data transmission, or choose 'Raw' for no data encoding + 8B10B + + + TX_USER_DATA_WIDTH + User data width + Select the width at which the user logic will provide parallel data to the serial transceiver for transmission + 16 + + + TX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal transmitter data path + 20 + + + TX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the transmitter buffer + 1 + + + TX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection + 0 + + + + false + + + + + + TX_OUTCLK_SOURCE + TXOUTCLK source + Select the source of TXOUTCLK + TXOUTCLKPMA + + + TX_DIFF_SWING_EMPH_MODE + Differential swing and emphasis mode + Select the transmitter differential swing and emphasis mode for your application + CUSTOM + + + RX_LINE_RATE + Line rate (Gb/s) + Enter the receiver line rate in Gb/s + 2 + + + RX_PLL_TYPE + PLL type + Select the receiver PLL type + QPLL0 + + + RX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type + 125 + + + RX_DATA_DECODING + Decoding + Select the decoding format for data reception, or choose 'Raw' for no data decoding + 8B10B + + + RX_USER_DATA_WIDTH + User data width + Select the width at which the serial transceiver will provide received parallel data to the user logic + 16 + + + RX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal receiver data path + 20 + + + RX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the receiver elastic buffer + 1 + + + RX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection + 0 + + + + false + + + + + + RX_EQ_MODE + Equalization mode + Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. + AUTO + + + RX_JTOL_FC + Mask corner frequency (MHz) + Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. + 1.19976 + + + RX_JTOL_LF_SLOPE + Mask low frequency slope (dB/decade) + Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. + -20 + + + RX_OUTCLK_SOURCE + RXOUTCLK source + Select the source of RXOUTCLK + RXOUTCLKPMA + + + SIM_CPLL_CAL_BYPASS + 1 + + + PCIE_ENABLE + false + + + RX_TERMINATION + Termination + Select the receiver termination + PROGRAMMABLE + + + RX_TERMINATION_PROG_VALUE + Programmable termination voltage (mV) + Select the termination voltage (in mV) when in programmable mode + 800 + + + RX_COUPLING + Link coupling + Select the link coupling + AC + + + RX_BUFFER_BYPASS_MODE + Receiver elastic buffer bypass mode + Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode + MULTI + + + + false + + + + + + RX_BUFFER_RESET_ON_CB_CHANGE + Reset receiver elastic buffer on channel bonding change + Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL + ENABLE + + + + false + + + + + + RX_BUFFER_RESET_ON_COMMAALIGN + Reset receiver elastic buffer on comma alignment + Control whether the receiver elastic buffer is reset on comma alignment + DISABLE + + + RX_BUFFER_RESET_ON_RATE_CHANGE + Reset receiver elastic buffer on rate change + Control whether the receiver elastic buffer is reset on rate change + ENABLE + + + TX_BUFFER_RESET_ON_RATE_CHANGE + Reset transmitter buffer on rate change + Control whether the transmitter buffer is reset on rate change + ENABLE + + + RESET_SEQUENCE_INTERVAL + Reset sequence time interval (ns) + Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval + 0 + + + RX_COMMA_PRESET + Comma value preset + NONE + + + RX_COMMA_VALID_ONLY + Valid comma values for 8B/10B decoding + Select the range of comma characters decoded by the 8B/10B decoder + 0 + + + RX_COMMA_P_ENABLE + Detect plus comma + Indicate whether or not the specified bit pattern is detected as a plus comma + true + + + RX_COMMA_M_ENABLE + Detect minus comma + Indicate whether or not the specified bit pattern is detected as a minus comma + true + + + RX_COMMA_DOUBLE_ENABLE + Detect combined plus/minus (double-length) comma + Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence + false + + + RX_COMMA_P_VAL + Plus comma value + Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received + 1010000011 + + + RX_COMMA_M_VAL + Minus comma value + Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received + 0101111100 + + + RX_COMMA_MASK + Mask + Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" + 0011111111 + + + RX_COMMA_ALIGN_WORD + Alignment boundary + Select which data byte boundaries are allowed for comma alignment + 1 + + + RX_COMMA_SHOW_REALIGN_ENABLE + Show realign comma + Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency + true + + + RX_SLIDE_MODE + Manual alignment (RXSLIDE) mode + Select whether to enable manual alignment, and in what mode if enabled + OFF + + + RX_CB_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable channel bonding, and how many sequences to use if enabled + 0 + + + RX_CB_LEN_SEQ + Length of each sequence + Select the number of characters in each channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_SKEW + Sequence maximum skew + Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_LEVEL + Maximum channel bonding level to be used + Select the maximum channel bonding level that will be used in the system channel bonding topology + 2 + + + + false + + + + + + RX_CB_MASK + 00000000 + + + + false + + + + + + RX_CB_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + + + + false + + + + + + RX_CB_K + 00000000 + + + + false + + + + + + RX_CB_DISP + 00000000 + + + + false + + + + + + RX_CB_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable clock correction, and how many sequences to use if enabled + 2 + + + RX_CC_LEN_SEQ + Length of each sequence + Select the number of characters in each channel clock correction sequence + 2 + + + RX_CC_PERIODICITY + Periodicity of the sequence (in bytes) + Specify the separation between clock correction sequences, in bytes + 5000 + + + RX_CC_KEEP_IDLE + Keep idle + Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received + DISABLE + + + RX_CC_PRECEDENCE + Precedence + Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time + ENABLE + + + + false + + + + + + RX_CC_REPEAT_WAIT + Minimum repetition + Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction + 0 + + + RX_CC_MASK + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + 00000000 + + + + false + + + + + + RX_CC_VAL + 00000000000000000000001011110000010100000000000000000000000000101111000001010000 + + + RX_CC_K + 00100010 + + + + false + + + + + + RX_CC_DISP + 00110000 + + + + false + + + + + + RX_CC_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_0 + Value + Specify the value for this clock correction sequence and pattern + 01010000 + + + RX_CC_K_0_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_1 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_0_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_0 + Value + Specify the value for this clock correction sequence and pattern + 01010000 + + + RX_CC_K_1_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + true + + + RX_CC_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_1 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_1_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + true + + + RX_CC_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + ENABLE_OPTIONAL_PORTS + Enable optional ports + Indicate whether a port should be included + + + + RX_REFCLK_SOURCE + Receiver reference clock source + Select a reference clock input to drive the PLL chosen for receiver operation + + + + TX_REFCLK_SOURCE + Transmitter reference clock source + Select a reference clock input to drive the PLL chosen for transmitter operation + + + + RX_RECCLK_OUTPUT + Drive recovered clock out of device + Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use + + + + LOCATE_RESET_CONTROLLER + Include reset controller in the + Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + LOCATE_TX_BUFFER_BYPASS_CONTROLLER + Include transmitter buffer bypass controller in the + If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_RX_BUFFER_BYPASS_CONTROLLER + Include receiver elastic buffer bypass controller in the + If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_IN_SYSTEM_IBERT_CORE + Include In-System IBERT core + Indicate whether or not the In-System IBERT core should be instantiated in the example design. + NONE + + + LOCATE_TX_USER_CLOCKING + Include simple transmitter user clocking network in the + Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_RX_USER_CLOCKING + Include simple receiver user clocking network in the + Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_USER_DATA_WIDTH_SIZING + Include user data width sizing in the + Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + ORGANIZE_PORTS_BY + In the example design, organize ports across multiple channels by + If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) + NAME + + + PRESET + Transceiver configuration preset + You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard + None + + + INTERNAL_PRESET + Transceiver configuration preset + None + + + INTERNAL_PORT_USAGE_UPDATED + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLEMENT_UPDATED + 13 + + + + false + + + + + + INTERNAL_CHANNEL_SITES_UPDATED + 3 + + + + false + + + + + + INTERNAL_CHANNEL_COLUMN_LOC_MAX + 96 + + + + false + + + + + + INTERNAL_RX_COMMA_PRESET_UPDATE + 9 + + + + false + + + + + + INTERNAL_UPDATE_IP_SYMBOL_drpclk_in + false + + + + false + + + + + + SECONDARY_QPLL_ENABLE + Enable secondary QPLL + Enable and configure the QPLL which is not used in this core configuration + false + + + SECONDARY_QPLL_LINE_RATE + Line rate of second core (Gb/s) + Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL + 10.3125 + + + + false + + + + + + SECONDARY_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection + 0 + + + + false + + + + + + SECONDARY_QPLL_REFCLK_FREQUENCY + Actual Reference clock frequency (MHz) + Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate + 257.8125 + + + + false + + + + + + TXPROGDIV_FREQ_ENABLE + Enable selectable TXOUTCLK frequency + Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency + false + + + + false + + + + + + TXPROGDIV_FREQ_SOURCE + Programmable divider clock source + Select which PLL source is used to generate the selectable TXOUTCLK frequency + QPLL0 + + + + false + + + + + + TXPROGDIV_FREQ_VAL + TXOUTCLK frequency (MHz) + Select the TXOUTCLK frequency to be generated by the TX programmable divider + 100 + + + + false + + + + + + SATA_TX_BURST_LEN + TX COM sequence burst length + Select the number of bursts that make up a SATA COM sequence + 15 + + + FREERUN_FREQUENCY + Free-running and DRP clock frequency (MHz) + Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface + 100 + + + INCLUDE_CPLL_CAL + 2 + + + USER_GTPOWERGOOD_DELAY_EN + Select 1 to enable powergood delay circuit + 1 + + + DISABLE_LOC_XDC + Select to disable generation of LOC constraints in xdc + 0 + + + ENABLE_COMMON_USRCLK + 0 + + + USB_ENABLE + false + + + PCIE_64BIT + false + + + PCIE_GEN4_EIOS + false + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGBYPASSB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGMONITORENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGPDB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK00_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN + -1 + + + + false + + + + + + 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INTERNAL_PORT_ENABLED_RXLPMOSHOLD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXLPMOSOVRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXMCOMMAALIGNEN_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXMONITORSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOOBRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSCALRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSHOLD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTCFG_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTHOLD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTOVRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTSTROBE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTTESTOVRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSOVRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOUTCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPCOMMAALIGNEN_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPCSRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPHALIGN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPHALIGNEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPHDLYPD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPHDLYRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPHOVRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPLLCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPMARESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPOLARITY_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRBSCNTRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRBSSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPROGDIVRESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXQPIEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRATE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRATEMODE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIDE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPOUTCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPPMA_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSYNCALLIN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSYNCIN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSYNCMODE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSYSCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXTERMINATION_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXUSERRDY_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXUSRCLK_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXUSRCLK2_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SIGVALIDCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TSTIN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TX8B10BBYPASS_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TX8B10BEN_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXBUFDIFFCTRL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXCOMINIT_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXCOMSAS_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXCOMWAKE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXCTRL0_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXCTRL1_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXCTRL2_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDATA_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDATAEXTENDRSVD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDCCFORCESTART_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDCCRESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDEEMPH_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDETECTRX_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDIFFCTRL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDIFFPD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDLYBYPASS_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDLYEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDLYHOLD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDLYOVRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDLYSRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDLYUPDOWN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXELECIDLE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXELFORCESTART_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXHEADER_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXINHIBIT_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXLATCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXLFPSTRESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXLFPSU2LPEXIT_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXLFPSU3WAKE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXMAINCURSOR_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXMARGIN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXMUXDCDEXHOLD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXMUXDCDORWREN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXONESZEROS_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXOUTCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPCSRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPDELECIDLEMODE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHALIGN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHALIGNEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHDLYPD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHDLYRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHDLYTSTCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHINIT_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHOVRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPIPPMEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPIPPMOVRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPIPPMPD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPIPPMSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPIPPMSTEPSIZE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPISOPD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPLLCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPMARESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPOLARITY_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPOSTCURSOR_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPOSTCURSORINV_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPRBSFORCEERR_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPRBSSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPRECURSOR_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPRECURSORINV_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPROGDIVRESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXQPIBIASEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXQPISTRONGPDOWN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXQPIWEAKPUP_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXRATE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXRATEMODE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSEQUENCE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSWING_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSYNCALLIN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSYNCIN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSYNCMODE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSYSCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXUSERRDY_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXUSRCLK_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXUSRCLK2_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BUFGTCE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BUFGTCEMASK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BUFGTDIV_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BUFGTRESET_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BUFGTRSTMASK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLFBCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLLOCK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLREFCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DMONITOROUT_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DMONITOROUTCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDO_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPRDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANDATAERROR_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTHTXN_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTHTXP_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTPOWERGOOD_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLKMONITOR_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTYTXN_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTYTXP_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEGEN3_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEIDLE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLLPD_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLLRESET_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIESYNCTXSYNCDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIEUSERGEN3RDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIEUSERPHYSTATUSRST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIEUSERRATESTART_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCSRSVDOUT_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PHYSTATUS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PINRSRVDAS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_POWERPRESENT_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RESETEXCEPTION_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXBUFSTATUS_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXBYTEISALIGNED_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXBYTEREALIGN_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCDRLOCK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCDRPHDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCHANBONDSEQ_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCHANISALIGNED_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCHANREALIGN_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCHBONDO_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCKCALDONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCLKCORCNT_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCOMINITDET_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCOMMADET_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCOMSASDET_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCOMWAKEDET_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCTRL0_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCTRL1_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCTRL2_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXCTRL3_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXDATA_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXDATAEXTENDRSVD_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXDATAVALID_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXDLYSRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXELECIDLE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXHEADER_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXHEADERVALID_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXLFPSTRESETDET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXLFPSU2LPEXITDET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXLFPSU3WAKEDET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXMONITOROUT_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTSTARTED_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTSTROBEDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOSINTSTROBESTARTED_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOUTCLK_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRBSERR_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXQPISENN_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXQPISENP_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRATEDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSTATUS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXVALID_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDCCDONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXOUTCLK_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXQPISENN_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXQPISENP_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXRATEDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT + 0 + + + + false + + + + + + Component_Name + gth_xcku_quad_x0y2 + + + + + UltraScale FPGAs Transceivers Wizard + 8 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.1 + + + + + + + diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd new file mode 100644 index 0000000..47cc1d7 --- /dev/null +++ b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_top.vhd @@ -0,0 +1,380 @@ +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.all; + +entity gth_xcku_quad_x0y2_top is + port ( + clk_100 : in std_logic; + clk_200 : in std_logic; + reset_all : in std_logic; + mgtrefclk0_x0y3_int : in std_logic; + FREECLK : in std_logic; + + ch0_gthrxn_in : in std_logic_vector(3 downto 0); + ch0_gthrxp_in : in std_logic_vector(3 downto 0); + ch0_gthtxn_out : out std_logic_vector(3 downto 0); + ch0_gthtxp_out : out std_logic_vector(3 downto 0); + + tx_clk : out std_logic; + tx_data : in std_logic_vector(31 downto 0); + tx_k : in std_logic_vector(3 downto 0); + + rx_clk : out std_logic; + rx_data : out std_logic_vector(31 downto 0); + rx_k : out std_logic_vector(3 downto 0); + + rx_cdr_stable : out std_logic; + tx_pll_reset : in std_logic; + rx_pll_reset : in std_logic; + + tx_ready : out std_logic; + rx_ready : out std_logic; + + tx_active : out std_logic; + rx_active : out std_logic; + gtpowergood : out std_logic_vector(3 downto 0); + + init_done : out std_logic; + + TX_USRCLK : out std_logic + ); +end entity gth_xcku_quad_x0y2_top; + +architecture behavioral of gth_xcku_quad_x0y2_top is + component gth_xcku_quad_x0y2_wrapper + port ( + gthrxn_in : in std_logic_vector(3 downto 0); + gthrxp_in : in std_logic_vector(3 downto 0); + gthtxn_out : out std_logic_vector(3 downto 0); + gthtxp_out : out std_logic_vector(3 downto 0); + gtwiz_userclk_tx_reset_in : in std_logic; + gtwiz_userclk_tx_srcclk_out : out std_logic; + gtwiz_userclk_tx_usrclk_out : out std_logic; + gtwiz_userclk_tx_usrclk2_out : out std_logic; + gtwiz_userclk_tx_active_out : out std_logic; + gtwiz_userclk_rx_reset_in : in std_logic; + gtwiz_userclk_rx_srcclk_out : out std_logic; + gtwiz_userclk_rx_usrclk_out : out std_logic; + gtwiz_userclk_rx_usrclk2_out : out std_logic; + gtwiz_userclk_rx_active_out : out std_logic; + gtwiz_reset_clk_freerun_in : in std_logic; + gtwiz_reset_all_in : in std_logic; + gtwiz_reset_tx_pll_and_datapath_in : in std_logic; + gtwiz_reset_tx_datapath_in : in std_logic; + gtwiz_reset_rx_pll_and_datapath_in : in std_logic; + gtwiz_reset_rx_datapath_in : in std_logic; + gtwiz_reset_rx_cdr_stable_out : out std_logic; + gtwiz_reset_tx_done_out : out std_logic; + gtwiz_reset_rx_done_out : out std_logic; + gtwiz_userdata_tx_in : in std_logic_vector(63 downto 0); + gtwiz_userdata_rx_out : out std_logic_vector(63 downto 0); + gtrefclk00_in : in std_logic; + qpll0outclk_out : out std_logic; + qpll0outrefclk_out : out std_logic; + rx8b10ben_in : in std_logic_vector(3 downto 0); + rxbufreset_in : in std_logic_vector(3 downto 0); + rxcommadeten_in : in std_logic_vector(3 downto 0); + rxmcommaalignen_in : in std_logic_vector(3 downto 0); + rxpcommaalignen_in : in std_logic_vector(3 downto 0); + tx8b10ben_in : in std_logic_vector(3 downto 0); + txctrl0_in : in std_logic_vector(63 downto 0); + txctrl1_in : in std_logic_vector(63 downto 0); + txctrl2_in : in std_logic_vector(31 downto 0); + gtpowergood_out : out std_logic_vector(3 downto 0); + rxbufstatus_out : out std_logic_vector(11 downto 0); + rxbyteisaligned_out : out std_logic_vector(3 downto 0); + rxbyterealign_out : out std_logic_vector(3 downto 0); + rxclkcorcnt_out : out std_logic_vector(7 downto 0); + rxcommadet_out : out std_logic_vector(3 downto 0); + rxctrl0_out : out std_logic_vector(63 downto 0); + rxctrl1_out : out std_logic_vector(63 downto 0); + rxctrl2_out : out std_logic_vector(31 downto 0); + rxctrl3_out : out std_logic_vector(31 downto 0); + rxpmaresetdone_out : out std_logic_vector(3 downto 0); + txpmaresetdone_out : out std_logic_vector(3 downto 0) + ); + end component gth_xcku_quad_x0y2_wrapper; + + component gth_xcku_init is + generic ( + P_FREERUN_FREQUENCY : integer := 100; + P_TX_TIMER_DURATION_US : integer := 30000; + P_RX_TIMER_DURATION_US : integer := 130000 + ); + port ( + clk_freerun_in : in std_logic; + reset_all_in : in std_logic; + tx_init_done_in : in std_logic; + rx_init_done_in : in std_logic; + rx_data_good_in : in std_logic; + reset_all_out : out std_logic := '0'; + reset_rx_out : out std_logic := '0'; + init_done_out : out std_logic := '0'; + retry_ctr_out : out std_logic_vector(3 downto 0) := x"0" + ); + end component; + + signal gtpowergood_i : std_logic_vector(3 downto 0); + signal reset_rx_cdr_stable_i : std_logic; + signal reset_tx_done_i : std_logic; + signal reset_rx_done_i : std_logic; + signal userclk_tx_active_i : std_logic; + signal userclk_tx_reset_i : std_logic := '0'; + signal userclk_tx_srcclk_i : std_logic; + signal userclk_tx_usrclk_i : std_logic; + signal userclk_tx_usrclk2_i : std_logic; + signal userclk_rx_reset_i : std_logic := '0'; + signal userclk_rx_srcclk_i : std_logic; + signal userclk_rx_usrclk_i : std_logic; + signal userclk_rx_usrclk2_i : std_logic; + signal userclk_rx_active_i : std_logic; + signal reset_tx_pll_and_datapath_i : std_logic; + signal reset_tx_datapath_i : std_logic := '0'; + signal reset_rx_pll_and_datapath_i : std_logic; + signal reset_rx_datapath_i : std_logic := '0'; + signal qpll0outclk_i : std_logic; + signal qpll0outrefclk_i : std_logic; + signal txctrl0_i : std_logic_vector(63 downto 0); + signal txctrl1_i : std_logic_vector(63 downto 0); + signal txctrl2_i : std_logic_vector(31 downto 0); + signal userdata_tx_i : std_logic_vector(63 downto 0); + signal userdata_rx_i : std_logic_vector(63 downto 0); + signal rxpmaresetdone_i : std_logic_vector(3 downto 0); + signal txpmaresetdone_i : std_logic_vector(3 downto 0); + + signal rxctrl0_i : std_logic_vector(63 downto 0); + signal rxctrl1_i : std_logic_vector(63 downto 0); + signal rxctrl2_i : std_logic_vector(31 downto 0); + signal rxctrl3_i : std_logic_vector(31 downto 0); + + signal gthrxp_i : std_logic_vector(3 downto 0); + signal gthrxn_i : std_logic_vector(3 downto 0); + signal gthtxp_i : std_logic_vector(3 downto 0); + signal gthtxn_i : std_logic_vector(3 downto 0); + + signal reset_all_i : std_logic; + signal reset_all_init : std_logic; + + signal rxcommadeten_i : std_logic_vector(3 downto 0); + signal rxmcommaalignen_i : std_logic_vector(3 downto 0); + signal rxpcommaalignen_i : std_logic_vector(3 downto 0); + + signal rxcommadet_i : std_logic_vector(3 downto 0); + signal rxbyteisaligned_i : std_logic_vector(3 downto 0); + signal rxbyterealign_i : std_logic_vector(3 downto 0); + + signal init_done_i : std_logic; + signal enable_i : std_logic; + + --VIO + signal rxclkcorcnt_i : std_logic_vector(7 downto 0); + signal rxbufstatus_i : std_logic_vector(11 downto 0); + + --RX FIFO + signal rx_empty : std_logic_vector(3 downto 0); + + --TX FIFO + signal tx_fifo_full_i : std_logic_vector(3 downto 0); + signal tx_fifo_empty_i : std_logic_vector(3 downto 0); + signal tx_fifo_valid_i : std_logic_vector(3 downto 0); + signal tx_fifo_almempty_i : std_logic_vector(3 downto 0); + signal tx_fifo_almfull_i : std_logic_vector(3 downto 0); + signal tx_fifo_wr_cnt : std_logic_vector(39 downto 0); + signal tx_fifo_wren_i : std_logic_vector(3 downto 0); + + attribute MARK_DEBUG : string; + attribute MARK_DEBUG of clk_200 : signal is "TRUE"; + attribute MARK_DEBUG of tx_data : signal is "TRUE"; + attribute MARK_DEBUG of tx_k : signal is "TRUE"; + attribute MARK_DEBUG of tx_fifo_full_i : signal is "TRUE"; + attribute MARK_DEBUG of tx_fifo_almfull_i : signal is "TRUE"; + attribute MARK_DEBUG of tx_fifo_wr_cnt : signal is "TRUE"; + attribute MARK_DEBUG of userclk_tx_usrclk2_i : signal is "TRUE"; + attribute MARK_DEBUG of reset_all : signal is "TRUE"; + attribute MARK_DEBUG of userclk_tx_active_i : signal is "TRUE"; + attribute MARK_DEBUG of reset_tx_done_i : signal is "TRUE"; + attribute MARK_DEBUG of userdata_tx_i : signal is "TRUE"; + attribute MARK_DEBUG of txctrl2_i : signal is "TRUE"; + attribute MARK_DEBUG of tx_fifo_empty_i : signal is "TRUE"; + attribute MARK_DEBUG of tx_fifo_valid_i : signal is "TRUE"; + attribute KEEP : string; + attribute KEEP of clk_200 : signal is "TRUE"; + attribute KEEP of tx_data : signal is "TRUE"; + attribute KEEP of tx_k : signal is "TRUE"; + attribute KEEP of tx_fifo_full_i : signal is "TRUE"; + attribute KEEP of tx_fifo_almfull_i : signal is "TRUE"; + attribute KEEP of tx_fifo_wr_cnt : signal is "TRUE"; + attribute KEEP of userclk_tx_usrclk2_i : signal is "TRUE"; + attribute KEEP of reset_all : signal is "TRUE"; + attribute KEEP of userclk_tx_active_i : signal is "TRUE"; + attribute KEEP of reset_tx_done_i : signal is "TRUE"; + attribute KEEP of userdata_tx_i : signal is "TRUE"; + attribute KEEP of txctrl2_i : signal is "TRUE"; + attribute KEEP of tx_fifo_empty_i : signal is "TRUE"; + attribute KEEP of tx_fifo_valid_i : signal is "TRUE"; +begin + init_done <= init_done_i; + tx_clk <= userclk_tx_usrclk2_i; + txctrl0_i <= x"0000000000000000"; + txctrl1_i <= x"0000000000000000"; + txctrl2_i(7 downto 2) <= "000000"; + txctrl2_i(15 downto 10) <= "000000"; + txctrl2_i(23 downto 18) <= "000000"; + txctrl2_i(31 downto 26) <= "000000"; + + rx_clk <= userclk_rx_usrclk2_i; + + rx_cdr_stable <= reset_rx_cdr_stable_i; + reset_tx_pll_and_datapath_i <= tx_pll_reset; + reset_rx_pll_and_datapath_i <= rx_pll_reset; + + tx_ready <= reset_tx_done_i; + rx_ready <= reset_rx_done_i; + + tx_active <= userclk_tx_active_i; + rx_active <= userclk_rx_active_i; + + gthrxn_i <= ch0_gthrxn_in; + gthrxp_i <= ch0_gthrxp_in; + ch0_gthtxn_out <= gthtxn_i; + ch0_gthtxp_out <= gthtxp_i; + + reset_all_init <= reset_all; + userclk_tx_reset_i <= not (txpmaresetdone_i(0) and txpmaresetdone_i(1) + and txpmaresetdone_i(2) and txpmaresetdone_i(3)); + userclk_rx_reset_i <= not (rxpmaresetdone_i(0) and rxpmaresetdone_i(1) + and rxpmaresetdone_i(2) and rxpmaresetdone_i(3)); + + reset_rx_datapath_i <= '0'; + reset_tx_datapath_i <= '0'; + + gtpowergood <= gtpowergood_i; + + --enable Comma detection on K28.5 + rxcommadeten_i <= "1111"; + rxmcommaalignen_i <= "1111"; + rxpcommaalignen_i <= "1111"; + TX_USRCLK <= userclk_tx_usrclk2_i; + + THE_INIT : gth_xcku_init + port map ( + clk_freerun_in => FREECLK, + reset_all_in => reset_all_init, + tx_init_done_in => reset_tx_done_i, + rx_init_done_in => reset_rx_done_i, + rx_data_good_in => '1', + reset_all_out => reset_all_i, + reset_rx_out => open, + init_done_out => init_done_i, + retry_ctr_out => open + ); + + enable_i <= '1'; + + generate_fifos: + for i in 0 to 3 generate + begin + THE_RX_FIFO : entity work.fifo_16x18x9_oreg + port map ( + Data(17) => rxctrl2_i(8 * i), + Data(16 downto 9) => userdata_rx_i(16 * i + 7 downto 16 * i), + Data( 8) => rxctrl2_i(8 * i + 1), + Data( 7 downto 0) => userdata_rx_i(16 * i + 15 downto 16 * i + 8), + WrClock => userclk_rx_usrclk2_i, + RdClock => clk_200, + WrEn => enable_i, + RdEn => enable_i, + Reset => reset_all, + Q(7 downto 0) => rx_data(8 * i + 7 downto 8 * i), + Q(8) => rx_k(i), + Empty => rx_empty(i), + Full => open, + AlmostEmpty => open, + AlmostFull => open + ); + + THE_TX_FIFO : entity work.fifo_1024x9x18_oreg_wcnt + port map ( + Data(8) => tx_k(i), + Data(7 downto 0) => tx_data(8 * i + 7 downto 8 * i), + WrClock => clk_200, + RdClock => userclk_tx_usrclk2_i, + WrEn => tx_fifo_wren_i(i), + RdEn => enable_i, + Reset => reset_all, + Q( 7 downto 0) => userdata_tx_i(16 * i + 15 downto 16 * i + 8), + Q( 8) => txctrl2_i(8 * i + 1), + Q(16 downto 9) => userdata_tx_i(16 * i + 7 downto 16 * i), + Q(17) => txctrl2_i(8 * i), + WCNT => tx_fifo_wr_cnt(10 * i + 9 downto 10 * i), + Empty => tx_fifo_empty_i(i), + Full => tx_fifo_full_i(i), + AlmostEmpty => tx_fifo_almempty_i(i), + AlmostFull => tx_fifo_almfull_i(i) + ); + + process (userclk_tx_usrclk2_i) is + begin + if rising_edge(userclk_tx_usrclk2_i) then + tx_fifo_valid_i(i) <= enable_i and not tx_fifo_empty_i(i); + end if; + end process; + + tx_fifo_wren_i(i) <= userclk_tx_active_i and reset_tx_done_i; + end generate generate_fifos; + + THE_GTH : gth_xcku_quad_x0y2_wrapper + port map( + gthrxn_in => gthrxn_i, + gthrxp_in => gthrxp_i, + gthtxn_out => gthtxn_i, + gthtxp_out => gthtxp_i, + gtwiz_userclk_tx_reset_in => userclk_tx_reset_i, + gtwiz_userclk_tx_srcclk_out => userclk_tx_srcclk_i, + gtwiz_userclk_tx_usrclk_out => userclk_tx_usrclk_i, + gtwiz_userclk_tx_usrclk2_out => userclk_tx_usrclk2_i, + gtwiz_userclk_tx_active_out => userclk_tx_active_i, + gtwiz_userclk_rx_reset_in => userclk_rx_reset_i, + gtwiz_userclk_rx_srcclk_out => userclk_rx_srcclk_i, + gtwiz_userclk_rx_usrclk_out => userclk_rx_usrclk_i, + gtwiz_userclk_rx_usrclk2_out => userclk_rx_usrclk2_i, + gtwiz_userclk_rx_active_out => userclk_rx_active_i, + gtwiz_reset_clk_freerun_in => FREECLK, + gtwiz_reset_all_in => reset_all_i, + gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_i, + gtwiz_reset_tx_datapath_in => reset_tx_datapath_i, + gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath_i, + gtwiz_reset_rx_datapath_in => reset_rx_datapath_i, + gtwiz_reset_rx_cdr_stable_out => reset_rx_cdr_stable_i, + gtwiz_reset_tx_done_out => reset_tx_done_i, + gtwiz_reset_rx_done_out => reset_rx_done_i, + gtwiz_userdata_tx_in => userdata_tx_i, + gtwiz_userdata_rx_out => userdata_rx_i, + gtrefclk00_in => mgtrefclk0_x0y3_int, + qpll0outclk_out => qpll0outclk_i, + qpll0outrefclk_out => qpll0outrefclk_i, + rx8b10ben_in => "1111", + rxbufreset_in => "0000", + rxcommadeten_in => rxcommadeten_i, + rxmcommaalignen_in => rxmcommaalignen_i, + rxpcommaalignen_in => rxpcommaalignen_i, + tx8b10ben_in => "1111", + txctrl0_in => txctrl0_i, + txctrl1_in => txctrl1_i, + txctrl2_in => txctrl2_i, + gtpowergood_out => gtpowergood_i, + rxbufstatus_out => rxbufstatus_i, + rxbyteisaligned_out => rxbyteisaligned_i, + rxbyterealign_out => rxbyterealign_i, + rxclkcorcnt_out => rxclkcorcnt_i, + rxcommadet_out => rxcommadet_i, + rxctrl0_out => rxctrl0_i, + rxctrl1_out => rxctrl1_i, + rxctrl2_out => rxctrl2_i, + rxctrl3_out => rxctrl3_i, + rxpmaresetdone_out => rxpmaresetdone_i, + txpmaresetdone_out => txpmaresetdone_i + ); +end architecture behavioral; diff --git a/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_wrapper.v b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_wrapper.v new file mode 100644 index 0000000..0f77c01 --- /dev/null +++ b/media_interfaces/xcku/gth_xcku_quad_x0y2/gth_xcku_quad_x0y2_wrapper.v @@ -0,0 +1,263 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ===================================================================================================================== +// This example design wrapper module instantiates the core and any helper blocks which the user chose to exclude from +// the core, connects them as appropriate, and maps enabled ports +// ===================================================================================================================== + +module gth_xcku_quad_x0y2_wrapper ( + input wire [3:0] gthrxn_in + ,input wire [3:0] gthrxp_in + ,output wire [3:0] gthtxn_out + ,output wire [3:0] gthtxp_out + ,input wire [0:0] gtwiz_userclk_tx_reset_in + ,output wire [0:0] gtwiz_userclk_tx_srcclk_out + ,output wire [0:0] gtwiz_userclk_tx_usrclk_out + ,output wire [0:0] gtwiz_userclk_tx_usrclk2_out + ,output wire [0:0] gtwiz_userclk_tx_active_out + ,input wire [0:0] gtwiz_userclk_rx_reset_in + ,output wire [0:0] gtwiz_userclk_rx_srcclk_out + ,output wire [0:0] gtwiz_userclk_rx_usrclk_out + ,output wire [0:0] gtwiz_userclk_rx_usrclk2_out + ,output wire [0:0] gtwiz_userclk_rx_active_out + ,input wire [0:0] gtwiz_reset_clk_freerun_in + ,input wire [0:0] gtwiz_reset_all_in + ,input wire [0:0] gtwiz_reset_tx_pll_and_datapath_in + ,input wire [0:0] gtwiz_reset_tx_datapath_in + ,input wire [0:0] gtwiz_reset_rx_pll_and_datapath_in + ,input wire [0:0] gtwiz_reset_rx_datapath_in + ,output wire [0:0] gtwiz_reset_rx_cdr_stable_out + ,output wire [0:0] gtwiz_reset_tx_done_out + ,output wire [0:0] gtwiz_reset_rx_done_out + ,input wire [63:0] gtwiz_userdata_tx_in + ,output wire [63:0] gtwiz_userdata_rx_out + ,input wire [0:0] gtrefclk00_in + ,output wire [0:0] qpll0outclk_out + ,output wire [0:0] qpll0outrefclk_out + ,input wire [3:0] rx8b10ben_in + ,input wire [3:0] rxbufreset_in + ,input wire [3:0] rxcommadeten_in + ,input wire [3:0] rxmcommaalignen_in + ,input wire [3:0] rxpcommaalignen_in + ,input wire [3:0] tx8b10ben_in + ,input wire [63:0] txctrl0_in + ,input wire [63:0] txctrl1_in + ,input wire [31:0] txctrl2_in + ,output wire [3:0] gtpowergood_out + ,output wire [11:0] rxbufstatus_out + ,output wire [3:0] rxbyteisaligned_out + ,output wire [3:0] rxbyterealign_out + ,output wire [7:0] rxclkcorcnt_out + ,output wire [3:0] rxcommadet_out + ,output wire [63:0] rxctrl0_out + ,output wire [63:0] rxctrl1_out + ,output wire [31:0] rxctrl2_out + ,output wire [31:0] rxctrl3_out + ,output wire [3:0] rxpmaresetdone_out + ,output wire [3:0] txpmaresetdone_out +); + + + // =================================================================================================================== + // PARAMETERS AND FUNCTIONS + // =================================================================================================================== + + // Declare and initialize local parameters and functions used for HDL generation + localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000; + `include "gth_xcku_wrapper_functions.v" + localparam integer P_TX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); + localparam integer P_RX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); + + + // =================================================================================================================== + // HELPER BLOCKS + // =================================================================================================================== + + // Any helper blocks which the user chose to exclude from the core will appear below. In addition, some signal + // assignments related to optionally-enabled ports may appear below. + + // ------------------------------------------------------------------------------------------------------------------- + // Transmitter user clocking network helper block + // ------------------------------------------------------------------------------------------------------------------- + + wire [3:0] txusrclk_int; + wire [3:0] txusrclk2_int; + wire [3:0] txoutclk_int; + + // Generate a single module instance which is driven by a clock source associated with the master transmitter channel, + // and which drives TXUSRCLK and TXUSRCLK2 for all channels + + // The source clock is TXOUTCLK from the master transmitter channel + assign gtwiz_userclk_tx_srcclk_out = txoutclk_int[P_TX_MASTER_CH_PACKED_IDX]; + + // Instantiate a single instance of the transmitter user clocking network helper block + gtwizard_ultrascale_v1_7_8_gtwiz_userclk_tx gtwiz_userclk_tx_inst ( + .gtwiz_userclk_tx_srcclk_in (gtwiz_userclk_tx_srcclk_out), + .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in), + .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out), + .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out), + .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out) + ); + + // Drive TXUSRCLK and TXUSRCLK2 for all channels with the respective helper block outputs + assign txusrclk_int = {4{gtwiz_userclk_tx_usrclk_out}}; + assign txusrclk2_int = {4{gtwiz_userclk_tx_usrclk2_out}}; + + // ------------------------------------------------------------------------------------------------------------------- + // Receiver user clocking network helper block + // ------------------------------------------------------------------------------------------------------------------- + + wire [3:0] rxusrclk_int; + wire [3:0] rxusrclk2_int; + wire [3:0] rxoutclk_int; + + // Generate a single module instance which is driven by a clock source associated with the master receiver channel, + // and which drives RXUSRCLK and RXUSRCLK2 for all channels + + // The source clock is RXOUTCLK from the master receiver channel + assign gtwiz_userclk_rx_srcclk_out = rxoutclk_int[P_RX_MASTER_CH_PACKED_IDX]; + + // Instantiate a single instance of the receiver user clocking network helper block + gtwizard_ultrascale_v1_7_8_gtwiz_userclk_rx gtwiz_userclk_rx_inst ( + .gtwiz_userclk_rx_srcclk_in (gtwiz_userclk_rx_srcclk_out), + .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in), + .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out), + .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out), + .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out) + ); + + // Drive RXUSRCLK and RXUSRCLK2 for all channels with the respective helper block outputs + assign rxusrclk_int = {4{gtwiz_userclk_rx_usrclk_out}}; + assign rxusrclk2_int = {4{gtwiz_userclk_rx_usrclk2_out}}; + wire [3:0] gtpowergood_int; + + // Required assignment to expose the GTPOWERGOOD port per user request + assign gtpowergood_out = gtpowergood_int; + + // ---------------------------------------------------------------------------------------------------------------- + // Assignments to expose data ports, or data control ports, per configuration requirement or user request + // ---------------------------------------------------------------------------------------------------------------- + + wire [63:0] txctrl0_int; + + // Required assignment to expose the TXCTRL0 port per configuration requirement or user request + assign txctrl0_int = txctrl0_in; + wire [63:0] txctrl1_int; + + // Required assignment to expose the TXCTRL1 port per configuration requirement or user request + assign txctrl1_int = txctrl1_in; + wire [63:0] rxctrl0_int; + + // Required assignment to expose the RXCTRL0 port per configuration requirement or user request + assign rxctrl0_out = rxctrl0_int; + wire [63:0] rxctrl1_int; + + // Required assignment to expose the RXCTRL1 port per configuration requirement or user request + assign rxctrl1_out = rxctrl1_int; + + + // =================================================================================================================== + // CORE INSTANCE + // =================================================================================================================== + + // Instantiate the core, mapping its enabled ports to example design ports and helper blocks as appropriate + gth_xcku_quad_x0y2 gth_xcku_quad_x0y2_inst ( + .gthrxn_in (gthrxn_in) + ,.gthrxp_in (gthrxp_in) + ,.gthtxn_out (gthtxn_out) + ,.gthtxp_out (gthtxp_out) + ,.gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_out) + ,.gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_out) + ,.gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in) + ,.gtwiz_reset_all_in (gtwiz_reset_all_in) + ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in) + ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in) + ,.gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in) + ,.gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in) + ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out) + ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out) + ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out) + ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_in) + ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_out) + ,.gtrefclk00_in (gtrefclk00_in) + ,.qpll0outclk_out (qpll0outclk_out) + ,.qpll0outrefclk_out (qpll0outrefclk_out) + ,.rx8b10ben_in (rx8b10ben_in) + ,.rxbufreset_in (rxbufreset_in) + ,.rxcommadeten_in (rxcommadeten_in) + ,.rxmcommaalignen_in (rxmcommaalignen_in) + ,.rxpcommaalignen_in (rxpcommaalignen_in) + ,.rxusrclk_in (rxusrclk_int) + ,.rxusrclk2_in (rxusrclk2_int) + ,.tx8b10ben_in (tx8b10ben_in) + ,.txctrl0_in (txctrl0_int) + ,.txctrl1_in (txctrl1_int) + ,.txctrl2_in (txctrl2_in) + ,.txusrclk_in (txusrclk_int) + ,.txusrclk2_in (txusrclk2_int) + ,.gtpowergood_out (gtpowergood_int) + ,.rxbufstatus_out (rxbufstatus_out) + ,.rxbyteisaligned_out (rxbyteisaligned_out) + ,.rxbyterealign_out (rxbyterealign_out) + ,.rxclkcorcnt_out (rxclkcorcnt_out) + ,.rxcommadet_out (rxcommadet_out) + ,.rxctrl0_out (rxctrl0_int) + ,.rxctrl1_out (rxctrl1_int) + ,.rxctrl2_out (rxctrl2_out) + ,.rxctrl3_out (rxctrl3_out) + ,.rxoutclk_out (rxoutclk_int) + ,.rxpmaresetdone_out (rxpmaresetdone_out) + ,.txoutclk_out (txoutclk_int) + ,.txpmaresetdone_out (txpmaresetdone_out) +); + +endmodule diff --git a/media_interfaces/xcku/cri_gth_0_2_0_8/cri_gth_0_2_0_8.xci b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xci similarity index 99% rename from media_interfaces/xcku/cri_gth_0_2_0_8/cri_gth_0_2_0_8.xci rename to media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xci index 5c44f6b..6cfdeda 100644 --- a/media_interfaces/xcku/cri_gth_0_2_0_8/cri_gth_0_2_0_8.xci +++ b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xci @@ -6,7 +6,7 @@ 1.0 - cri_gth_0_2_0_8 + gth_xcku_x0y8 "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000" @@ -102,7 +102,7 @@ 100.0000000 0 X0Y8 - cri_gth_0_2_0_8 + gth_xcku_x0y8 0 0 @@ -654,7 +654,7 @@ 12 0 None - 10 + 9 100.0000000 1 1 @@ -769,7 +769,7 @@ 0011111111 true 0101111100 - K28.5 + NONE true 1010000011 true @@ -1373,18 +1373,15 @@ . 2020.1 - GLOBAL + OUT_OF_CONTEXT - - - @@ -1393,29 +1390,22 @@ - - - - - - - diff --git a/media_interfaces/xcku/cri_gth_0_2_0_8/cri_gth_0_2_0_8.xml b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xml similarity index 99% rename from media_interfaces/xcku/cri_gth_0_2_0_8/cri_gth_0_2_0_8.xml rename to media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xml index 41b4cc7..9bc32ad 100644 --- a/media_interfaces/xcku/cri_gth_0_2_0_8/cri_gth_0_2_0_8.xml +++ b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8.xml @@ -2,7 +2,7 @@ xilinx.com customized_ip - cri_gth_0_2_0_8 + gth_xcku_x0y8 1.0 @@ -14,7 +14,7 @@ outputProductCRC - 9:5c0af63c + 9:dfbfd79b @@ -15572,7 +15572,7 @@ RX_COMMA_PRESET Comma value preset - K28.5 + NONE RX_COMMA_VALID_ONLY @@ -16682,7 +16682,7 @@ INTERNAL_RX_COMMA_PRESET_UPDATE - 10 + 9 @@ -22704,7 +22704,7 @@ Component_Name - cri_gth_0_2_0_8 + gth_xcku_x0y8 @@ -22713,12 +22713,9 @@ 8 - - - @@ -22727,29 +22724,22 @@ - - - - - - - diff --git a/media_interfaces/xcku/gth_8b10b.vhd b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_top.vhd similarity index 92% rename from media_interfaces/xcku/gth_8b10b.vhd rename to media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_top.vhd index cbdb4a8..d091ac7 100644 --- a/media_interfaces/xcku/gth_8b10b.vhd +++ b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_top.vhd @@ -4,7 +4,7 @@ use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; -entity gth_8b10b is +entity gth_xcku_x0y8_top is port ( clk_100 : in std_logic; clk_200 : in std_logic; @@ -40,10 +40,10 @@ entity gth_8b10b is TX_USRCLK : out std_logic ); -end entity gth_8b10b; +end entity gth_xcku_x0y8_top; -architecture behavioral of gth_8b10b is - component cri_gth_0_2_0_8_example_wrapper +architecture behavioral of gth_xcku_x0y8_top is + component gth_xcku_x0y8_wrapper port ( gthrxn_in : in std_logic; gthrxp_in : in std_logic; @@ -97,22 +97,23 @@ architecture behavioral of gth_8b10b is ); end component; - component cri_gth_init is - generic ( - P_FREERUN_FREQUENCY : integer := 100; - P_TX_TIMER_DURATION_US : integer := 30000; - P_RX_TIMER_DURATION_US : integer := 130000 - ); - port ( - clk_freerun_in : in std_logic; - reset_all_in : in std_logic; - tx_init_done_in : in std_logic; - rx_init_done_in : in std_logic; - reset_all_out : out std_logic := '0'; - reset_rx_out : out std_logic := '0'; - init_done_out : out std_logic := '0'; - retry_ctr_out : out std_logic_vector(3 downto 0) := x"0" - ); + component gth_xcku_init is + generic ( + P_FREERUN_FREQUENCY : integer := 100; + P_TX_TIMER_DURATION_US : integer := 30000; + P_RX_TIMER_DURATION_US : integer := 130000 + ); + port ( + clk_freerun_in : in std_logic; + reset_all_in : in std_logic; + tx_init_done_in : in std_logic; + rx_init_done_in : in std_logic; + rx_data_good_in : in std_logic; + reset_all_out : out std_logic := '0'; + reset_rx_out : out std_logic := '0'; + init_done_out : out std_logic := '0'; + retry_ctr_out : out std_logic_vector(3 downto 0) := x"0" + ); end component; signal gtpowergood_i : std_logic; @@ -252,16 +253,17 @@ begin rxpcommaalignen_i <= '1'; TX_USRCLK <= userclk_tx_usrclk2_i; - THE_INIT : cri_gth_init + THE_INIT : gth_xcku_init port map ( - clk_freerun_in => FREECLK, - reset_all_in => reset_all_init, - tx_init_done_in => reset_tx_done_i, - rx_init_done_in => reset_rx_done_i, - reset_all_out => reset_all_i, - reset_rx_out => open, - init_done_out => init_done_i, - retry_ctr_out => open + clk_freerun_in => FREECLK, + reset_all_in => reset_all_init, + tx_init_done_in => reset_tx_done_i, + rx_init_done_in => reset_rx_done_i, + rx_data_good_in => '1', + reset_all_out => reset_all_i, + reset_rx_out => open, + init_done_out => init_done_i, + retry_ctr_out => open ); enable_i <= '1'; @@ -313,8 +315,12 @@ begin tx_fifo_wren_i <= userclk_tx_active_i and reset_tx_done_i; - THE_GTH : cri_gth_0_2_0_8_example_wrapper + THE_GTH : gth_xcku_x0y8_wrapper port map( + gthrxn_in => gthrxn_i, + gthrxp_in => gthrxp_i, + gthtxn_out => gthtxn_i, + gthtxp_out => gthtxp_i, gtwiz_userclk_tx_reset_in => userclk_tx_reset_i, gtwiz_userclk_tx_srcclk_out => userclk_tx_srcclk_i, gtwiz_userclk_tx_usrclk_out => userclk_tx_usrclk_i, @@ -339,8 +345,6 @@ begin gtrefclk00_in => mgtrefclk0_x0y3_int, qpll0outclk_out => qpll0outclk_i, qpll0outrefclk_out => qpll0outrefclk_i, - gthrxn_in => gthrxn_i, - gthrxp_in => gthrxp_i, rx8b10ben_in => '1', rxbufreset_in => '0', rxcommadeten_in => rxcommadeten_i, @@ -350,8 +354,6 @@ begin txctrl0_in => txctrl0_i, txctrl1_in => txctrl1_i, txctrl2_in => txctrl2_i, - gthtxn_out => gthtxn_i, - gthtxp_out => gthtxp_i, gtpowergood_out => gtpowergood_i, rxbufstatus_out => rxbufstatus_i, rxbyteisaligned_out => rxbyteisaligned_i, diff --git a/media_interfaces/xcku/cri_gth_0_2_0_8_example_wrapper.v b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_wrapper.v similarity index 97% rename from media_interfaces/xcku/cri_gth_0_2_0_8_example_wrapper.v rename to media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_wrapper.v index 8a48032..627857c 100644 --- a/media_interfaces/xcku/cri_gth_0_2_0_8_example_wrapper.v +++ b/media_interfaces/xcku/gth_xcku_x0y8/gth_xcku_x0y8_wrapper.v @@ -54,7 +54,7 @@ // the core, connects them as appropriate, and maps enabled ports // ===================================================================================================================== -module cri_gth_0_2_0_8_example_wrapper ( +module gth_xcku_x0y8_wrapper ( input wire [0:0] gthrxn_in ,input wire [0:0] gthrxp_in ,output wire [0:0] gthtxn_out @@ -112,8 +112,8 @@ module cri_gth_0_2_0_8_example_wrapper ( // =================================================================================================================== // Declare and initialize local parameters and functions used for HDL generation - // localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000; - `include "cri_gth_q0_2_0_8_example_wrapper_functions.v" + localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000; + `include "gth_xcku_wrapper_functions.v" localparam integer P_TX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); localparam integer P_RX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); @@ -140,7 +140,7 @@ module cri_gth_0_2_0_8_example_wrapper ( assign gtwiz_userclk_tx_srcclk_out = txoutclk_int[P_TX_MASTER_CH_PACKED_IDX]; // Instantiate a single instance of the transmitter user clocking network helper block - cri_gth_0_2_0_8_example_gtwiz_userclk_tx gtwiz_userclk_tx_inst ( + gtwizard_ultrascale_v1_7_8_gtwiz_userclk_tx gtwiz_userclk_tx_inst ( .gtwiz_userclk_tx_srcclk_in (gtwiz_userclk_tx_srcclk_out), .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in), .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out), @@ -167,7 +167,7 @@ module cri_gth_0_2_0_8_example_wrapper ( assign gtwiz_userclk_rx_srcclk_out = rxoutclk_int[P_RX_MASTER_CH_PACKED_IDX]; // Instantiate a single instance of the receiver user clocking network helper block - cri_gth_0_2_0_8_example_gtwiz_userclk_rx gtwiz_userclk_rx_inst ( + gtwizard_ultrascale_v1_7_8_gtwiz_userclk_rx gtwiz_userclk_rx_inst ( .gtwiz_userclk_rx_srcclk_in (gtwiz_userclk_rx_srcclk_out), .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in), .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out), @@ -210,7 +210,7 @@ module cri_gth_0_2_0_8_example_wrapper ( // =================================================================================================================== // Instantiate the core, mapping its enabled ports to example design ports and helper blocks as appropriate - cri_gth_0_2_0_8 cri_gth_0_2_0_8_inst ( + gth_xcku_x0y8 gth_xcku_x0y8_inst ( .gthrxn_in (gthrxn_in) ,.gthrxp_in (gthrxp_in) ,.gthtxn_out (gthtxn_out) diff --git a/media_interfaces/xcku/gtwizard_options.txt b/media_interfaces/xcku/gtwizard_options.txt new file mode 100644 index 0000000..fba870f --- /dev/null +++ b/media_interfaces/xcku/gtwizard_options.txt @@ -0,0 +1,35 @@ +Tab "Basic": + Columns "Transmitter" and "Receiver": + Line rate (Gb/s): 2 + Actual Reference Clock (MHz): 125 + Decoding: 8B/10B + User data width: 16 + +Tab "Physical Resources": + Channel table: + Quad X0Y2 in SLR 0: + GTHE3_CHANNEL_X0Y8: + (X), MGTREFCLK0 + (for quad version also GTHE3_CHANNEL_X0Y9 -- GTHE3_CHANNEL_X0Y11) + +Tab "Optional Features": + Receiver comma detection and alignment: + Plus comma: + (X), 1010000011 + Minus comma: + (X), 0101111100 + Mask: + 0011111111 + Receiver clock correction: + Enable and select number of sequences to use: + 2 + Length of each sequence: + 2 + Sequence 0, pattern 0: + 01010000 + Sequence 0, pattern 1: + 10111100, K character + Sequence 1, pattern 0: + 01010000, Inverted disparity + Sequence 1, pattern 1: + 10111100, K character, Inverted disparity diff --git a/xilinx/xcku/fifo_19x16.vhd b/xilinx/xcku/fifo_19x16.vhd new file mode 100644 index 0000000..030c808 --- /dev/null +++ b/xilinx/xcku/fifo_19x16.vhd @@ -0,0 +1,55 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_19x16 is + port ( + Data : in std_logic_vector(18 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(18 downto 0); + WCNT : out std_logic_vector(4 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); +end entity fifo_19x16; + +architecture structural of fifo_19x16 is + component fifo_19x16_xcku + port ( + clk : in std_logic; + srst : in std_logic; + din : in std_logic_vector(18 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(18 downto 0); + full : out std_logic; + empty : out std_logic; + data_count : out std_logic_vector(3 downto 0); + prog_full : out std_logic; + wr_rst_busy : out std_logic; + rd_rst_busy : out std_logic + ); + end component; +begin + fifo : fifo_19x16_xcku + port map ( + clk => Clock, + srst => Reset, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + dout => Q, + full => Full, + empty => Empty, + data_count => WCNT(3 downto 0), + prog_full => AlmostFull, + wr_rst_busy => open, + rd_rst_busy => open + ); + + -- TODO: Check impact of different count values + WCNT(4) <= '0'; +end architecture structural; diff --git a/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci b/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci new file mode 100644 index 0000000..589c5db --- /dev/null +++ b/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci @@ -0,0 +1,569 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_19x16_xcku + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 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C_HAS_RD_DATA_COUNT + 0 + + + C_HAS_RD_RST + 0 + + + C_HAS_RST + 0 + + + C_HAS_SRST + 1 + + + C_HAS_UNDERFLOW + 0 + + + C_HAS_VALID + 0 + + + C_HAS_WR_ACK + 0 + + + C_HAS_WR_DATA_COUNT + 0 + + + C_HAS_WR_RST + 0 + + + C_IMPLEMENTATION_TYPE + 0 + + + C_INIT_WR_PNTR_VAL + 0 + + + C_MEMORY_TYPE + 1 + + + C_MIF_FILE_NAME + BlankString + + + C_OPTIMIZATION_MODE + 0 + + + C_OVERFLOW_LOW + 0 + + + C_PRELOAD_LATENCY + 1 + + + C_PRELOAD_REGS + 0 + + + C_PRIM_FIFO_TYPE + 512x36 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL + 2 + + + C_PROG_EMPTY_THRESH_NEGATE_VAL + 3 + + + C_PROG_EMPTY_TYPE + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL + 8 + + + C_PROG_FULL_THRESH_NEGATE_VAL + 7 + + + C_PROG_FULL_TYPE + 1 + + + C_RD_DATA_COUNT_WIDTH + 4 + + + C_RD_DEPTH + 16 + + + C_RD_FREQ + 1 + + + C_RD_PNTR_WIDTH + 4 + + + C_UNDERFLOW_LOW + 0 + + + C_USE_DOUT_RST + 1 + + + C_USE_ECC + 0 + + + C_USE_EMBEDDED_REG + 0 + + + C_USE_PIPELINE_REG + 0 + + + C_POWER_SAVING_MODE + 0 + + + C_USE_FIFO16_FLAGS + 0 + + + C_USE_FWFT_DATA_COUNT + 0 + + + C_VALID_LOW + 0 + + + C_WR_ACK_LOW + 0 + + + C_WR_DATA_COUNT_WIDTH + 4 + + + C_WR_DEPTH + 16 + + + C_WR_FREQ + 1 + + + C_WR_PNTR_WIDTH + 4 + + + C_WR_RESPONSE_LATENCY + 1 + + + C_MSGON_VAL + 1 + + + C_ENABLE_RST_SYNC + 1 + + + C_EN_SAFETY_CKT + 0 + + + C_ERROR_INJECTION_TYPE + 0 + + + C_SYNCHRONIZER_STAGE + 2 + + + C_INTERFACE_TYPE + 0 + + + C_AXI_TYPE + 1 + + + C_HAS_AXI_WR_CHANNEL + 1 + + + C_HAS_AXI_RD_CHANNEL + 1 + + + C_HAS_SLAVE_CE + 0 + + + C_HAS_MASTER_CE + 0 + + + C_ADD_NGC_CONSTRAINT + 0 + + + C_USE_COMMON_OVERFLOW + 0 + + + C_USE_COMMON_UNDERFLOW + 0 + + + C_USE_DEFAULT_SETTINGS + 0 + + + C_AXI_ID_WIDTH + 1 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 64 + + + C_AXI_LEN_WIDTH + 8 + + + C_AXI_LOCK_WIDTH + 1 + + + C_HAS_AXI_ID + 0 + + + C_HAS_AXI_AWUSER + 0 + + + C_HAS_AXI_WUSER + 0 + + + C_HAS_AXI_BUSER + 0 + + + C_HAS_AXI_ARUSER + 0 + + + C_HAS_AXI_RUSER + 0 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_HAS_AXIS_TDATA + 1 + + + C_HAS_AXIS_TID + 0 + + + C_HAS_AXIS_TDEST + 0 + + + C_HAS_AXIS_TUSER + 1 + + + C_HAS_AXIS_TREADY + 1 + + + C_HAS_AXIS_TLAST + 0 + + + C_HAS_AXIS_TSTRB + 0 + + + C_HAS_AXIS_TKEEP + 0 + + + C_AXIS_TDATA_WIDTH + 8 + + + C_AXIS_TID_WIDTH + 1 + + + C_AXIS_TDEST_WIDTH + 1 + + + C_AXIS_TUSER_WIDTH + 4 + + + C_AXIS_TSTRB_WIDTH + 1 + + + C_AXIS_TKEEP_WIDTH + 1 + + + C_WACH_TYPE + 0 + + + C_WDCH_TYPE + 0 + + + C_WRCH_TYPE + 0 + + + C_RACH_TYPE + 0 + + + C_RDCH_TYPE + 0 + + + C_AXIS_TYPE + 0 + + + C_IMPLEMENTATION_TYPE_WACH + 1 + + + C_IMPLEMENTATION_TYPE_WDCH + 1 + + + C_IMPLEMENTATION_TYPE_WRCH + 1 + + + C_IMPLEMENTATION_TYPE_RACH + 1 + + + C_IMPLEMENTATION_TYPE_RDCH + 1 + + + C_IMPLEMENTATION_TYPE_AXIS + 1 + + + C_APPLICATION_TYPE_WACH + 0 + + + C_APPLICATION_TYPE_WDCH + 0 + + + C_APPLICATION_TYPE_WRCH + 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_08ae7940 + 19 + 19 + + + choice_list_165ed04b + 64 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_0721dec1 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Multiple_Programmable_Empty_Threshold_Constants + Single_Programmable_Empty_Threshold_Input_Port + Multiple_Programmable_Empty_Threshold_Input_Ports + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_541ed8d9 + Embedded_Reg + Fabric_Reg + Both + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_88535724 + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Multiple_Programmable_Full_Threshold_Constants + Single_Programmable_Full_Threshold_Input_Port + Multiple_Programmable_Full_Threshold_Input_Ports + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_ae1178b5 + Asynchronous_Reset + Synchronous_Reset + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + fifo_19x16_xcku + + + + true + + + + + + Fifo_Implementation + Common_Clock_Block_RAM + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + false + + + + true + + + + + + Input_Data_Width + 19 + + + + true + + + + + + Input_Depth + 16 + + + + true + + + + + + Output_Data_Width + 19 + + + + false + + + + + + Output_Depth + 16 + + + + false + + + + + + Enable_ECC + false + + + + true + + + + + + Use_Embedded_Registers + false + + + + true + + + + + + Reset_Pin + true + + + + true + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + true + + + + + + Full_Flags_Reset_Value + 0 + + + + false + + + + + + Use_Dout_Reset + true + + + + true + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + false + + + + + + Almost_Full_Flag + false + + + + true + + + + + + Almost_Empty_Flag + false + + + + true + + + + + + Valid_Flag + false + + + + true + + + + + + Valid_Sense + Active_High + + + + false + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + true + + + + true + + + + + + Data_Count_Width + 4 + + + + true + + + + + + Write_Data_Count + false + + + + false + + + + + + Write_Data_Count_Width + 4 + + + + false + + + + + + Read_Data_Count + false + + + + false + + + + + + Read_Data_Count_Width + 4 + + + + false + + + + + + Disable_Timing_Violations + false + + + + false + + + + + + Read_Clock_Frequency + 1 + + + + false + + + + + + Write_Clock_Frequency + 1 + + + + false + + + + + + Programmable_Full_Type + Single_Programmable_Full_Threshold_Constant + + + + true + + + + + + Full_Threshold_Assert_Value + 8 + + + + true + + + + + + Full_Threshold_Negate_Value + 7 + + + + false + + + + + + Programmable_Empty_Type + No_Programmable_Empty_Threshold + + + + true + + + + + + Empty_Threshold_Assert_Value + 2 + + + + false + + + + + + Empty_Threshold_Negate_Value + 3 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + + false 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FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + 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