From: Cahit <c.ugur@gsi.de>
Date: Fri, 3 May 2013 13:29:31 +0000 (+0200)
Subject: pll in 125MHz out 20MHz - cu
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=14e470808cba5dea37088cb5da0a69ad944163d9;p=trb3.git

pll in 125MHz out 20MHz - cu
---

diff --git a/base/cores/pll_in125_out20.vhd b/base/cores/pll_in125_out20.vhd
new file mode 100644
index 0000000..f02a40d
--- /dev/null
+++ b/base/cores/pll_in125_out20.vhd
@@ -0,0 +1,100 @@
+-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- Module  Version: 5.3
+--/opt/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n pll_in125_out20 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -bypassk -fclkop 20 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 125 -fclkok_tol 0.0 -norst -noclkok2 -bw -e 
+
+-- Mon Apr 22 16:54:04 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in125_out20 is
+  port (
+    CLK   : in  std_logic;
+    CLKOP : out std_logic;
+    CLKOK : out std_logic;
+    LOCK  : out std_logic);
+  attribute dont_touch                    : boolean;
+  attribute dont_touch of pll_in125_out20 : entity is true;
+end pll_in125_out20;
+
+architecture Structure of pll_in125_out20 is
+
+  -- internal signal declarations
+  signal CLKOP_t   : std_logic;
+  signal scuba_vlo : std_logic;
+
+  -- local component declarations
+  component EHXPLLF
+    generic (FEEDBK_PATH : in string; CLKOK_INPUT : in string;
+    DELAY_PWD            : in string; DELAY_VAL : in integer;
+    CLKOS_TRIM_DELAY     : in integer;
+    CLKOS_TRIM_POL       : in string;
+    CLKOP_TRIM_DELAY     : in integer;
+    CLKOP_TRIM_POL       : in string; CLKOK_BYPASS : in string;
+    CLKOS_BYPASS         : in string; CLKOP_BYPASS : in string;
+    PHASE_DELAY_CNTL     : in string; DUTY : in integer;
+    PHASEADJ             : in string; CLKOK_DIV : in integer;
+    CLKOP_DIV            : in integer; CLKFB_DIV : in integer;
+    CLKI_DIV             : in integer; FIN : in string);
+    port (CLKI : in  std_logic; CLKFB : in std_logic; RST : in std_logic;
+    RSTK       : in  std_logic; WRDEL : in std_logic; DRPAI3 : in std_logic;
+    DRPAI2     : in  std_logic; DRPAI1 : in std_logic; DRPAI0 : in std_logic;
+    DFPAI3     : in  std_logic; DFPAI2 : in std_logic; DFPAI1 : in std_logic;
+    DFPAI0     : in  std_logic; FDA3 : in std_logic; FDA2 : in std_logic;
+    FDA1       : in  std_logic; FDA0 : in std_logic; CLKOP : out std_logic;
+    CLKOS      : out std_logic; CLKOK : out std_logic; CLKOK2 : out std_logic;
+    LOCK       : out std_logic; CLKINTFB : out std_logic);
+  end component;
+  component VLO
+    port (Z : out std_logic);
+  end component;
+  attribute FREQUENCY_PIN_CLKOP              : string;
+  attribute FREQUENCY_PIN_CLKI               : string;
+  attribute FREQUENCY_PIN_CLKOK              : string;
+  attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "20.000000";
+  attribute FREQUENCY_PIN_CLKI of PLLInst_0  : label is "125.000000";
+  attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "125.000000";
+  attribute syn_keep                         : boolean;
+  attribute syn_noprune                      : boolean;
+  attribute syn_noprune of Structure         : architecture is true;
+
+begin
+  -- component instantiation statements
+  scuba_vlo_inst : VLO
+    port map (Z => scuba_vlo);
+
+  PLLInst_0 : EHXPLLF
+    generic map (FEEDBK_PATH      => "CLKOP", CLKOK_BYPASS => "ENABLED",
+                 CLKOS_BYPASS     => "DISABLED", CLKOP_BYPASS => "DISABLED",
+                 CLKOK_INPUT      => "CLKOP", DELAY_PWD => "DISABLED", DELAY_VAL => 0,
+                 CLKOS_TRIM_DELAY => 0, CLKOS_TRIM_POL => "RISING",
+                 CLKOP_TRIM_DELAY => 0, CLKOP_TRIM_POL => "RISING",
+                 PHASE_DELAY_CNTL => "STATIC", DUTY => 8, PHASEADJ => "0.0",
+                 CLKOK_DIV        => 2, CLKOP_DIV => 48, CLKFB_DIV => 4, CLKI_DIV => 25,
+                 FIN              => "125.000000")
+    port map (CLKI     => CLK, CLKFB => CLKOP_t, RST => scuba_vlo,
+              RSTK     => scuba_vlo, WRDEL => scuba_vlo, DRPAI3 => scuba_vlo,
+              DRPAI2   => scuba_vlo, DRPAI1 => scuba_vlo, DRPAI0 => scuba_vlo,
+              DFPAI3   => scuba_vlo, DFPAI2 => scuba_vlo, DFPAI1 => scuba_vlo,
+              DFPAI0   => scuba_vlo, FDA3 => scuba_vlo, FDA2 => scuba_vlo,
+              FDA1     => scuba_vlo, FDA0 => scuba_vlo, CLKOP => CLKOP_t,
+              CLKOS    => open, CLKOK => CLKOK, CLKOK2 => open, LOCK => LOCK,
+              CLKINTFB => open);
+
+  CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in125_out20 is
+  for Structure
+    for all : EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+    for all : VLO use entity ecp3.VLO(V); end for;
+  end for;
+end Structure_CON;
+
+-- synopsys translate_on