From: Ludwig Maier Date: Wed, 1 Oct 2014 18:49:59 +0000 (+0200) Subject: nxyter ADC debugging X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=154b9f3574c29af1c84a2bac54beab859d0ccd02;p=trb3.git nxyter ADC debugging --- diff --git a/nxyter/compile_frankfurt.pl b/nxyter/compile_frankfurt.pl deleted file mode 100755 index 63e4b75..0000000 --- a/nxyter/compile_frankfurt.pl +++ /dev/null @@ -1,156 +0,0 @@ -#!/usr/bin/perl -use Data::Dumper; -use warnings; -use strict; - - - - -################################################################################### -#Settings for this project -my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64'; -my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; -my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; -my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; -################################################################################### - - - - - - - - -use FileHandle; - -$ENV{'SYNPLIFY'}=$synplify_path; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - - - - -my $FAMILYNAME="LatticeECP3"; -my $DEVICENAME="LFE3-150EA"; -my $PACKAGE="FPBGA672"; -my $SPEEDGRADE="8"; - - -#create full lpf file -system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); - -#set -e -#set -o errexit - -#generate timestamp -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -system("env| grep LM_"); -my $r = ""; - -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - - - -foreach (@a) -{ - if(/\@E:/) - { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); - print "\n\n"; - exit 129; - } -} - - -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - - -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -execute($c); - -my $tpmap = $TOPNAME . "_map" ; - -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; -execute($c); - -system("rm $TOPNAME.ncd"); - - -#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; -$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# IOR IO Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; -# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -chdir ".."; - -exit; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/nxyter/compile_munich32.pl b/nxyter/compile_munich32.pl index 2ad7c9e..f5cefd9 100755 --- a/nxyter/compile_munich32.pl +++ b/nxyter/compile_munich32.pl @@ -10,7 +10,7 @@ use strict; #Settings for this project my $TOPNAME = "trb3_periph"; #Name of top-level entity my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/3.2'; -my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; +my $synplify_path = '/usr/local/opt/synplify/I-2013.09-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; ################################################################################### diff --git a/nxyter/cores/dynamic_shift_register8x64.ipx b/nxyter/cores/dynamic_shift_register8x64.ipx deleted file mode 100644 index abd7cc9..0000000 --- a/nxyter/cores/dynamic_shift_register8x64.ipx +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/nxyter/cores/dynamic_shift_register8x64.lpc b/nxyter/cores/dynamic_shift_register8x64.lpc deleted file mode 100644 index dc5aeb9..0000000 --- a/nxyter/cores/dynamic_shift_register8x64.lpc +++ /dev/null @@ -1,41 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN672C -SpeedGrade=8 -Package=FPBGA672 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=RAM_Based_Shift_Register -CoreRevision=4.1 -ModuleName=dynamic_shift_register8x64 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=04/18/2014 -Time=13:07:29 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -DataWidth=8 -Type=VarLossless -NoOfShifts=16 -MaxLossyShifts=16 -MaxLosslessShifts=64 -EOR=1 -MemFile= -MemFormat=orca -RamType=dram - -[FilesGenerated] -=mem diff --git a/nxyter/cores/dynamic_shift_register8x64.vhd b/nxyter/cores/dynamic_shift_register8x64.vhd deleted file mode 100644 index 3b85a64..0000000 --- a/nxyter/cores/dynamic_shift_register8x64.vhd +++ /dev/null @@ -1,454 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) --- Module Version: 4.1 ---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n dynamic_shift_register8x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type shiftreg -width 8 -depth 64 -mode 2 -pipe_final_output -e - --- Fri Apr 18 13:07:29 2014 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity dynamic_shift_register8x64 is - port ( - Din: in std_logic_vector(7 downto 0); - Addr: in std_logic_vector(5 downto 0); - Clock: in std_logic; - ClockEn: in std_logic; - Reset: in std_logic; - Q: out std_logic_vector(7 downto 0)); -end dynamic_shift_register8x64; - -architecture Structure of dynamic_shift_register8x64 is - - -- internal signal declarations - signal shreg_addr_w5_inv: std_logic; - signal shreg_addr_w4_inv: std_logic; - signal Reset_inv: std_logic; - signal scuba_vhi: std_logic; - signal ishreg_addr_w0: std_logic; - signal ishreg_addr_w1: std_logic; - signal sreg_0_ctr_1_ci: std_logic; - signal ishreg_addr_w2: std_logic; - signal ishreg_addr_w3: std_logic; - signal co0: std_logic; - signal ishreg_addr_w4: std_logic; - signal ishreg_addr_w5: std_logic; - signal co2: std_logic; - signal co1: std_logic; - signal low_inv: std_logic; - signal co0_1: std_logic; - signal co1_1: std_logic; - signal shreg_addr_w4: std_logic; - signal co2_1: std_logic; - signal shreg_addr_w5: std_logic; - signal scuba_vlo: std_logic; - signal Q7_ffin: std_logic; - signal Q6_ffin: std_logic; - signal Q5_ffin: std_logic; - signal Q4_ffin: std_logic; - signal Q3_ffin: std_logic; - signal Q2_ffin: std_logic; - signal Q1_ffin: std_logic; - signal Q0_ffin: std_logic; - signal shreg_addr_r5: std_logic; - signal shreg_addr_r4: std_logic; - signal mdL0_0_7: std_logic; - signal mdL0_0_6: std_logic; - signal mdL0_0_5: std_logic; - signal mdL0_0_4: std_logic; - signal mdL0_0_3: std_logic; - signal mdL0_0_2: std_logic; - signal mdL0_0_1: std_logic; - signal mdL0_0_0: std_logic; - signal dec0_wre3: std_logic; - signal mdL0_1_7: std_logic; - signal mdL0_1_6: std_logic; - signal mdL0_1_5: std_logic; - signal mdL0_1_4: std_logic; - signal mdL0_1_3: std_logic; - signal mdL0_1_2: std_logic; - signal mdL0_1_1: std_logic; - signal mdL0_1_0: std_logic; - signal dec1_wre7: std_logic; - signal mdL0_2_7: std_logic; - signal mdL0_2_6: std_logic; - signal mdL0_2_5: std_logic; - signal mdL0_2_4: std_logic; - signal mdL0_2_3: std_logic; - signal mdL0_2_2: std_logic; - signal mdL0_2_1: std_logic; - signal mdL0_2_0: std_logic; - signal dec2_wre11: std_logic; - signal mdL0_3_7: std_logic; - signal mdL0_3_6: std_logic; - signal mdL0_3_5: std_logic; - signal mdL0_3_4: std_logic; - signal mdL0_3_3: std_logic; - signal mdL0_3_2: std_logic; - signal mdL0_3_1: std_logic; - signal mdL0_3_0: std_logic; - signal shreg_addr_r3: std_logic; - signal shreg_addr_r2: std_logic; - signal shreg_addr_r1: std_logic; - signal shreg_addr_r0: std_logic; - signal dec3_wre15: std_logic; - signal shreg_addr_w3: std_logic; - signal shreg_addr_w2: std_logic; - signal shreg_addr_w1: std_logic; - signal shreg_addr_w0: std_logic; - - -- local component declarations - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FSUB2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; BI: in std_logic; BOUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX41 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; SD1: in std_logic; SD2: in std_logic; - Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component DPR16X4C - generic (INITVAL : in String); - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; - RAD0: in std_logic; RAD1: in std_logic; - RAD2: in std_logic; RAD3: in std_logic; - WAD0: in std_logic; WAD1: in std_logic; - WAD2: in std_logic; WAD3: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - attribute GSR : string; - attribute MEM_INIT_FILE : string; - attribute MEM_LPC_FILE : string; - attribute COMP : string; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute MEM_INIT_FILE of sram_1_0_0 : label is "(0-15)(0-3)"; - attribute MEM_LPC_FILE of sram_1_0_0 : label is "dynamic_shift_register8x64.lpc"; - attribute COMP of sram_1_0_0 : label is "sram_1_0_0"; - attribute MEM_INIT_FILE of sram_1_0_1 : label is "(0-15)(4-7)"; - attribute MEM_LPC_FILE of sram_1_0_1 : label is "dynamic_shift_register8x64.lpc"; - attribute COMP of sram_1_0_1 : label is "sram_1_0_1"; - attribute MEM_INIT_FILE of sram_1_1_0 : label is "(16-31)(0-3)"; - attribute MEM_LPC_FILE of sram_1_1_0 : label is "dynamic_shift_register8x64.lpc"; - attribute COMP of sram_1_1_0 : label is "sram_1_1_0"; - attribute MEM_INIT_FILE of sram_1_1_1 : label is "(16-31)(4-7)"; - attribute MEM_LPC_FILE of sram_1_1_1 : label is "dynamic_shift_register8x64.lpc"; - attribute COMP of sram_1_1_1 : label is "sram_1_1_1"; - attribute MEM_INIT_FILE of sram_1_2_0 : label is "(32-47)(0-3)"; - attribute MEM_LPC_FILE of sram_1_2_0 : label is "dynamic_shift_register8x64.lpc"; - attribute COMP of sram_1_2_0 : label is "sram_1_2_0"; - attribute MEM_INIT_FILE of sram_1_2_1 : label is "(32-47)(4-7)"; - attribute MEM_LPC_FILE of sram_1_2_1 : label is "dynamic_shift_register8x64.lpc"; - attribute COMP of sram_1_2_1 : label is "sram_1_2_1"; - attribute MEM_INIT_FILE of sram_1_3_0 : label is "(48-63)(0-3)"; - attribute MEM_LPC_FILE of sram_1_3_0 : label is "dynamic_shift_register8x64.lpc"; - attribute COMP of sram_1_3_0 : label is "sram_1_3_0"; - attribute MEM_INIT_FILE of sram_1_3_1 : label is "(48-63)(4-7)"; - attribute MEM_LPC_FILE of sram_1_3_1 : label is "dynamic_shift_register8x64.lpc"; - attribute COMP of sram_1_3_1 : label is "sram_1_3_1"; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - INV_3: INV - port map (A=>Reset, Z=>Reset_inv); - - INV_2: INV - port map (A=>scuba_vlo, Z=>low_inv); - - INV_1: INV - port map (A=>shreg_addr_w4, Z=>shreg_addr_w4_inv); - - INV_0: INV - port map (A=>shreg_addr_w5, Z=>shreg_addr_w5_inv); - - LUT4_3: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, - AD0=>shreg_addr_w5_inv, DO0=>dec0_wre3); - - LUT4_2: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, - AD0=>shreg_addr_w5_inv, DO0=>dec1_wre7); - - LUT4_1: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, - AD0=>shreg_addr_w5, DO0=>dec2_wre11); - - LUT4_0: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, - AD0=>shreg_addr_w5, DO0=>dec3_wre15); - - FF_13: FD1P3DX - port map (D=>ishreg_addr_w0, SP=>ClockEn, CK=>Clock, CD=>Reset, - Q=>shreg_addr_w0); - - FF_12: FD1P3DX - port map (D=>ishreg_addr_w1, SP=>ClockEn, CK=>Clock, CD=>Reset, - Q=>shreg_addr_w1); - - FF_11: FD1P3DX - port map (D=>ishreg_addr_w2, SP=>ClockEn, CK=>Clock, CD=>Reset, - Q=>shreg_addr_w2); - - FF_10: FD1P3DX - port map (D=>ishreg_addr_w3, SP=>ClockEn, CK=>Clock, CD=>Reset, - Q=>shreg_addr_w3); - - FF_9: FD1P3DX - port map (D=>ishreg_addr_w4, SP=>ClockEn, CK=>Clock, CD=>Reset, - Q=>shreg_addr_w4); - - FF_8: FD1P3DX - port map (D=>ishreg_addr_w5, SP=>ClockEn, CK=>Clock, CD=>Reset, - Q=>shreg_addr_w5); - - FF_7: FD1P3DX - port map (D=>Q7_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(7)); - - FF_6: FD1P3DX - port map (D=>Q6_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(6)); - - FF_5: FD1P3DX - port map (D=>Q5_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(5)); - - FF_4: FD1P3DX - port map (D=>Q4_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(4)); - - FF_3: FD1P3DX - port map (D=>Q3_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(3)); - - FF_2: FD1P3DX - port map (D=>Q2_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(2)); - - FF_1: FD1P3DX - port map (D=>Q1_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(1)); - - FF_0: FD1P3DX - port map (D=>Q0_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(0)); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - sreg_0_ctr_1_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>sreg_0_ctr_1_ci, - S0=>open, S1=>open); - - sreg_0_ctr_1_0: CU2 - port map (CI=>sreg_0_ctr_1_ci, PC0=>shreg_addr_w0, - PC1=>shreg_addr_w1, CO=>co0, NC0=>ishreg_addr_w0, - NC1=>ishreg_addr_w1); - - sreg_0_ctr_1_1: CU2 - port map (CI=>co0, PC0=>shreg_addr_w2, PC1=>shreg_addr_w3, - CO=>co1, NC0=>ishreg_addr_w2, NC1=>ishreg_addr_w3); - - sreg_0_ctr_1_2: CU2 - port map (CI=>co1, PC0=>shreg_addr_w4, PC1=>shreg_addr_w5, - CO=>co2, NC0=>ishreg_addr_w4, NC1=>ishreg_addr_w5); - - raddr_sub_1_0: FSUB2B - port map (A0=>scuba_vlo, A1=>shreg_addr_w0, B0=>low_inv, - B1=>Addr(0), BI=>scuba_vlo, BOUT=>co0_1, S0=>open, - S1=>shreg_addr_r0); - - raddr_sub_1_1: FSUB2B - port map (A0=>shreg_addr_w1, A1=>shreg_addr_w2, B0=>Addr(1), - B1=>Addr(2), BI=>co0_1, BOUT=>co1_1, S0=>shreg_addr_r1, - S1=>shreg_addr_r2); - - raddr_sub_1_2: FSUB2B - port map (A0=>shreg_addr_w3, A1=>shreg_addr_w4, B0=>Addr(3), - B1=>Addr(4), BI=>co1_1, BOUT=>co2_1, S0=>shreg_addr_r3, - S1=>shreg_addr_r4); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - raddr_sub_1_3: FSUB2B - port map (A0=>shreg_addr_w5, A1=>scuba_vlo, B0=>Addr(5), - B1=>scuba_vlo, BI=>co2_1, BOUT=>open, S0=>shreg_addr_r5, - S1=>open); - - mux_7: MUX41 - port map (D0=>mdL0_0_7, D1=>mdL0_1_7, D2=>mdL0_2_7, D3=>mdL0_3_7, - SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q7_ffin); - - mux_6: MUX41 - port map (D0=>mdL0_0_6, D1=>mdL0_1_6, D2=>mdL0_2_6, D3=>mdL0_3_6, - SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q6_ffin); - - mux_5: MUX41 - port map (D0=>mdL0_0_5, D1=>mdL0_1_5, D2=>mdL0_2_5, D3=>mdL0_3_5, - SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q5_ffin); - - mux_4: MUX41 - port map (D0=>mdL0_0_4, D1=>mdL0_1_4, D2=>mdL0_2_4, D3=>mdL0_3_4, - SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q4_ffin); - - mux_3: MUX41 - port map (D0=>mdL0_0_3, D1=>mdL0_1_3, D2=>mdL0_2_3, D3=>mdL0_3_3, - SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q3_ffin); - - mux_2: MUX41 - port map (D0=>mdL0_0_2, D1=>mdL0_1_2, D2=>mdL0_2_2, D3=>mdL0_3_2, - SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q2_ffin); - - mux_1: MUX41 - port map (D0=>mdL0_0_1, D1=>mdL0_1_1, D2=>mdL0_2_1, D3=>mdL0_3_1, - SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q1_ffin); - - mux_0: MUX41 - port map (D0=>mdL0_0_0, D1=>mdL0_1_0, D2=>mdL0_2_0, D3=>mdL0_3_0, - SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q0_ffin); - - sram_1_0_0: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7), - WCK=>Clock, WRE=>dec0_wre3, RAD0=>shreg_addr_r0, - RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, - RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, - WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, - WAD3=>shreg_addr_w3, DO0=>mdL0_0_4, DO1=>mdL0_0_5, - DO2=>mdL0_0_6, DO3=>mdL0_0_7); - - sram_1_0_1: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3), - WCK=>Clock, WRE=>dec0_wre3, RAD0=>shreg_addr_r0, - RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, - RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, - WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, - WAD3=>shreg_addr_w3, DO0=>mdL0_0_0, DO1=>mdL0_0_1, - DO2=>mdL0_0_2, DO3=>mdL0_0_3); - - sram_1_1_0: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7), - WCK=>Clock, WRE=>dec1_wre7, RAD0=>shreg_addr_r0, - RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, - RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, - WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, - WAD3=>shreg_addr_w3, DO0=>mdL0_1_4, DO1=>mdL0_1_5, - DO2=>mdL0_1_6, DO3=>mdL0_1_7); - - sram_1_1_1: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3), - WCK=>Clock, WRE=>dec1_wre7, RAD0=>shreg_addr_r0, - RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, - RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, - WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, - WAD3=>shreg_addr_w3, DO0=>mdL0_1_0, DO1=>mdL0_1_1, - DO2=>mdL0_1_2, DO3=>mdL0_1_3); - - sram_1_2_0: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7), - WCK=>Clock, WRE=>dec2_wre11, RAD0=>shreg_addr_r0, - RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, - RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, - WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, - WAD3=>shreg_addr_w3, DO0=>mdL0_2_4, DO1=>mdL0_2_5, - DO2=>mdL0_2_6, DO3=>mdL0_2_7); - - sram_1_2_1: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3), - WCK=>Clock, WRE=>dec2_wre11, RAD0=>shreg_addr_r0, - RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, - RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, - WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, - WAD3=>shreg_addr_w3, DO0=>mdL0_2_0, DO1=>mdL0_2_1, - DO2=>mdL0_2_2, DO3=>mdL0_2_3); - - sram_1_3_0: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7), - WCK=>Clock, WRE=>dec3_wre15, RAD0=>shreg_addr_r0, - RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, - RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, - WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, - WAD3=>shreg_addr_w3, DO0=>mdL0_3_4, DO1=>mdL0_3_5, - DO2=>mdL0_3_6, DO3=>mdL0_3_7); - - sram_1_3_1: DPR16X4C - generic map (initval=> "0x0000000000000000") - port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3), - WCK=>Clock, WRE=>dec3_wre15, RAD0=>shreg_addr_r0, - RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, - RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, - WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, - WAD3=>shreg_addr_w3, DO0=>mdL0_3_0, DO1=>mdL0_3_1, - DO2=>mdL0_3_2, DO3=>mdL0_3_3); - -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of dynamic_shift_register8x64 is - for Structure - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FSUB2B use entity ecp3.FSUB2B(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX41 use entity ecp3.MUX41(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/nxyter/nodelist.txt b/nxyter/nodelist.txt index 1d2a471..0c760d8 100755 --- a/nxyter/nodelist.txt +++ b/nxyter/nodelist.txt @@ -1,25 +1,50 @@ -[ash] +[pbs1] system = linux -corenum = 4 -env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[dallas] +[pbs2] system = linux -corenum = 4 -env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[vasquez] +[pbs3] system = linux -corenum = 4 -env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[bishop] +[pbs4] system = linux -corenum = 4 -env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[lambert] +[pbs5] system = linux -corenum = 4 -env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs6] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs7] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs8] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs9] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs10] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ diff --git a/nxyter/source/adc_ad9228.vhd b/nxyter/source/adc_ad9228.vhd index 2d95b39..92cc132 100644 --- a/nxyter/source/adc_ad9228.vhd +++ b/nxyter/source/adc_ad9228.vhd @@ -71,17 +71,14 @@ architecture Behavioral of adc_ad9228 is signal q_1 : std_logic_vector(19 downto 0); -- ADC Data Handler - signal adc0_error_status_c : std_logic_vector(2 downto 0); - signal adc1_error_status_c : std_logic_vector(2 downto 0); - signal adc0_error_status_sl : std_logic_vector(2 downto 0); - signal adc1_error_status_sl : std_logic_vector(2 downto 0); - signal adc0_error_status : std_logic_vector(2 downto 0); - signal adc1_error_status : std_logic_vector(2 downto 0); + signal adc0_error_status_o : std_logic_vector(2 downto 0); + signal adc1_error_status_o : std_logic_vector(2 downto 0); signal adc0_sloppy_frame_f : std_logic; signal adc0_sloppy_frame_c : std_logic; signal adc1_sloppy_frame_f : std_logic; signal adc1_sloppy_frame_c : std_logic; + signal adc0_debug : std_logic_vector(15 downto 0); -- Data Types type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); @@ -112,7 +109,9 @@ architecture Behavioral of adc_ad9228 is signal RESET_CLKDIV : std_logic; signal RESET_ADC0 : std_logic; signal RESET_ADC1 : std_logic; - + + signal debug_state : std_logic_vector(1 downto 0); + -- attribute syn_keep : boolean; @@ -145,41 +144,32 @@ begin ----------------------------------------------------------------------------- DFALSE: if (DEBUG_ENABLE = false) generate - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(3 downto 1) <= adc0_error_status; - DEBUG_OUT(4) <= adc0_data_clk_o; - DEBUG_OUT(5) <= adc0_locked_o; - DEBUG_OUT(15 downto 6) <= (others => '0'); - --DEBUG_OUT(0) <= CLK_IN; - --DEBUG_OUT(1) <= DDR_DATA_CLK; - --DEBUG_OUT(2) <= adc0_write_enable; - --DEBUG_OUT(3) <= adc0_fifo_full; - --DEBUG_OUT(4) <= adc0_fifo_empty; - --DEBUG_OUT(5) <= adc0_data_clk_m; - --DEBUG_OUT(6) <= adc0_read_enable; - --DEBUG_OUT(7) <= adc0_read_enable_t; - --DEBUG_OUT(8) <= adc0_read_enable_tt; - --DEBUG_OUT(9) <= adc0_data_clk_o; - --DEBUG_OUT(10) <= adc0_error; - --DEBUG_OUT(11) <= adc0_frame_locked; - --DEBUG_OUT(12) <= adc0_frame_clk_ok; - --DEBUG_OUT(13) <= wait_timer_done; - --DEBUG_OUT(14) <= RESET_CLKDIV; - --DEBUG_OUT(15) <= RESET_ADC0; + DEBUG_OUT <= (others => '0'); + end generate DFALSE; DTRUE: if (DEBUG_ENABLE = true) generate PROC_DEBUG: process (DEBUG_IN) begin - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= DDR_DATA_CLK; - case DEBUG_IN is - - when others => - DEBUG_OUT(15 downto 2) <= (others => '0'); + when x"1" => + DEBUG_OUT <= adc0_debug; + when others => + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= '0'; + DEBUG_OUT(2) <= wait_timer_start; + DEBUG_OUT(3) <= '0'; + DEBUG_OUT(4) <= wait_timer_done; + DEBUG_OUT(5) <= '0'; + DEBUG_OUT(6) <= RESET_CLKDIV; + DEBUG_OUT(7) <= '0'; + DEBUG_OUT(8) <= RESET_ADC0; + DEBUG_OUT(9) <= '0'; + DEBUG_OUT(11 downto 10) <= debug_state; + DEBUG_OUT(15 downto 12) <= (others => '0'); + end case; end process PROC_DEBUG; @@ -225,7 +215,7 @@ begin adc0_sloppy_frame_f <= ADC0_SLOPPY_FRAME_IN when rising_edge(CLK_IN); adc0_sloppy_frame_c <= adc0_sloppy_frame_f when rising_edge(CLK_IN); - adc_ad9228_data_handler_1: entity work.adc_ad9228_data_handler + adc_ad9228_data_handler_adc0: entity work.adc_ad9228_data_handler generic map ( DEBUG_ENABLE => DEBUG_ENABLE ) @@ -241,15 +231,15 @@ begin DATA_CLK_OUT => adc0_data_clk_o, SLOPPY_FRAME_IN => adc0_sloppy_frame_c, FRAME_LOCKED_OUT => adc0_locked_o, - ERROR_STATUS_OUT => adc0_error_status, - ERROR_STATUS_SL_OUT => adc0_error_status_sl, - DEBUG_OUT => open + STATUS_OUT => adc0_error_status_o, + STATUS_CLK_OUT => open, + DEBUG_OUT => adc0_debug ); adc1_sloppy_frame_f <= ADC1_SLOPPY_FRAME_IN when rising_edge(CLK_IN); adc1_sloppy_frame_c <= adc1_sloppy_frame_f when rising_edge(CLK_IN); - adc_ad9228_data_handler_2: entity work.adc_ad9228_data_handler + adc_ad9228_data_handler_adc1: entity work.adc_ad9228_data_handler generic map ( DEBUG_ENABLE => DEBUG_ENABLE ) @@ -265,8 +255,8 @@ begin DATA_CLK_OUT => adc1_data_clk_o, SLOPPY_FRAME_IN => adc1_sloppy_frame_c, FRAME_LOCKED_OUT => adc1_locked_o, - ERROR_STATUS_OUT => open, --ERROR_STATUS_OUT, - ERROR_STATUS_SL_OUT => open, --ERROR_STATUS_OUT, + STATUS_OUT => adc1_error_status_o, + STATUS_CLK_OUT => open, DEBUG_OUT => open ); @@ -299,7 +289,8 @@ begin RESET_ADC1 <= '0'; wait_timer_start <= '0'; timer_reset <= '1'; - R_STATE <= R_IDLE; + R_STATE <= R_IDLE; + debug_state <= "00"; else RESET_CLKDIV <= '0'; RESET_ADC0 <= '0'; @@ -320,6 +311,7 @@ begin timer_reset <= '1'; R_STATE <= R_IDLE; end if; + debug_state <= "00"; when R_WAIT_CLKDIV => if (wait_timer_done = '0') then @@ -334,7 +326,8 @@ begin wait_timer_start <= '1'; R_STATE <= R_WAIT_RESET_ADC; end if; - + debug_state <= "01"; + when R_WAIT_RESET_ADC => if (wait_timer_done = '0') then RESET_ADC0 <= '1'; @@ -345,13 +338,15 @@ begin wait_timer_start <= '1'; R_STATE <= R_WAIT_RESET_END; end if; - + debug_state <= "10"; + when R_WAIT_RESET_END => if (wait_timer_done = '0') then R_STATE <= R_WAIT_RESET_END; else R_STATE <= R_IDLE; - end if; + end if; + debug_state <= "11"; end case; end if; end if; @@ -378,10 +373,6 @@ begin ADC0_LOCKED_OUT <= adc0_locked_o; ADC1_LOCKED_OUT <= adc1_locked_o; - ADC0_ERROR_STATUS_OUT <= adc0_error_status_c - when adc0_sloppy_frame_c = '0' - else adc0_error_status_sl; - ADC1_ERROR_STATUS_OUT <= adc1_error_status_c - when adc1_sloppy_frame_c = '0' - else adc1_error_status_sl; + ADC0_ERROR_STATUS_OUT <= adc0_error_status_o; + ADC1_ERROR_STATUS_OUT <= adc1_error_status_o; end Behavioral; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 184bc48..df95b98 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -62,9 +62,6 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- -- NX_TIMESTAMP_IN Process - signal nx_timestamp_delay_f : unsigned(2 downto 0); - signal nx_timestamp_delay : unsigned(2 downto 0); - signal nx_shift_register_delay : std_logic_vector(5 downto 0); signal nx_frame_word_ff : std_logic_vector(7 downto 0); signal nx_frame_word_f : std_logic_vector(7 downto 0); signal nx_frame_word_s : std_logic_vector(7 downto 0); @@ -82,24 +79,42 @@ architecture Behavioral of nx_data_receiver is signal nx_frame_synced : std_logic; signal rs_sync_set : std_logic; signal rs_sync_reset : std_logic; - - -- NX Timestamp Frame Delay - type delay_array_b is array(0 to 3) of std_logic_vector(31 downto 0); - signal nx_frame_word_delayed_t : delay_array_b; - signal nx_frame_clk_delayed_t : std_logic_vector(3 downto 0); - signal nx_timestamp_delayed : std_logic_vector(31 downto 0); - signal nx_timestamp_delayed_clk : std_logic; - - signal nx_frame_word_delay_f : unsigned(1 downto 0); - signal nx_frame_word_delay : unsigned(1 downto 0); - signal adc_data_clk_last : std_logic_vector(3 downto 0); - signal frame_word_delay_change : std_logic; - signal frame_word_delay_set : std_logic; + -- NX Frame Delay + signal nx_timestamp_delay_f : unsigned(2 downto 0); + signal nx_timestamp_delay : unsigned(2 downto 0); + signal nx_data : std_logic_vector(31 downto 0); + signal nx_data_clk : std_logic; + + -- Merge Data Streams + signal merge_handler_reset_i : std_logic; + signal merge_handler_reset : std_logic; + signal adc_data_buffer : std_logic_vector(11 downto 0); + signal adc_data_buffer_filled : std_logic; + signal data_m : std_logic_vector(43 downto 0); + signal data_clk_m : std_logic; + + signal merge_timeout_ctr : unsigned(3 downto 0); + signal merge_timeout_error : std_logic; + signal merge_error_ctr : unsigned(11 downto 0); + signal merge_error : std_logic; + + -- Data Clock Domain Transfer + signal fifo_reset_i : std_logic; + signal fifo_write_enable : std_logic; + signal fifo_read_enable : std_logic; + signal fifo_empty : std_logic; + signal fifo_full : std_logic; + signal fifo_data_clk_tt : std_logic; + signal fifo_data_clk_t : std_logic; + signal fifo_data_clk : std_logic; + + signal fifo_data : std_logic_vector(43 downto 0); -- ADC Ckl Generator signal adc_sclk_skip : std_logic; signal adc_sampling_clk : std_logic; + signal nx_shift_register_delay : std_logic_vector(5 downto 0); signal johnson_ff_0 : std_logic; signal johnson_ff_1 : std_logic; signal johnson_counter_sync : std_logic_vector(1 downto 0); @@ -142,15 +157,6 @@ architecture Behavioral of nx_data_receiver is signal adc_debug_type_f : std_logic_vector(3 downto 0); signal adc_debug_type : std_logic_vector(3 downto 0); - -- Merge Data Streams - signal merge_handler_reset_i : std_logic; - signal merge_handler_reset : std_logic; - signal data_frame : std_logic_vector(43 downto 0); - signal data_frame_clk : std_logic; - signal merge_timeout_ctr : unsigned(3 downto 0); - signal merge_timeout_error : std_logic; - signal merge_error_ctr : unsigned(11 downto 0); - -- Data Output Handler signal data_o : std_logic_vector(43 downto 0); signal data_clk_o : std_logic; @@ -184,6 +190,7 @@ architecture Behavioral of nx_data_receiver is signal error_o : std_logic; signal error_status_bits : std_logic_vector(15 downto 0); + -- Rate Errors signal nx_frame_rate_offline_last : std_logic; signal nx_frame_rate_offline : std_logic; @@ -200,10 +207,10 @@ architecture Behavioral of nx_data_receiver is signal timestamp_dt_error : std_logic; -- Data Stream DeltaT Error Counters - signal new_adc_dt_ctr : unsigned(3 downto 0); - signal new_timestamp_dt_ctr : unsigned(3 downto 0); - signal new_adc_dt_error_ctr : unsigned(11 downto 0); - signal new_timestamp_dt_error_ctr : unsigned(11 downto 0); + signal adc_dt_ctr : unsigned(3 downto 0); + signal timestamp_dt_ctr : unsigned(3 downto 0); + signal adc_dt_error_ctr : unsigned(11 downto 0); + signal timestamp_dt_error_ctr : unsigned(11 downto 0); signal adc_dt_error_p : std_logic; signal adc_dt_error_c100 : std_logic; @@ -215,16 +222,6 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- -- NX FIFO READ ENABLE - signal fifo_reset_i : std_logic; - signal fifo_write_enable : std_logic; - signal fifo_read_enable : std_logic; - signal fifo_empty : std_logic; - signal fifo_full : std_logic; - signal fifo_data_clk_tt : std_logic; - signal fifo_data_clk_t : std_logic; - signal fifo_data_clk : std_logic; - - signal fifo_data : std_logic_vector(43 downto 0); -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); @@ -244,13 +241,15 @@ architecture Behavioral of nx_data_receiver is signal nx_timestamp_delay_r : unsigned(2 downto 0); signal nx_timestamp_delay_a : unsigned(2 downto 0); signal nx_timestamp_delay_s : unsigned(2 downto 0); + signal nx_timestamp_delay_s_last : unsigned(2 downto 0); signal nx_timestamp_delay_actr : unsigned(15 downto 0); + signal reset_inhibit_ts_delay : std_logic; signal fifo_full_rr : std_logic; signal fifo_full_r : std_logic; signal fifo_empty_rr : std_logic; signal fifo_empty_r : std_logic; - signal new_adc_dt_error_ctr_r : unsigned(11 downto 0); - signal new_timestamp_dt_error_ctr_r : unsigned(11 downto 0); + signal adc_dt_error_ctr_r : unsigned(11 downto 0); + signal timestamp_dt_error_ctr_r : unsigned(11 downto 0); signal adc_notlock_ctr_r : unsigned(7 downto 0); signal merge_error_ctr_r : unsigned(11 downto 0); signal nx_frame_synced_rr : std_logic; @@ -258,18 +257,19 @@ architecture Behavioral of nx_data_receiver is signal disable_adc_r : std_logic; signal adc_debug_type_r : std_logic_vector(3 downto 0); - signal adc_sloppy_frame : std_logic; -- not used - signal reset_inhibit_r : std_logic; -- not used + signal adc_sloppy_frame : std_logic; + signal reset_inhibit_r : std_logic; ----------------------------------------------------------------------------- -- Reset Handler ----------------------------------------------------------------------------- + signal reset_inhibit_start : std_logic; + signal reset_inhibit : std_logic; signal disable_resets : std_logic; - signal disable_adc_resets : std_logic; + signal disable_adc_resets : std_logic; signal nx_online_ii : std_logic; signal nx_online_i : std_logic; signal adc_error : std_logic; - signal adc_error_undef : std_logic; signal startup_reset : std_logic; signal rs_wait_timer_start : std_logic; signal rs_wait_timer_done : std_logic; @@ -283,6 +283,7 @@ architecture Behavioral of nx_data_receiver is signal reset_handler_trigger : std_logic_vector(15 downto 0); type R_STATES is (R_IDLE, + R_WAIT_INHIBIT, R_START, R_WAIT_0, R_WAIT_NX_ONLINE, @@ -303,14 +304,11 @@ architecture Behavioral of nx_data_receiver is signal adc_reset_handler : std_logic; signal adc_reset_p : std_logic; signal output_handler_reset : std_logic; - signal disable_adc_f : std_logic; - signal disable_adc : std_logic; signal reset_handler_counter : unsigned(15 downto 0); signal reset_handler_busy : std_logic; signal reset_timeout_flag : std_logic; - signal adc_reset_handler_cnx_ff : std_logic; signal adc_reset_handler_cnx_f : std_logic; signal adc_reset_handler_cnx : std_logic; @@ -343,21 +341,15 @@ architecture Behavioral of nx_data_receiver is attribute syn_keep of adc_reset_handler_cnx_ff : signal is true; attribute syn_keep of adc_reset_handler_cnx_f : signal is true; - attribute syn_keep of nx_frame_clk_delayed_t : signal is true; - attribute syn_keep of nx_frame_word_delayed_t : signal is true; - + attribute syn_keep of merge_handler_reset_i : signal is true; + attribute syn_keep of merge_handler_reset : signal is true; + attribute syn_keep of nx_online_ii : signal is true; attribute syn_keep of nx_online_i : signal is true; - attribute syn_keep of disable_adc_f : signal is true; - attribute syn_keep of disable_adc : signal is true; - attribute syn_keep of adc_debug_type_f : signal is true; attribute syn_keep of adc_debug_type : signal is true; - attribute syn_keep of nx_frame_word_delay_f : signal is true; - attribute syn_keep of nx_frame_word_delay : signal is true; - attribute syn_keep of nx_frame_word_f : signal is true; attribute syn_preserve : boolean; @@ -367,21 +359,15 @@ architecture Behavioral of nx_data_receiver is attribute syn_preserve of adc_reset_handler_cnx_ff : signal is true; attribute syn_preserve of adc_reset_handler_cnx_f : signal is true; - attribute syn_preserve of nx_frame_clk_delayed_t : signal is true; - attribute syn_preserve of nx_frame_word_delayed_t : signal is true; - + attribute syn_preserve of merge_handler_reset_i : signal is true; + attribute syn_preserve of merge_handler_reset : signal is true; + attribute syn_preserve of nx_online_ii : signal is true; attribute syn_preserve of nx_online_i : signal is true; - attribute syn_preserve of disable_adc_f : signal is true; - attribute syn_preserve of disable_adc : signal is true; - attribute syn_preserve of adc_debug_type_f : signal is true; attribute syn_preserve of adc_debug_type : signal is true; - attribute syn_preserve of nx_frame_word_delay_f : signal is true; - attribute syn_preserve of nx_frame_word_delay : signal is true; - attribute syn_preserve of nx_frame_word_f : signal is true; begin @@ -404,7 +390,6 @@ begin fifo_write_enable, fifo_empty, fifo_read_enable, - nx_timestamp_delayed_clk, adc_data_s_clk, data_clk_o, nx_frame_synced, @@ -428,7 +413,7 @@ begin DEBUG_OUT(11) <= pll_adc_sampling_clk_reset; DEBUG_OUT(15 downto 12) <= debug_state; - when "010" => + when "010" => -- Works -- AD9228 Handler Debug output DEBUG_OUT <= ADC_DEBUG; @@ -449,39 +434,22 @@ begin DEBUG_OUT(14) <= frame_rate_error; DEBUG_OUT(15) <= reset_timeout_flag; - when "100" => - -- AD9228 Handler Debug output - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= '0'; - DEBUG_OUT(2) <= nx_frame_clk; - DEBUG_OUT(3) <= '0'; - DEBUG_OUT(4) <= nx_timestamp_delayed_clk; - DEBUG_OUT(5) <= '0'; - DEBUG_OUT(6) <= adc_data_clk; - DEBUG_OUT(7) <= '0'; - DEBUG_OUT(8) <= fifo_write_enable; - DEBUG_OUT(9) <= '0'; - DEBUG_OUT(10) <= data_frame_clk; - DEBUG_OUT(11) <= '0'; - DEBUG_OUT(12) <= nx_frame_synced; - DEBUG_OUT(13) <= '0'; - DEBUG_OUT(14) <= frame_word_delay_change; - DEBUG_OUT(15) <= data_clk_o; - - when "101" => - -- AD9228 Handler Debug output + when "100" => -- Works + -- Merge Handler DEBUG_OUT(0) <= NX_DATA_CLK_IN; DEBUG_OUT(1) <= '0'; - DEBUG_OUT(2) <= nx_frame_clk; - DEBUG_OUT(3) <= '0'; - DEBUG_OUT(4) <= nx_timestamp_delayed_clk; - DEBUG_OUT(5) <= merge_timeout_error; - DEBUG_OUT(6) <= adc_data_s_clk; - DEBUG_OUT(7) <= data_frame_clk; - DEBUG_OUT(9 downto 8) <= nx_frame_word_delay; - DEBUG_OUT(10) <= frame_word_delay_change; - DEBUG_OUT(11) <= frame_word_delay_set; - DEBUG_OUT(15 downto 12) <= adc_data_clk_last; + DEBUG_OUT(2) <= nx_data_clk; + DEBUG_OUT(3) <= timestamp_dt_error; + DEBUG_OUT(4) <= '0'; + DEBUG_OUT(5) <= adc_dt_error; + DEBUG_OUT(8 downto 6) <= adc_error_status_i; + DEBUG_OUT(9) <= adc_data_buffer_filled; + DEBUG_OUT(10) <= merge_error; + DEBUG_OUT(11) <= nx_data_clk; + DEBUG_OUT(12) <= adc_data_clk; + DEBUG_OUT(13) <= data_clk_m; + DEBUG_OUT(14) <= CLK_IN; + DEBUG_OUT(15) <= data_clk_o; when "110" => DEBUG_OUT(0) <= NX_DATA_CLK_IN; @@ -505,7 +473,7 @@ begin -- Default DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(1) <= TRIGGER_IN; - DEBUG_OUT(2) <= data_frame_clk; + DEBUG_OUT(2) <= data_clk_m; DEBUG_OUT(3) <= fifo_reset_handler; DEBUG_OUT(4) <= fifo_full; DEBUG_OUT(5) <= fifo_write_enable; @@ -513,7 +481,7 @@ begin DEBUG_OUT(7) <= fifo_read_enable; DEBUG_OUT(8) <= fifo_data_clk; DEBUG_OUT(9) <= nx_frame_clk; - DEBUG_OUT(10) <= nx_timestamp_delayed_clk; + DEBUG_OUT(10) <= '0'; DEBUG_OUT(11) <= adc_data_s_clk; DEBUG_OUT(12) <= data_clk_o; DEBUG_OUT(13) <= parity_error_c100; @@ -656,7 +624,7 @@ begin TIMER_DONE_OUT => rs_timeout_timer_done ); - pulse_dtrans_1: pulse_dtrans + pulse_dtrans_1: pulse_dtrans generic map ( CLK_RATIO => 4 ) @@ -745,65 +713,21 @@ begin nx_frame_word_ff <= NX_TIMESTAMP_IN when rising_edge(NX_DATA_CLK_IN); nx_frame_word_f <= nx_frame_word_ff when rising_edge(NX_DATA_CLK_IN); - -- Second delay NX_TIMESTAMP_IN relatively to ADC Clock - dynamic_shift_register8x64_1: entity work.dynamic_shift_register8x64 - port map ( - Din => nx_frame_word_f, - Addr => nx_shift_register_delay, - Clock => NX_DATA_CLK_IN, - ClockEn => '1', - Reset => RESET_NX_DATA_CLK_IN, - Q => nx_frame_word_s - ); - - -- Timestamp Input Delay relative to ADC - PROC_NX_SHIFT_REGISTER_DELAY: process(NX_DATA_CLK_IN) - begin - if (rising_edge(NX_DATA_CLK_IN)) then - nx_timestamp_delay_f <= nx_timestamp_delay_s; - if( RESET_NX_DATA_CLK_IN = '1' ) then - nx_timestamp_delay <= "010"; - nx_shift_register_delay <= "011011"; -- 27 - else - nx_timestamp_delay <= nx_timestamp_delay_f; - - case nx_timestamp_delay is - when "000" => - nx_shift_register_delay <= "011011"; -- 27 - - when "001" => - nx_shift_register_delay <= "011111"; -- 31 - - when "010" => - nx_shift_register_delay <= "100011"; -- 35 - - when "011" => - nx_shift_register_delay <= "100111"; -- 39 - - when "100" => - nx_shift_register_delay <= "101011"; -- 43 - - when others => null; - end case; - end if; - end if; - end process PROC_NX_SHIFT_REGISTER_DELAY; - -- Merge TS Data 8bit to 32Bit Timestamp Frame PROC_8_TO_32_BIT: process(NX_DATA_CLK_IN) begin if (rising_edge(NX_DATA_CLK_IN)) then case frame_byte_pos is - when "11" => nx_frame_word_t(31 downto 24) <= nx_frame_word_s; + when "11" => nx_frame_word_t(31 downto 24) <= nx_frame_word_f; nx_frame_clk_t <= '0'; - when "10" => nx_frame_word_t(23 downto 16) <= nx_frame_word_s; + when "10" => nx_frame_word_t(23 downto 16) <= nx_frame_word_f; nx_frame_clk_t <= '0'; - when "01" => nx_frame_word_t(15 downto 8) <= nx_frame_word_s; + when "01" => nx_frame_word_t(15 downto 8) <= nx_frame_word_f; nx_frame_clk_t <= '0'; - when "00" => nx_frame_word_t( 7 downto 0) <= nx_frame_word_s; + when "00" => nx_frame_word_t( 7 downto 0) <= nx_frame_word_f; nx_frame_clk_t <= '1'; end case; @@ -897,85 +821,12 @@ begin parity_error <= '0'; end if; else - parity_error <= '0'; + parity_error <= '0'; end if; end if; end if; end process PROC_PARITY_CHECKER; - ----------------------------------------------------------------------------- - -- Delay NX Timestamp relative to ADC Frames - ----------------------------------------------------------------------------- - PROC_NX_TIMESTAMP_FRAME_DELAY: process(NX_DATA_CLK_IN) - begin - if (rising_edge(NX_DATA_CLK_IN)) then - nx_frame_word_delay <= nx_frame_word_delay_f; - nx_frame_word_delayed_t(0) <= nx_frame_word; - nx_frame_clk_delayed_t(0) <= nx_frame_clk; - - -- Delay Pipeline NX Clock - for X in 1 to 3 loop - nx_frame_word_delayed_t(X) <= nx_frame_word_delayed_t(X - 1); - nx_frame_clk_delayed_t(X) <= nx_frame_clk_delayed_t(X - 1); - end loop; - - -- Output - nx_timestamp_delayed_clk <= - nx_frame_clk_delayed_t(to_integer(nx_frame_word_delay)); - nx_timestamp_delayed <= - nx_frame_word_delayed_t(to_integer(nx_frame_word_delay)); - end if; - end process PROC_NX_TIMESTAMP_FRAME_DELAY; - - PROC_NX_FRAME_WORD_DELAY_AUTO_SETUP: process(NX_DATA_CLK_IN) - begin - if (rising_edge(NX_DATA_CLK_IN)) then - adc_data_clk_last(0) <= adc_data_s_clk; - - if (RESET_NX_DATA_CLK_IN = '1') then - nx_frame_word_delay_f <= "10"; - adc_data_clk_last(3 downto 1) <= (others => '0'); - frame_word_delay_change <= '0'; - frame_word_delay_set <= '0'; - else - for I in 1 to 3 loop - adc_data_clk_last(I) <= adc_data_clk_last(I - 1); - end loop; - frame_word_delay_change <= '0'; - frame_word_delay_set <= '0'; - - if (disable_adc = '1') then - nx_frame_word_delay_f <= "10"; - frame_word_delay_set <= '1'; - else - if (nx_timestamp_delayed_clk = '1') then - case adc_data_clk_last is - when "0100" => - nx_frame_word_delay_f <= nx_frame_word_delay_f + 1; - frame_word_delay_change <= '1'; - - when "0010" => - nx_frame_word_delay_f <= nx_frame_word_delay_f + 2; - frame_word_delay_change <= '1'; - - when "0001" => - nx_frame_word_delay_f <= nx_frame_word_delay_f + 3; - frame_word_delay_change <= '1'; - - when others => - null; - - end case; - - if (adc_data_s_clk = '1') then - frame_word_delay_set <= '1'; - end if; - end if; - end if; - end if; - end if; - end process PROC_NX_FRAME_WORD_DELAY_AUTO_SETUP; - ----------------------------------------------------------------------------- -- ADC Input Handler ----------------------------------------------------------------------------- @@ -994,11 +845,12 @@ begin ----------------------------------------------------------------------------- - ADC_RESET_AD9228 <= RESET_NX_DATA_CLK_IN or adc_reset_handler_cnx; + --ADC_RESET_AD9228 <= RESET_NX_DATA_CLK_IN or adc_reset_handler_cnx; + ADC_RESET_AD9228 <= adc_reset_handler_cnx; adc_ad9228_1: adc_ad9228 generic map ( - DEBUG_ENABLE => false + DEBUG_ENABLE => true ) port map ( CLK_IN => NX_DATA_CLK_IN, @@ -1039,73 +891,125 @@ begin ADC0_LOCKED_OUT => adc_locked, ADC1_LOCKED_OUT => open, - ADC0_SLOPPY_FRAME_IN => adc_sloppy_frame, - ADC1_SLOPPY_FRAME_IN => '0', + ADC0_SLOPPY_FRAME_IN => adc_sloppy_frame, + ADC1_SLOPPY_FRAME_IN => '0', ADC0_ERROR_STATUS_OUT => adc_error_status_i, ADC1_ERROR_STATUS_OUT => open, - DEBUG_IN => adc_debug_type, - DEBUG_OUT => ADC_DEBUG + DEBUG_IN => adc_debug_type, + DEBUG_OUT => ADC_DEBUG + ); + + ----------------------------------------------------------------------------- + -- Delay NX Data relative to ADC + ----------------------------------------------------------------------------- + + dynamic_shift_register33x64_1: entity work.dynamic_shift_register33x64 + port map ( + Din(31 downto 0) => nx_frame_word, + Din(32) => nx_frame_clk, + Addr => nx_shift_register_delay, + Clock => NX_DATA_CLK_IN, + ClockEn => '1', + Reset => RESET_NX_DATA_CLK_IN, + Q(31 downto 0) => nx_data, + Q(32) => nx_data_clk ); - -- Deprecated --> REMOVE - PROC_ADC_DATA_BIT_SHIFT: process(NX_DATA_CLK_IN) - variable adcval : unsigned(11 downto 0) := (others => '0'); + nx_timestamp_delay_f <= nx_timestamp_delay_s + when rising_edge(NX_DATA_CLK_IN); + nx_timestamp_delay <= nx_timestamp_delay_f + when rising_edge(NX_DATA_CLK_IN); + + PROC_NX_SHIFT_REGISTER_DELAY: process(NX_DATA_CLK_IN) begin if (rising_edge(NX_DATA_CLK_IN)) then - if (adc_data_clk = '1') then - adc_data_s <= adc_data; - adc_data_s_clk <= '1'; + if(RESET_NX_DATA_CLK_IN = '1') then + nx_shift_register_delay <= (others => '0'); else - adc_data_s <= x"aff"; - adc_data_s_clk <= '0'; + case nx_timestamp_delay is + when "000" => + nx_shift_register_delay <= "011011"; -- 27 + + when "001" => + nx_shift_register_delay <= "011111"; -- 31 + + when "010" => + nx_shift_register_delay <= "100011"; -- 35 + + when "011" => + nx_shift_register_delay <= "100111"; -- 39 + + when "100" => + nx_shift_register_delay <= "101011"; -- 43 + + when "101" => + nx_shift_register_delay <= "101111"; -- 47 + + when "110" => + nx_shift_register_delay <= "110011"; -- 51 + + when "111" => + nx_shift_register_delay <= "111111"; -- 55 + + end case; end if; end if; - end process PROC_ADC_DATA_BIT_SHIFT; + end process PROC_NX_SHIFT_REGISTER_DELAY; ----------------------------------------------------------------------------- -- Merge Data Streams Timestamps and ADC Value ----------------------------------------------------------------------------- - merge_handler_reset_i <= output_handler_reset - when rising_edge(NX_DATA_CLK_IN); - merge_handler_reset <= merge_handler_reset_i - when rising_edge(NX_DATA_CLK_IN); - disable_adc_f <= disable_adc_r when rising_edge(NX_DATA_CLK_IN); - disable_adc <= disable_adc_f when rising_edge(NX_DATA_CLK_IN); + merge_handler_reset_i <= output_handler_reset + when rising_edge(NX_DATA_CLK_IN); + merge_handler_reset <= merge_handler_reset_i + when rising_edge(NX_DATA_CLK_IN); + PROC_DATA_MERGE_HANDLER: process(NX_DATA_CLK_IN) begin if (rising_edge(NX_DATA_CLK_IN)) then - if (RESET_NX_DATA_CLK_IN = '1' or merge_handler_reset = '1') then - merge_timeout_ctr <= (others => '0'); - merge_timeout_error <= '0'; - merge_error_ctr <= (others => '0'); + if (RESET_IN = '1') then + data_m <= (others => '0'); + data_clk_m <= '0'; + adc_data_buffer <= (others => '0'); + adc_data_buffer_filled <= '0'; + merge_error <= '0'; + merge_error_ctr <= (others => '0'); else - if (nx_timestamp_delayed_clk = '1' and - (adc_data_s_clk = '1' or disable_adc = '1') - ) then - data_frame(31 downto 0) <= nx_timestamp_delayed; - if (disable_adc = '0') then - data_frame(43 downto 32) <= adc_data_s; + data_m <= (others => '0'); + data_clk_m <= '0'; + merge_error <= '0'; + + if (nx_data_clk = '1') then + data_m(31 downto 0) <= nx_data; + data_clk_m <= '1'; + + -- Look for ADC Data, add if available + if (adc_data_clk = '1') then + data_m(43 downto 32) <= adc_data; + elsif (adc_data_buffer_filled = '1') then + data_m(43 downto 32) <= adc_data_buffer; + adc_data_buffer_filled <= '0'; else - data_frame(43 downto 32) <= x"000"; + -- No ADC Data Available, error + data_m(43 downto 32) <= (others => '0'); + merge_error <= '1'; end if; - data_frame_clk <= '1'; - merge_timeout_ctr <= (others => '0'); - else - data_frame <= (others => '0'); - data_frame_clk <= '0'; - merge_timeout_ctr <= merge_timeout_ctr + 1; - end if; - -- Timeout? - if (merge_timeout_ctr > x"3") then - merge_timeout_error <= '1'; - merge_error_ctr <= merge_error_ctr + 1; - else - merge_timeout_error <= '0'; + elsif (adc_data_clk = '1') then + if (adc_data_buffer_filled = '0') then + adc_data_buffer <= adc_data; + adc_data_buffer_filled <= '1'; + else + -- Already Full, error + merge_error <= '1'; + merge_error_ctr <= merge_error_ctr + 1; + adc_data_buffer_filled <= '0'; + end if; end if; + end if; end if; end process PROC_DATA_MERGE_HANDLER; @@ -1116,7 +1020,7 @@ begin fifo_data_stream_44to44_dc_1: fifo_data_stream_44to44_dc port map ( - Data => data_frame, + Data => data_m, WrClock => NX_DATA_CLK_IN, RdClock => CLK_IN, WrEn => fifo_write_enable, @@ -1128,7 +1032,7 @@ begin Full => fifo_full ); fifo_reset_i <= RESET_IN or fifo_reset_handler; - fifo_write_enable <= not fifo_full and data_frame_clk; + fifo_write_enable <= not fifo_full and data_clk_m; fifo_read_enable <= not fifo_empty; PROC_NX_FIFO_READ_ENABLE: process(CLK_IN) @@ -1385,34 +1289,34 @@ begin begin if (rising_edge(NX_DATA_CLK_IN)) then if (RESET_NX_DATA_CLK_IN = '1') then - new_adc_dt_ctr <= (others => '0'); - new_timestamp_dt_ctr <= (others => '0'); - new_adc_dt_error_ctr <= (others => '0'); - new_timestamp_dt_error_ctr <= (others => '0'); + adc_dt_ctr <= (others => '0'); + timestamp_dt_ctr <= (others => '0'); + adc_dt_error_ctr <= (others => '0'); + timestamp_dt_error_ctr <= (others => '0'); else - adc_dt_error_p <= '0'; - timestamp_dt_error_p <= '0'; + adc_dt_error_p <= '0'; + timestamp_dt_error_p <= '0'; -- ADC if (adc_data_clk = '1') then - if (new_adc_dt_ctr /= x"3" ) then - new_adc_dt_error_ctr <= new_adc_dt_error_ctr + 1; - adc_dt_error_p <= '1'; + if (adc_dt_ctr /= x"3" ) then + adc_dt_error_ctr <= adc_dt_error_ctr + 1; + adc_dt_error_p <= '1'; end if; - new_adc_dt_ctr <= (others => '0'); + adc_dt_ctr <= (others => '0'); else - new_adc_dt_ctr <= new_adc_dt_ctr + 1; + adc_dt_ctr <= adc_dt_ctr + 1; end if; -- TimeStamp if (nx_frame_clk = '1') then - if (new_timestamp_dt_ctr /= x"3") then - new_timestamp_dt_error_ctr <= new_timestamp_dt_error_ctr + 1; + if (timestamp_dt_ctr /= x"3") then + timestamp_dt_error_ctr <= timestamp_dt_error_ctr + 1; timestamp_dt_error_p <= '1'; end if; - new_timestamp_dt_ctr <= (others => '0'); + timestamp_dt_ctr <= (others => '0'); else - new_timestamp_dt_ctr <= new_timestamp_dt_ctr + 1; + timestamp_dt_ctr <= timestamp_dt_ctr + 1; end if; end if; @@ -1422,9 +1326,22 @@ begin ----------------------------------------------------------------------------- -- Reset Handler ----------------------------------------------------------------------------- + nx_online_ii <= NX_ONLINE_IN when rising_edge(CLK_IN); + nx_online_i <= nx_online_ii when rising_edge(CLK_IN); - nx_online_ii <= NX_ONLINE_IN when rising_edge(CLK_IN); - nx_online_i <= nx_online_ii when rising_edge(CLK_IN); + reset_inhibit_start <= reset_inhibit_ts_delay or reset_inhibit_r; + + timer_static_RESET_INHIBIT: timer_static + generic map ( + CTR_WIDTH => 20, + CTR_END => 500000 -- 5ms + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => reset_inhibit_start, + TIMER_BUSY_OUT => reset_inhibit + ); PROC_RESET_HANDLER: process(CLK_IN) begin @@ -1434,7 +1351,7 @@ begin fifo_reset_handler <= '0'; pll_adc_sampling_clk_reset <= '0'; adc_reset_p <= '0'; - adc_reset_handler <= '0'; +-- adc_reset_handler <= '0'; output_handler_reset <= '0'; rs_wait_timer_start <= '0'; @@ -1452,7 +1369,7 @@ begin fifo_reset_handler <= '0'; pll_adc_sampling_clk_reset <= '0'; adc_reset_p <= '0'; - adc_reset_handler <= '0'; +-- adc_reset_handler <= '0'; output_handler_reset <= '0'; rs_wait_timer_start <= '0'; @@ -1462,17 +1379,22 @@ begin nx_timestamp_reset_o <= '0'; debug_state <= x"0"; - - if (disable_resets = '0') then - - if (reset_handler_start_r = '1') then - -- Reset by register always wins, start it - rs_timeout_timer_reset <= '1'; - reset_timeout_flag <= '0'; - reset_handler_trigger(0) <= '1'; - reset_handler_trigger(15 downto 1) <= (others => '0'); - R_STATE <= R_START; - elsif (rs_timeout_timer_done = '1') then + + if (reset_handler_start_r = '1') then + -- Reset by register always wins, start it + rs_timeout_timer_reset <= '1'; + reset_timeout_flag <= '0'; + reset_handler_trigger(0) <= '1'; + reset_handler_trigger(15 downto 1) <= (others => '0'); + R_STATE <= R_START; + elsif (disable_resets = '1' or reset_inhibit = '1') then + -- Reset Disabled + reset_timeout_flag <= '0'; + rs_timeout_timer_reset <= '1'; + reset_handler_trigger <= (others => '0'); + debug_state <= x"f"; + else + if (rs_timeout_timer_done = '1') then -- Reset Timeout, retry RESET rs_timeout_timer_reset <= '1'; reset_timeout_flag <= '1'; @@ -1485,19 +1407,22 @@ begin if (NX_CLOCK_ON_IN = '1') then if ((disable_adc_r = '0' and disable_adc_resets = '0' and - (pll_adc_not_lock = '1' or - adc_reset_sync = '1' or + (adc_reset_sync = '1' or adc_frame_rate_error = '1' or adc_error = '1' or adc_dt_error = '1' or - adc_sclk_ok_c100 = '0' or adc_locked_c100 = '0' ) ) or - nx_frame_rate_error = '1' or - startup_reset = '1' or - timestamp_dt_error = '1' or - parity_rate_error = '1' + (disable_adc_r = '0' and + (pll_adc_not_lock = '1' or + adc_sclk_ok_c100 = '0' + ) + ) or + parity_rate_error = '1' or + timestamp_dt_error = '1' or + nx_frame_rate_error = '1' or + startup_reset = '1' ) then reset_handler_trigger( 0) <= '0'; @@ -1509,7 +1434,7 @@ begin reset_handler_trigger( 7) <= pll_adc_not_lock; reset_handler_trigger( 8) <= adc_reset_sync; reset_handler_trigger( 9) <= adc_frame_rate_error; - reset_handler_trigger(10) <= '0'; --adc_error; + reset_handler_trigger(10) <= adc_error; reset_handler_trigger(11) <= adc_dt_error ; reset_handler_trigger(12) <= not adc_sclk_ok_c100; reset_handler_trigger(13) <= not adc_locked_c100; @@ -1529,7 +1454,7 @@ begin R_STATE <= R_IDLE; end if; debug_state <= x"1"; - + when R_START => -- First wait 1mue for NX_MAIN_CLK, have to put lock status here -- to check in the future. @@ -1587,7 +1512,7 @@ begin frame_rates_reset <= '1'; pll_adc_sampling_clk_reset <= '1'; adc_reset_p <= '1'; - adc_reset_handler <= '1'; +-- adc_reset_handler <= '1'; output_handler_reset <= '1'; fifo_reset_handler <= '1'; @@ -1598,7 +1523,7 @@ begin when R_WAIT_3 => pll_adc_sampling_clk_reset <= '1'; - adc_reset_handler <= '1'; +-- adc_reset_handler <= '1'; output_handler_reset <= '1'; fifo_reset_handler <= '1'; if (rs_wait_timer_done = '0') then @@ -1615,17 +1540,17 @@ begin if (nx_frame_rate_offline = '0' and nx_frame_rate_error = '0') then -- Next: Release PLL Reset, i.e. sampling_clk_reset - adc_reset_handler <= '1'; +-- adc_reset_handler <= '1'; output_handler_reset <= '1'; fifo_reset_handler <= '1'; - if (disable_adc_r = '0') then - R_STATE <= R_PLL_WAIT_LOCK; - else + if (disable_adc_r = '1' or disable_adc_resets = '1') then R_STATE <= R_WAIT_DATA_HANDLER_OK; + else + R_STATE <= R_PLL_WAIT_LOCK; end if; else pll_adc_sampling_clk_reset <= '1'; - adc_reset_handler <= '1'; +-- adc_reset_handler <= '1'; output_handler_reset <= '1'; fifo_reset_handler <= '1'; R_STATE <= R_WAIT_NX_FRAME_RATE_OK; @@ -1640,7 +1565,7 @@ begin fifo_reset_handler <= '1'; R_STATE <= R_WAIT_ADC_OK; else - adc_reset_handler <= '1'; +-- adc_reset_handler <= '1'; output_handler_reset <= '1'; fifo_reset_handler <= '1'; R_STATE <= R_PLL_WAIT_LOCK; @@ -1672,13 +1597,6 @@ begin debug_state <= x"b"; end case; end if; - - else - -- Reset Disabled - reset_timeout_flag <= '0'; - rs_timeout_timer_reset <= '1'; - reset_handler_trigger <= (others => '0'); - debug_state <= x"f"; end if; end if; end if; @@ -1768,27 +1686,37 @@ begin if (RESET_IN = '1') then nx_timestamp_delay_a <= "010"; nx_timestamp_delay_actr <= (others => '0'); + nx_timestamp_delay_s_last <= (others => '0'); + reset_inhibit_ts_delay <= '0'; else + reset_inhibit_ts_delay <= '0'; + -- Automatic nx_timestamp_delay adjust - if (disable_adc_f = '0' and - nx_timestamp_delay_adjust = '1' and - ADC_TR_ERROR_IN = '1') then - if (nx_timestamp_delay_a <= "100") then - nx_timestamp_delay_a <= nx_timestamp_delay_a + 1; + if (disable_adc_r = '0') then + if (nx_timestamp_delay_adjust = '1' and + ADC_TR_ERROR_IN = '1') then + if (nx_timestamp_delay_a <= "100") then + nx_timestamp_delay_a <= nx_timestamp_delay_a + 1; + else + nx_timestamp_delay_a <= (others => '0'); + end if; + nx_timestamp_delay_actr <= nx_timestamp_delay_actr + 1; + end if; + + -- Multiplexer + if (nx_timestamp_delay_adjust = '1') then + nx_timestamp_delay_s <= nx_timestamp_delay_a; else - nx_timestamp_delay_a <= (others => '0'); + nx_timestamp_delay_s <= nx_timestamp_delay_r; end if; - nx_timestamp_delay_actr <= nx_timestamp_delay_actr + 1; - end if; - -- Multiplexer - if (nx_timestamp_delay_adjust = '1') then - nx_timestamp_delay_s <= nx_timestamp_delay_a; - else - nx_timestamp_delay_s <= nx_timestamp_delay_r; + nx_timestamp_delay_s_last <= nx_timestamp_delay_s; + if (nx_timestamp_delay_s_last /= nx_timestamp_delay_s) then + reset_inhibit_ts_delay <= '1'; + end if; end if; end if; - end if; + end if; end process PROC_NX_TIMESTAMP_DELAY_ADJUST; ----------------------------------------------------------------------------- @@ -1805,16 +1733,16 @@ begin fifo_full_r <= '0'; fifo_empty_r <= '0'; nx_frame_synced_r <= '0'; - new_adc_dt_error_ctr_r <= (others => '0'); - new_timestamp_dt_error_ctr_r <= (others => '0'); + adc_dt_error_ctr_r <= (others => '0'); + timestamp_dt_error_ctr_r <= (others => '0'); adc_notlock_ctr_r <= (others => '0'); merge_error_ctr_r <= (others => '0'); else fifo_full_r <= fifo_full_rr; fifo_empty_r <= fifo_empty_rr; nx_frame_synced_r <= nx_frame_synced_rr; - new_adc_dt_error_ctr_r <= new_adc_dt_error_ctr; - new_timestamp_dt_error_ctr_r <= new_timestamp_dt_error_ctr; + adc_dt_error_ctr_r <= adc_dt_error_ctr; + timestamp_dt_error_ctr_r <= timestamp_dt_error_ctr; adc_notlock_ctr_r <= adc_notlock_ctr; merge_error_ctr_r <= merge_error_ctr; end if; @@ -1838,7 +1766,7 @@ begin pll_adc_sample_clk_finedelb_r <= (others => '0'); pll_adc_not_lock_ctr_clear <= '0'; nx_timestamp_delay_adjust <= '1'; - nx_timestamp_delay_r <= "010"; + nx_timestamp_delay_r <= "011"; reset_handler_start_r <= '0'; adc_debug_type_r <= (others => '0'); debug_mode <= (others => '0'); @@ -1848,6 +1776,8 @@ begin reset_inhibit_r <= '0'; disable_adc_resets <= '0'; disable_resets <= '0'; + + adc_reset_handler <= '0'; else slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -1857,7 +1787,8 @@ begin reset_parity_error_ctr <= '0'; pll_adc_not_lock_ctr_clear <= '0'; reset_handler_start_r <= '0'; - + adc_reset_handler <= '0'; + if (SLV_READ_IN = '1') then case SLV_ADDR_IN is when x"0000" => @@ -1958,13 +1889,13 @@ begin when x"000f" => slv_data_out_o(11 downto 0) <= - std_logic_vector(new_adc_dt_error_ctr_r); + std_logic_vector(adc_dt_error_ctr_r); slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; when x"0010" => slv_data_out_o(11 downto 0) <= - std_logic_vector(new_timestamp_dt_error_ctr_r); + std_logic_vector(timestamp_dt_error_ctr_r); slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; @@ -1995,6 +1926,10 @@ begin elsif (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is + when x"0000" => + adc_reset_handler <= '1'; + slv_ack_o <= '1'; + when x"0001" => reset_handler_start_r <= SLV_DATA_IN(0); disable_adc_resets <= SLV_DATA_IN(2); diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd index 947675c..2b51489 100644 --- a/nxyter/source/nx_trigger_generator.vhd +++ b/nxyter/source/nx_trigger_generator.vhd @@ -80,6 +80,7 @@ architecture Behavioral of nx_trigger_generator is signal slv_unknown_addr_o : std_logic; signal slv_ack_o : std_logic; signal pulser_trigger_period_r : unsigned(27 downto 0); + signal ignore_busy : std_logic; begin -- Debug Line @@ -193,14 +194,18 @@ begin else external_trigger <= '0'; external_trigger_busy <= '0'; - + case S_STATE is when S_IDLE => if (TRIGGER_BUSY_IN = '0' and external_trigger_i = '1') then - external_trigger_ctr <= "10100"; -- 20 external_trigger <= '1'; - S_STATE <= S_BUSY; + if (ignore_busy = '0') then + external_trigger_ctr <= "10100"; -- 20 + S_STATE <= S_BUSY; + else + S_STATE <= S_IDLE; + end if; else external_trigger_ctr <= (others => '0'); S_STATE <= S_IDLE; @@ -309,6 +314,7 @@ begin self_trigger_on <= SLV_DATA_IN(0); pulser_trigger_on <= SLV_DATA_IN(1); trigger_output_select <= SLV_DATA_IN(2); + ignore_busy <= SLV_DATA_IN(15); slv_ack_o <= '1'; when x"0001" => @@ -329,7 +335,9 @@ begin slv_data_out_o(0) <= self_trigger_on; slv_data_out_o(1) <= pulser_trigger_on; slv_data_out_o(2) <= trigger_output_select; - slv_data_out_o(31 downto 3) <= (others => '0'); + slv_data_out_o(14 downto 3) <= (others => '0'); + slv_data_out_o(15) <= ignore_busy; + slv_data_out_o(31 downto 16) <= (others => '0'); slv_ack_o <= '1'; when x"0001" => diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index fc798a8..8b831c1 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -808,6 +808,7 @@ component timer_static CLK_IN : in std_logic; RESET_IN : in std_logic; TIMER_START_IN : in std_logic; + TIMER_BUSY_OUT : out std_logic; TIMER_DONE_OUT : out std_logic ); end component; diff --git a/nxyter/source/timer_static.vhd b/nxyter/source/timer_static.vhd index 4451f88..118d3b3 100644 --- a/nxyter/source/timer_static.vhd +++ b/nxyter/source/timer_static.vhd @@ -13,6 +13,7 @@ entity timer_static is RESET_IN : in std_logic; TIMER_START_IN : in std_logic; + TIMER_BUSY_OUT : out std_logic; TIMER_DONE_OUT : out std_logic ); end entity; @@ -27,6 +28,7 @@ architecture Behavioral of timer_static is signal timer_ctr_x : unsigned(CTR_WIDTH - 1 downto 0); signal timer_ctr : unsigned(CTR_WIDTH - 1 downto 0); + signal timer_busy_o : std_logic; signal timer_done_o : std_logic; type STATES is (S_IDLE, @@ -60,13 +62,16 @@ begin timer_done_o <= '0'; if (TIMER_START_IN = '1') then timer_ctr_x <= ctr_limit - 1; + timer_busy_o <= '1'; NEXT_STATE <= S_COUNT; else timer_ctr_x <= (others => '0'); + timer_busy_o <= '0'; NEXT_STATE <= S_IDLE; end if; when S_COUNT => + timer_busy_o <= '1'; if (timer_ctr > to_unsigned(STEP_SIZE - 1, CTR_WIDTH)) then timer_ctr_x <= timer_ctr - to_unsigned(STEP_SIZE, CTR_WIDTH); timer_done_o <= '0'; @@ -85,6 +90,7 @@ begin -- Output Signals ----------------------------------------------------------------------------- + TIMER_busy_o <= timer_busy_o; TIMER_DONE_OUT <= timer_done_o; end Behavioral; diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index 7a22249..f88cadf 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -154,8 +154,9 @@ add_file -vhdl -lib "work" "cores/ram_dp_512x32.vhd" add_file -vhdl -lib "work" "cores/ram_fifo_delay_256x44.vhd" add_file -vhdl -lib "work" "cores/adc_ddr_generic.vhd" add_file -vhdl -lib "work" "cores/fifo_adc_48to48_dc.vhd" +add_file -vhdl -lib "work" "cores/fifo_adc_status_4to4_dc.vhd" add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" -add_file -vhdl -lib "work" "cores/dynamic_shift_register8x64.vhd" +add_file -vhdl -lib "work" "cores/dynamic_shift_register33x64.vhd" add_file -vhdl -lib "work" "../base/code/sedcheck.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 37d592d..4f99e4d 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -48,10 +48,7 @@ USE PRIMARY NET "clk_100_i_c"; USE PRIMARY NET "CLK_PCLK_RIGHT_c"; USE EDGE2EDGE NET "NX_CLK_ADC_DAT"; USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c"; - -#PRIORITIZE NET "NX1_DATA_CLK_IN_c" 40; -#PRIORITIZE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c" 50; - + ################################################################# # Reset Nets ################################################################# @@ -103,17 +100,15 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_s MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_dphase_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sampling_clk_reset*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_dt_error_ctr_r*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/timestamp_dt_error_ctr_*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_error_ctr_r*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_sclk_ok_f*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/disable_adc_f*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_error_status_i_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc_ad9228_data_handler*/adc_locked_o*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc0_sloppy_frame_c*" 200 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; @@ -128,6 +123,14 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_ MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 500 ns; + +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/disable_adc_f*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_error_status_i_*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc_ad9228_data_handler*/adc_locked_o*" 100 ns; + + MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ; MULTICYCLE TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ; MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ; diff --git a/nxyter/trb3_periph_multi.p2t b/nxyter/trb3_periph_multi.p2t index 157ed4e..5a26fc3 100644 --- a/nxyter/trb3_periph_multi.p2t +++ b/nxyter/trb3_periph_multi.p2t @@ -1,7 +1,7 @@ -w -i 2 -l 5 --n 20 +-n 5 -t 1 -s 1 -c 1 diff --git a/nxyter/trb3_periph_nxyter.lpf b/nxyter/trb3_periph_nxyter.lpf index bab9324..1a2437a 100644 --- a/nxyter/trb3_periph_nxyter.lpf +++ b/nxyter/trb3_periph_nxyter.lpf @@ -118,11 +118,11 @@ LOCATE COMP "NX1_TIMESTAMP_IN_0" SITE "K2"; #DQUL2_0 #50 LOCATE COMP "NX1_TIMESTAMP_IN_1" SITE "J4"; #DQUL2_2 #54 LOCATE COMP "NX1_TIMESTAMP_IN_2" SITE "D1"; #DQUL2_4 #58 LOCATE COMP "NX1_TIMESTAMP_IN_3" SITE "E1"; #DQUL2_6 #66 -LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L5"; #DQUL2_8 #70 +#LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L5"; #DQUL2_8 #70 LOCATE COMP "NX1_TIMESTAMP_IN_5" SITE "H2"; #DQUL3_0 #49 LOCATE COMP "NX1_TIMESTAMP_IN_6" SITE "K3"; #DQUL3_2 #53 LOCATE COMP "NX1_TIMESTAMP_IN_7" SITE "H1"; #DQUL3_4 #57 - +LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L2"; #DQUL3_6 # #DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP*" ; #IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;